1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License version 2 as published by
9  * the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef __ADRENO_GPU_H__
21 #define __ADRENO_GPU_H__
22 
23 #include <linux/firmware.h>
24 
25 #include "msm_gpu.h"
26 
27 #include "adreno_common.xml.h"
28 #include "adreno_pm4.xml.h"
29 
30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
31 #define REG_SKIP ~0
32 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
33 
34 /**
35  * adreno_regs: List of registers that are used in across all
36  * 3D devices. Each device type has different offset value for the same
37  * register, so an array of register offsets are declared for every device
38  * and are indexed by the enumeration values defined in this enum
39  */
40 enum adreno_regs {
41 	REG_ADRENO_CP_RB_BASE,
42 	REG_ADRENO_CP_RB_BASE_HI,
43 	REG_ADRENO_CP_RB_RPTR_ADDR,
44 	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
45 	REG_ADRENO_CP_RB_RPTR,
46 	REG_ADRENO_CP_RB_WPTR,
47 	REG_ADRENO_CP_RB_CNTL,
48 	REG_ADRENO_REGISTER_MAX,
49 };
50 
51 enum adreno_quirks {
52 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
53 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
54 };
55 
56 struct adreno_rev {
57 	uint8_t  core;
58 	uint8_t  major;
59 	uint8_t  minor;
60 	uint8_t  patchid;
61 };
62 
63 #define ADRENO_REV(core, major, minor, patchid) \
64 	((struct adreno_rev){ core, major, minor, patchid })
65 
66 struct adreno_gpu_funcs {
67 	struct msm_gpu_funcs base;
68 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
69 };
70 
71 struct adreno_info {
72 	struct adreno_rev rev;
73 	uint32_t revn;
74 	const char *name;
75 	const char *pm4fw, *pfpfw;
76 	const char *gpmufw;
77 	uint32_t gmem;
78 	enum adreno_quirks quirks;
79 	struct msm_gpu *(*init)(struct drm_device *dev);
80 	const char *zapfw;
81 };
82 
83 const struct adreno_info *adreno_info(struct adreno_rev rev);
84 
85 struct adreno_gpu {
86 	struct msm_gpu base;
87 	struct adreno_rev rev;
88 	const struct adreno_info *info;
89 	uint32_t gmem;  /* actual gmem size */
90 	uint32_t revn;  /* numeric revision name */
91 	const struct adreno_gpu_funcs *funcs;
92 
93 	/* interesting register offsets to dump: */
94 	const unsigned int *registers;
95 
96 	/*
97 	 * Are we loading fw from legacy path?  Prior to addition
98 	 * of gpu firmware to linux-firmware, the fw files were
99 	 * placed in toplevel firmware directory, following qcom's
100 	 * android kernel.  But linux-firmware preferred they be
101 	 * placed in a 'qcom' subdirectory.
102 	 *
103 	 * For backwards compatibility, we try first to load from
104 	 * the new path, using request_firmware_direct() to avoid
105 	 * any potential timeout waiting for usermode helper, then
106 	 * fall back to the old path (with direct load).  And
107 	 * finally fall back to request_firmware() with the new
108 	 * path to allow the usermode helper.
109 	 */
110 	enum {
111 		FW_LOCATION_UNKNOWN = 0,
112 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
113 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
114 		FW_LOCATION_HELPER,
115 	} fwloc;
116 
117 	/* firmware: */
118 	const struct firmware *pm4, *pfp;
119 
120 	/*
121 	 * Register offsets are different between some GPUs.
122 	 * GPU specific offsets will be exported by GPU specific
123 	 * code (a3xx_gpu.c) and stored in this common location.
124 	 */
125 	const unsigned int *reg_offsets;
126 };
127 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
128 
129 /* platform config data (ie. from DT, or pdata) */
130 struct adreno_platform_config {
131 	struct adreno_rev rev;
132 };
133 
134 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
135 
136 #define spin_until(X) ({                                   \
137 	int __ret = -ETIMEDOUT;                            \
138 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
139 	do {                                               \
140 		if (X) {                                   \
141 			__ret = 0;                         \
142 			break;                             \
143 		}                                          \
144 	} while (time_before(jiffies, __t));               \
145 	__ret;                                             \
146 })
147 
148 
149 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
150 {
151 	return (gpu->revn >= 300) && (gpu->revn < 400);
152 }
153 
154 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
155 {
156 	return gpu->revn == 305;
157 }
158 
159 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
160 {
161 	/* yes, 307, because a305c is 306 */
162 	return gpu->revn == 307;
163 }
164 
165 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
166 {
167 	return gpu->revn == 320;
168 }
169 
170 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
171 {
172 	return gpu->revn == 330;
173 }
174 
175 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
176 {
177 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
178 }
179 
180 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
181 {
182 	return (gpu->revn >= 400) && (gpu->revn < 500);
183 }
184 
185 static inline int adreno_is_a420(struct adreno_gpu *gpu)
186 {
187 	return gpu->revn == 420;
188 }
189 
190 static inline int adreno_is_a430(struct adreno_gpu *gpu)
191 {
192        return gpu->revn == 430;
193 }
194 
195 static inline int adreno_is_a530(struct adreno_gpu *gpu)
196 {
197 	return gpu->revn == 530;
198 }
199 
200 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
201 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
202 		const char *fwname);
203 int adreno_hw_init(struct msm_gpu *gpu);
204 void adreno_recover(struct msm_gpu *gpu);
205 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
206 		struct msm_file_private *ctx);
207 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
208 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
209 #ifdef CONFIG_DEBUG_FS
210 void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
211 #endif
212 void adreno_dump_info(struct msm_gpu *gpu);
213 void adreno_dump(struct msm_gpu *gpu);
214 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
215 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
216 
217 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
218 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
219 		int nr_rings);
220 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
221 
222 
223 /* ringbuffer helpers (the parts that are adreno specific) */
224 
225 static inline void
226 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
227 {
228 	adreno_wait_ring(ring, cnt+1);
229 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
230 }
231 
232 /* no-op packet: */
233 static inline void
234 OUT_PKT2(struct msm_ringbuffer *ring)
235 {
236 	adreno_wait_ring(ring, 1);
237 	OUT_RING(ring, CP_TYPE2_PKT);
238 }
239 
240 static inline void
241 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
242 {
243 	adreno_wait_ring(ring, cnt+1);
244 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
245 }
246 
247 static inline u32 PM4_PARITY(u32 val)
248 {
249 	return (0x9669 >> (0xF & (val ^
250 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
251 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
252 		(val >> 28)))) & 1;
253 }
254 
255 /* Maximum number of values that can be executed for one opcode */
256 #define TYPE4_MAX_PAYLOAD 127
257 
258 #define PKT4(_reg, _cnt) \
259 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
260 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
261 
262 static inline void
263 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
264 {
265 	adreno_wait_ring(ring, cnt + 1);
266 	OUT_RING(ring, PKT4(regindx, cnt));
267 }
268 
269 static inline void
270 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
271 {
272 	adreno_wait_ring(ring, cnt + 1);
273 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
274 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
275 }
276 
277 /*
278  * adreno_reg_check() - Checks the validity of a register enum
279  * @gpu:		Pointer to struct adreno_gpu
280  * @offset_name:	The register enum that is checked
281  */
282 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
283 		enum adreno_regs offset_name)
284 {
285 	if (offset_name >= REG_ADRENO_REGISTER_MAX ||
286 			!gpu->reg_offsets[offset_name]) {
287 		BUG();
288 	}
289 
290 	/*
291 	 * REG_SKIP is a special value that tell us that the register in
292 	 * question isn't implemented on target but don't trigger a BUG(). This
293 	 * is used to cleanly implement adreno_gpu_write64() and
294 	 * adreno_gpu_read64() in a generic fashion
295 	 */
296 	if (gpu->reg_offsets[offset_name] == REG_SKIP)
297 		return false;
298 
299 	return true;
300 }
301 
302 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
303 		enum adreno_regs offset_name)
304 {
305 	u32 reg = gpu->reg_offsets[offset_name];
306 	u32 val = 0;
307 	if(adreno_reg_check(gpu,offset_name))
308 		val = gpu_read(&gpu->base, reg - 1);
309 	return val;
310 }
311 
312 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
313 		enum adreno_regs offset_name, u32 data)
314 {
315 	u32 reg = gpu->reg_offsets[offset_name];
316 	if(adreno_reg_check(gpu, offset_name))
317 		gpu_write(&gpu->base, reg - 1, data);
318 }
319 
320 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
321 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
322 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
323 
324 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
325 		enum adreno_regs lo, enum adreno_regs hi, u64 data)
326 {
327 	adreno_gpu_write(gpu, lo, lower_32_bits(data));
328 	adreno_gpu_write(gpu, hi, upper_32_bits(data));
329 }
330 
331 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
332 {
333 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
334 }
335 
336 /*
337  * Given a register and a count, return a value to program into
338  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
339  * registers starting at _reg.
340  *
341  * The register base needs to be a multiple of the length. If it is not, the
342  * hardware will quietly mask off the bits for you and shift the size. For
343  * example, if you intend the protection to start at 0x07 for a length of 4
344  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
345  * expose registers you intended to protect!
346  */
347 #define ADRENO_PROTECT_RW(_reg, _len) \
348 	((1 << 30) | (1 << 29) | \
349 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
350 
351 /*
352  * Same as above, but allow reads over the range. For areas of mixed use (such
353  * as performance counters) this allows us to protect a much larger range with a
354  * single register
355  */
356 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
357 	((1 << 29) \
358 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
359 
360 #endif /* __ADRENO_GPU_H__ */
361