1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ADRENO_GPU_H__ 21 #define __ADRENO_GPU_H__ 22 23 #include <linux/firmware.h> 24 25 #include "msm_gpu.h" 26 27 #include "adreno_common.xml.h" 28 #include "adreno_pm4.xml.h" 29 30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 31 #define REG_SKIP ~0 32 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP 33 34 /** 35 * adreno_regs: List of registers that are used in across all 36 * 3D devices. Each device type has different offset value for the same 37 * register, so an array of register offsets are declared for every device 38 * and are indexed by the enumeration values defined in this enum 39 */ 40 enum adreno_regs { 41 REG_ADRENO_CP_RB_BASE, 42 REG_ADRENO_CP_RB_BASE_HI, 43 REG_ADRENO_CP_RB_RPTR_ADDR, 44 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 45 REG_ADRENO_CP_RB_RPTR, 46 REG_ADRENO_CP_RB_WPTR, 47 REG_ADRENO_CP_RB_CNTL, 48 REG_ADRENO_REGISTER_MAX, 49 }; 50 51 enum adreno_quirks { 52 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, 53 ADRENO_QUIRK_FAULT_DETECT_MASK = 2, 54 }; 55 56 struct adreno_rev { 57 uint8_t core; 58 uint8_t major; 59 uint8_t minor; 60 uint8_t patchid; 61 }; 62 63 #define ADRENO_REV(core, major, minor, patchid) \ 64 ((struct adreno_rev){ core, major, minor, patchid }) 65 66 struct adreno_gpu_funcs { 67 struct msm_gpu_funcs base; 68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 69 }; 70 71 struct adreno_info { 72 struct adreno_rev rev; 73 uint32_t revn; 74 const char *name; 75 const char *pm4fw, *pfpfw; 76 const char *gpmufw; 77 uint32_t gmem; 78 enum adreno_quirks quirks; 79 struct msm_gpu *(*init)(struct drm_device *dev); 80 const char *zapfw; 81 }; 82 83 const struct adreno_info *adreno_info(struct adreno_rev rev); 84 85 struct adreno_gpu { 86 struct msm_gpu base; 87 struct adreno_rev rev; 88 const struct adreno_info *info; 89 uint32_t gmem; /* actual gmem size */ 90 uint32_t revn; /* numeric revision name */ 91 const struct adreno_gpu_funcs *funcs; 92 93 /* interesting register offsets to dump: */ 94 const unsigned int *registers; 95 96 /* 97 * Are we loading fw from legacy path? Prior to addition 98 * of gpu firmware to linux-firmware, the fw files were 99 * placed in toplevel firmware directory, following qcom's 100 * android kernel. But linux-firmware preferred they be 101 * placed in a 'qcom' subdirectory. 102 * 103 * For backwards compatibility, we try first to load from 104 * the new path, using request_firmware_direct() to avoid 105 * any potential timeout waiting for usermode helper, then 106 * fall back to the old path (with direct load). And 107 * finally fall back to request_firmware() with the new 108 * path to allow the usermode helper. 109 */ 110 enum { 111 FW_LOCATION_UNKNOWN = 0, 112 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 113 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 114 FW_LOCATION_HELPER, 115 } fwloc; 116 117 /* firmware: */ 118 const struct firmware *pm4, *pfp; 119 120 /* 121 * Register offsets are different between some GPUs. 122 * GPU specific offsets will be exported by GPU specific 123 * code (a3xx_gpu.c) and stored in this common location. 124 */ 125 const unsigned int *reg_offsets; 126 }; 127 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 128 129 /* platform config data (ie. from DT, or pdata) */ 130 struct adreno_platform_config { 131 struct adreno_rev rev; 132 uint32_t fast_rate, bus_freq; 133 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING 134 struct msm_bus_scale_pdata *bus_scale_table; 135 #endif 136 }; 137 138 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 139 140 #define spin_until(X) ({ \ 141 int __ret = -ETIMEDOUT; \ 142 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 143 do { \ 144 if (X) { \ 145 __ret = 0; \ 146 break; \ 147 } \ 148 } while (time_before(jiffies, __t)); \ 149 __ret; \ 150 }) 151 152 153 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) 154 { 155 return (gpu->revn >= 300) && (gpu->revn < 400); 156 } 157 158 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 159 { 160 return gpu->revn == 305; 161 } 162 163 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 164 { 165 /* yes, 307, because a305c is 306 */ 166 return gpu->revn == 307; 167 } 168 169 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 170 { 171 return gpu->revn == 320; 172 } 173 174 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 175 { 176 return gpu->revn == 330; 177 } 178 179 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 180 { 181 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 182 } 183 184 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 185 { 186 return (gpu->revn >= 400) && (gpu->revn < 500); 187 } 188 189 static inline int adreno_is_a420(struct adreno_gpu *gpu) 190 { 191 return gpu->revn == 420; 192 } 193 194 static inline int adreno_is_a430(struct adreno_gpu *gpu) 195 { 196 return gpu->revn == 430; 197 } 198 199 static inline int adreno_is_a530(struct adreno_gpu *gpu) 200 { 201 return gpu->revn == 530; 202 } 203 204 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 205 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 206 const char *fwname); 207 int adreno_hw_init(struct msm_gpu *gpu); 208 void adreno_recover(struct msm_gpu *gpu); 209 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 210 struct msm_file_private *ctx); 211 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 212 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 213 #ifdef CONFIG_DEBUG_FS 214 void adreno_show(struct msm_gpu *gpu, struct seq_file *m); 215 #endif 216 void adreno_dump_info(struct msm_gpu *gpu); 217 void adreno_dump(struct msm_gpu *gpu); 218 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 219 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 220 221 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 222 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 223 int nr_rings); 224 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 225 226 227 /* ringbuffer helpers (the parts that are adreno specific) */ 228 229 static inline void 230 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 231 { 232 adreno_wait_ring(ring, cnt+1); 233 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 234 } 235 236 /* no-op packet: */ 237 static inline void 238 OUT_PKT2(struct msm_ringbuffer *ring) 239 { 240 adreno_wait_ring(ring, 1); 241 OUT_RING(ring, CP_TYPE2_PKT); 242 } 243 244 static inline void 245 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 246 { 247 adreno_wait_ring(ring, cnt+1); 248 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 249 } 250 251 static inline u32 PM4_PARITY(u32 val) 252 { 253 return (0x9669 >> (0xF & (val ^ 254 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 255 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 256 (val >> 28)))) & 1; 257 } 258 259 /* Maximum number of values that can be executed for one opcode */ 260 #define TYPE4_MAX_PAYLOAD 127 261 262 #define PKT4(_reg, _cnt) \ 263 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 264 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 265 266 static inline void 267 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 268 { 269 adreno_wait_ring(ring, cnt + 1); 270 OUT_RING(ring, PKT4(regindx, cnt)); 271 } 272 273 static inline void 274 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 275 { 276 adreno_wait_ring(ring, cnt + 1); 277 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 278 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 279 } 280 281 /* 282 * adreno_reg_check() - Checks the validity of a register enum 283 * @gpu: Pointer to struct adreno_gpu 284 * @offset_name: The register enum that is checked 285 */ 286 static inline bool adreno_reg_check(struct adreno_gpu *gpu, 287 enum adreno_regs offset_name) 288 { 289 if (offset_name >= REG_ADRENO_REGISTER_MAX || 290 !gpu->reg_offsets[offset_name]) { 291 BUG(); 292 } 293 294 /* 295 * REG_SKIP is a special value that tell us that the register in 296 * question isn't implemented on target but don't trigger a BUG(). This 297 * is used to cleanly implement adreno_gpu_write64() and 298 * adreno_gpu_read64() in a generic fashion 299 */ 300 if (gpu->reg_offsets[offset_name] == REG_SKIP) 301 return false; 302 303 return true; 304 } 305 306 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu, 307 enum adreno_regs offset_name) 308 { 309 u32 reg = gpu->reg_offsets[offset_name]; 310 u32 val = 0; 311 if(adreno_reg_check(gpu,offset_name)) 312 val = gpu_read(&gpu->base, reg - 1); 313 return val; 314 } 315 316 static inline void adreno_gpu_write(struct adreno_gpu *gpu, 317 enum adreno_regs offset_name, u32 data) 318 { 319 u32 reg = gpu->reg_offsets[offset_name]; 320 if(adreno_reg_check(gpu, offset_name)) 321 gpu_write(&gpu->base, reg - 1, data); 322 } 323 324 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 325 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 326 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 327 328 static inline void adreno_gpu_write64(struct adreno_gpu *gpu, 329 enum adreno_regs lo, enum adreno_regs hi, u64 data) 330 { 331 adreno_gpu_write(gpu, lo, lower_32_bits(data)); 332 adreno_gpu_write(gpu, hi, upper_32_bits(data)); 333 } 334 335 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 336 { 337 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 338 } 339 340 /* 341 * Given a register and a count, return a value to program into 342 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 343 * registers starting at _reg. 344 * 345 * The register base needs to be a multiple of the length. If it is not, the 346 * hardware will quietly mask off the bits for you and shift the size. For 347 * example, if you intend the protection to start at 0x07 for a length of 4 348 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 349 * expose registers you intended to protect! 350 */ 351 #define ADRENO_PROTECT_RW(_reg, _len) \ 352 ((1 << 30) | (1 << 29) | \ 353 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 354 355 /* 356 * Same as above, but allow reads over the range. For areas of mixed use (such 357 * as performance counters) this allows us to protect a much larger range with a 358 * single register 359 */ 360 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 361 ((1 << 29) \ 362 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 363 364 #endif /* __ADRENO_GPU_H__ */ 365