1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 enum adreno_quirks {
33 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
34 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
35 	ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
36 };
37 
38 struct adreno_rev {
39 	uint8_t  core;
40 	uint8_t  major;
41 	uint8_t  minor;
42 	uint8_t  patchid;
43 };
44 
45 #define ANY_ID 0xff
46 
47 #define ADRENO_REV(core, major, minor, patchid) \
48 	((struct adreno_rev){ core, major, minor, patchid })
49 
50 struct adreno_gpu_funcs {
51 	struct msm_gpu_funcs base;
52 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
53 };
54 
55 struct adreno_reglist {
56 	u32 offset;
57 	u32 value;
58 };
59 
60 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
61 
62 struct adreno_info {
63 	struct adreno_rev rev;
64 	uint32_t revn;
65 	const char *name;
66 	const char *fw[ADRENO_FW_MAX];
67 	uint32_t gmem;
68 	enum adreno_quirks quirks;
69 	struct msm_gpu *(*init)(struct drm_device *dev);
70 	const char *zapfw;
71 	u32 inactive_period;
72 	const struct adreno_reglist *hwcg;
73 	u64 address_space_size;
74 };
75 
76 const struct adreno_info *adreno_info(struct adreno_rev rev);
77 
78 struct adreno_gpu {
79 	struct msm_gpu base;
80 	struct adreno_rev rev;
81 	const struct adreno_info *info;
82 	uint32_t gmem;  /* actual gmem size */
83 	uint32_t revn;  /* numeric revision name */
84 	uint16_t speedbin;
85 	const struct adreno_gpu_funcs *funcs;
86 
87 	/* interesting register offsets to dump: */
88 	const unsigned int *registers;
89 
90 	/*
91 	 * Are we loading fw from legacy path?  Prior to addition
92 	 * of gpu firmware to linux-firmware, the fw files were
93 	 * placed in toplevel firmware directory, following qcom's
94 	 * android kernel.  But linux-firmware preferred they be
95 	 * placed in a 'qcom' subdirectory.
96 	 *
97 	 * For backwards compatibility, we try first to load from
98 	 * the new path, using request_firmware_direct() to avoid
99 	 * any potential timeout waiting for usermode helper, then
100 	 * fall back to the old path (with direct load).  And
101 	 * finally fall back to request_firmware() with the new
102 	 * path to allow the usermode helper.
103 	 */
104 	enum {
105 		FW_LOCATION_UNKNOWN = 0,
106 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
107 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
108 		FW_LOCATION_HELPER,
109 	} fwloc;
110 
111 	/* firmware: */
112 	const struct firmware *fw[ADRENO_FW_MAX];
113 
114 	/*
115 	 * Register offsets are different between some GPUs.
116 	 * GPU specific offsets will be exported by GPU specific
117 	 * code (a3xx_gpu.c) and stored in this common location.
118 	 */
119 	const unsigned int *reg_offsets;
120 };
121 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
122 
123 struct adreno_ocmem {
124 	struct ocmem *ocmem;
125 	unsigned long base;
126 	void *hdl;
127 };
128 
129 /* platform config data (ie. from DT, or pdata) */
130 struct adreno_platform_config {
131 	struct adreno_rev rev;
132 };
133 
134 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
135 
136 #define spin_until(X) ({                                   \
137 	int __ret = -ETIMEDOUT;                            \
138 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
139 	do {                                               \
140 		if (X) {                                   \
141 			__ret = 0;                         \
142 			break;                             \
143 		}                                          \
144 	} while (time_before(jiffies, __t));               \
145 	__ret;                                             \
146 })
147 
148 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
149 
150 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
151 {
152 	return (gpu->revn < 300);
153 }
154 
155 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
156 {
157 	return (gpu->revn < 210);
158 }
159 
160 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
161 {
162 	return gpu->revn == 225;
163 }
164 
165 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
166 {
167 	return gpu->revn == 305;
168 }
169 
170 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
171 {
172 	/* yes, 307, because a305c is 306 */
173 	return gpu->revn == 307;
174 }
175 
176 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
177 {
178 	return gpu->revn == 320;
179 }
180 
181 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
182 {
183 	return gpu->revn == 330;
184 }
185 
186 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
187 {
188 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
189 }
190 
191 static inline int adreno_is_a405(struct adreno_gpu *gpu)
192 {
193 	return gpu->revn == 405;
194 }
195 
196 static inline int adreno_is_a420(struct adreno_gpu *gpu)
197 {
198 	return gpu->revn == 420;
199 }
200 
201 static inline int adreno_is_a430(struct adreno_gpu *gpu)
202 {
203 	return gpu->revn == 430;
204 }
205 
206 static inline int adreno_is_a506(struct adreno_gpu *gpu)
207 {
208 	return gpu->revn == 506;
209 }
210 
211 static inline int adreno_is_a508(struct adreno_gpu *gpu)
212 {
213 	return gpu->revn == 508;
214 }
215 
216 static inline int adreno_is_a509(struct adreno_gpu *gpu)
217 {
218 	return gpu->revn == 509;
219 }
220 
221 static inline int adreno_is_a510(struct adreno_gpu *gpu)
222 {
223 	return gpu->revn == 510;
224 }
225 
226 static inline int adreno_is_a512(struct adreno_gpu *gpu)
227 {
228 	return gpu->revn == 512;
229 }
230 
231 static inline int adreno_is_a530(struct adreno_gpu *gpu)
232 {
233 	return gpu->revn == 530;
234 }
235 
236 static inline int adreno_is_a540(struct adreno_gpu *gpu)
237 {
238 	return gpu->revn == 540;
239 }
240 
241 static inline int adreno_is_a618(struct adreno_gpu *gpu)
242 {
243 	return gpu->revn == 618;
244 }
245 
246 static inline int adreno_is_a619(struct adreno_gpu *gpu)
247 {
248 	return gpu->revn == 619;
249 }
250 
251 static inline int adreno_is_a630(struct adreno_gpu *gpu)
252 {
253 	return gpu->revn == 630;
254 }
255 
256 static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
257 {
258 	return (gpu->revn == 640) || (gpu->revn == 680);
259 }
260 
261 static inline int adreno_is_a650(struct adreno_gpu *gpu)
262 {
263 	return gpu->revn == 650;
264 }
265 
266 static inline int adreno_is_7c3(struct adreno_gpu *gpu)
267 {
268 	/* The order of args is important here to handle ANY_ID correctly */
269 	return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
270 }
271 
272 static inline int adreno_is_a660(struct adreno_gpu *gpu)
273 {
274 	return gpu->revn == 660;
275 }
276 
277 /* check for a615, a616, a618, a619 or any derivatives */
278 static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
279 {
280 	return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619;
281 }
282 
283 static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
284 {
285 	return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
286 }
287 
288 /* check for a650, a660, or any derivatives */
289 static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
290 {
291 	return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
292 }
293 
294 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
295 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
296 		     uint32_t param, uint64_t *value, uint32_t *len);
297 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
298 		     uint32_t param, uint64_t value, uint32_t len);
299 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
300 		const char *fwname);
301 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
302 		const struct firmware *fw, u64 *iova);
303 int adreno_hw_init(struct msm_gpu *gpu);
304 void adreno_recover(struct msm_gpu *gpu);
305 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
306 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
307 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
308 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
309 		struct drm_printer *p);
310 #endif
311 void adreno_dump_info(struct msm_gpu *gpu);
312 void adreno_dump(struct msm_gpu *gpu);
313 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
314 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
315 
316 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
317 			  struct adreno_ocmem *ocmem);
318 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
319 
320 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
321 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
322 		int nr_rings);
323 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
324 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
325 
326 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
327 
328 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
329 int adreno_gpu_state_put(struct msm_gpu_state *state);
330 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
331 		bool *encoded);
332 
333 /*
334  * Common helper function to initialize the default address space for arm-smmu
335  * attached targets
336  */
337 struct msm_gem_address_space *
338 adreno_iommu_create_address_space(struct msm_gpu *gpu,
339 		struct platform_device *pdev);
340 
341 void adreno_set_llc_attributes(struct iommu_domain *iommu);
342 
343 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
344 
345 /*
346  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
347  * out of secure mode
348  */
349 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
350 
351 /* ringbuffer helpers (the parts that are adreno specific) */
352 
353 static inline void
354 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
355 {
356 	adreno_wait_ring(ring, cnt+1);
357 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
358 }
359 
360 /* no-op packet: */
361 static inline void
362 OUT_PKT2(struct msm_ringbuffer *ring)
363 {
364 	adreno_wait_ring(ring, 1);
365 	OUT_RING(ring, CP_TYPE2_PKT);
366 }
367 
368 static inline void
369 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
370 {
371 	adreno_wait_ring(ring, cnt+1);
372 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
373 }
374 
375 static inline u32 PM4_PARITY(u32 val)
376 {
377 	return (0x9669 >> (0xF & (val ^
378 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
379 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
380 		(val >> 28)))) & 1;
381 }
382 
383 /* Maximum number of values that can be executed for one opcode */
384 #define TYPE4_MAX_PAYLOAD 127
385 
386 #define PKT4(_reg, _cnt) \
387 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
388 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
389 
390 static inline void
391 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
392 {
393 	adreno_wait_ring(ring, cnt + 1);
394 	OUT_RING(ring, PKT4(regindx, cnt));
395 }
396 
397 static inline void
398 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
399 {
400 	adreno_wait_ring(ring, cnt + 1);
401 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
402 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
403 }
404 
405 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
406 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
407 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
408 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
409 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
410 
411 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
412 {
413 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
414 }
415 
416 /*
417  * Given a register and a count, return a value to program into
418  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
419  * registers starting at _reg.
420  *
421  * The register base needs to be a multiple of the length. If it is not, the
422  * hardware will quietly mask off the bits for you and shift the size. For
423  * example, if you intend the protection to start at 0x07 for a length of 4
424  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
425  * expose registers you intended to protect!
426  */
427 #define ADRENO_PROTECT_RW(_reg, _len) \
428 	((1 << 30) | (1 << 29) | \
429 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
430 
431 /*
432  * Same as above, but allow reads over the range. For areas of mixed use (such
433  * as performance counters) this allows us to protect a much larger range with a
434  * single register
435  */
436 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
437 	((1 << 29) \
438 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
439 
440 
441 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
442 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
443 		interval, timeout)
444 
445 #endif /* __ADRENO_GPU_H__ */
446