1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #ifndef __ADRENO_GPU_H__ 10 #define __ADRENO_GPU_H__ 11 12 #include <linux/firmware.h> 13 #include <linux/iopoll.h> 14 15 #include "msm_gpu.h" 16 17 #include "adreno_common.xml.h" 18 #include "adreno_pm4.xml.h" 19 20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 21 #define REG_SKIP ~0 22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP 23 24 /** 25 * adreno_regs: List of registers that are used in across all 26 * 3D devices. Each device type has different offset value for the same 27 * register, so an array of register offsets are declared for every device 28 * and are indexed by the enumeration values defined in this enum 29 */ 30 enum adreno_regs { 31 REG_ADRENO_CP_RB_BASE, 32 REG_ADRENO_CP_RB_BASE_HI, 33 REG_ADRENO_CP_RB_RPTR_ADDR, 34 REG_ADRENO_CP_RB_RPTR_ADDR_HI, 35 REG_ADRENO_CP_RB_RPTR, 36 REG_ADRENO_CP_RB_WPTR, 37 REG_ADRENO_CP_RB_CNTL, 38 REG_ADRENO_REGISTER_MAX, 39 }; 40 41 enum { 42 ADRENO_FW_PM4 = 0, 43 ADRENO_FW_SQE = 0, /* a6xx */ 44 ADRENO_FW_PFP = 1, 45 ADRENO_FW_GMU = 1, /* a6xx */ 46 ADRENO_FW_GPMU = 2, 47 ADRENO_FW_MAX, 48 }; 49 50 enum adreno_quirks { 51 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1, 52 ADRENO_QUIRK_FAULT_DETECT_MASK = 2, 53 ADRENO_QUIRK_LMLOADKILL_DISABLE = 3, 54 }; 55 56 struct adreno_rev { 57 uint8_t core; 58 uint8_t major; 59 uint8_t minor; 60 uint8_t patchid; 61 }; 62 63 #define ADRENO_REV(core, major, minor, patchid) \ 64 ((struct adreno_rev){ core, major, minor, patchid }) 65 66 struct adreno_gpu_funcs { 67 struct msm_gpu_funcs base; 68 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); 69 }; 70 71 struct adreno_info { 72 struct adreno_rev rev; 73 uint32_t revn; 74 const char *name; 75 const char *fw[ADRENO_FW_MAX]; 76 uint32_t gmem; 77 enum adreno_quirks quirks; 78 struct msm_gpu *(*init)(struct drm_device *dev); 79 const char *zapfw; 80 u32 inactive_period; 81 }; 82 83 const struct adreno_info *adreno_info(struct adreno_rev rev); 84 85 struct adreno_gpu { 86 struct msm_gpu base; 87 struct adreno_rev rev; 88 const struct adreno_info *info; 89 uint32_t gmem; /* actual gmem size */ 90 uint32_t revn; /* numeric revision name */ 91 const struct adreno_gpu_funcs *funcs; 92 93 /* interesting register offsets to dump: */ 94 const unsigned int *registers; 95 96 /* 97 * Are we loading fw from legacy path? Prior to addition 98 * of gpu firmware to linux-firmware, the fw files were 99 * placed in toplevel firmware directory, following qcom's 100 * android kernel. But linux-firmware preferred they be 101 * placed in a 'qcom' subdirectory. 102 * 103 * For backwards compatibility, we try first to load from 104 * the new path, using request_firmware_direct() to avoid 105 * any potential timeout waiting for usermode helper, then 106 * fall back to the old path (with direct load). And 107 * finally fall back to request_firmware() with the new 108 * path to allow the usermode helper. 109 */ 110 enum { 111 FW_LOCATION_UNKNOWN = 0, 112 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */ 113 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */ 114 FW_LOCATION_HELPER, 115 } fwloc; 116 117 /* firmware: */ 118 const struct firmware *fw[ADRENO_FW_MAX]; 119 120 /* 121 * Register offsets are different between some GPUs. 122 * GPU specific offsets will be exported by GPU specific 123 * code (a3xx_gpu.c) and stored in this common location. 124 */ 125 const unsigned int *reg_offsets; 126 }; 127 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base) 128 129 /* platform config data (ie. from DT, or pdata) */ 130 struct adreno_platform_config { 131 struct adreno_rev rev; 132 }; 133 134 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) 135 136 #define spin_until(X) ({ \ 137 int __ret = -ETIMEDOUT; \ 138 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \ 139 do { \ 140 if (X) { \ 141 __ret = 0; \ 142 break; \ 143 } \ 144 } while (time_before(jiffies, __t)); \ 145 __ret; \ 146 }) 147 148 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu) 149 { 150 return (gpu->revn < 300); 151 } 152 153 static inline bool adreno_is_a20x(struct adreno_gpu *gpu) 154 { 155 return (gpu->revn < 210); 156 } 157 158 static inline bool adreno_is_a225(struct adreno_gpu *gpu) 159 { 160 return gpu->revn == 225; 161 } 162 163 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu) 164 { 165 return (gpu->revn >= 300) && (gpu->revn < 400); 166 } 167 168 static inline bool adreno_is_a305(struct adreno_gpu *gpu) 169 { 170 return gpu->revn == 305; 171 } 172 173 static inline bool adreno_is_a306(struct adreno_gpu *gpu) 174 { 175 /* yes, 307, because a305c is 306 */ 176 return gpu->revn == 307; 177 } 178 179 static inline bool adreno_is_a320(struct adreno_gpu *gpu) 180 { 181 return gpu->revn == 320; 182 } 183 184 static inline bool adreno_is_a330(struct adreno_gpu *gpu) 185 { 186 return gpu->revn == 330; 187 } 188 189 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu) 190 { 191 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); 192 } 193 194 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) 195 { 196 return (gpu->revn >= 400) && (gpu->revn < 500); 197 } 198 199 static inline int adreno_is_a420(struct adreno_gpu *gpu) 200 { 201 return gpu->revn == 420; 202 } 203 204 static inline int adreno_is_a430(struct adreno_gpu *gpu) 205 { 206 return gpu->revn == 430; 207 } 208 209 static inline int adreno_is_a530(struct adreno_gpu *gpu) 210 { 211 return gpu->revn == 530; 212 } 213 214 static inline int adreno_is_a540(struct adreno_gpu *gpu) 215 { 216 return gpu->revn == 540; 217 } 218 219 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 220 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, 221 const char *fwname); 222 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 223 const struct firmware *fw, u64 *iova); 224 int adreno_hw_init(struct msm_gpu *gpu); 225 void adreno_recover(struct msm_gpu *gpu); 226 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 227 struct msm_file_private *ctx); 228 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 229 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 230 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 231 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 232 struct drm_printer *p); 233 #endif 234 void adreno_dump_info(struct msm_gpu *gpu); 235 void adreno_dump(struct msm_gpu *gpu); 236 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords); 237 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu); 238 239 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 240 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, 241 int nr_rings); 242 void adreno_gpu_cleanup(struct adreno_gpu *gpu); 243 int adreno_load_fw(struct adreno_gpu *adreno_gpu); 244 245 void adreno_gpu_state_destroy(struct msm_gpu_state *state); 246 247 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state); 248 int adreno_gpu_state_put(struct msm_gpu_state *state); 249 250 /* 251 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU 252 * out of secure mode 253 */ 254 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid); 255 256 /* ringbuffer helpers (the parts that are adreno specific) */ 257 258 static inline void 259 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 260 { 261 adreno_wait_ring(ring, cnt+1); 262 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); 263 } 264 265 /* no-op packet: */ 266 static inline void 267 OUT_PKT2(struct msm_ringbuffer *ring) 268 { 269 adreno_wait_ring(ring, 1); 270 OUT_RING(ring, CP_TYPE2_PKT); 271 } 272 273 static inline void 274 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 275 { 276 adreno_wait_ring(ring, cnt+1); 277 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); 278 } 279 280 static inline u32 PM4_PARITY(u32 val) 281 { 282 return (0x9669 >> (0xF & (val ^ 283 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^ 284 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^ 285 (val >> 28)))) & 1; 286 } 287 288 /* Maximum number of values that can be executed for one opcode */ 289 #define TYPE4_MAX_PAYLOAD 127 290 291 #define PKT4(_reg, _cnt) \ 292 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \ 293 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27)) 294 295 static inline void 296 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt) 297 { 298 adreno_wait_ring(ring, cnt + 1); 299 OUT_RING(ring, PKT4(regindx, cnt)); 300 } 301 302 static inline void 303 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt) 304 { 305 adreno_wait_ring(ring, cnt + 1); 306 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | 307 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23)); 308 } 309 310 /* 311 * adreno_reg_check() - Checks the validity of a register enum 312 * @gpu: Pointer to struct adreno_gpu 313 * @offset_name: The register enum that is checked 314 */ 315 static inline bool adreno_reg_check(struct adreno_gpu *gpu, 316 enum adreno_regs offset_name) 317 { 318 if (offset_name >= REG_ADRENO_REGISTER_MAX || 319 !gpu->reg_offsets[offset_name]) { 320 BUG(); 321 } 322 323 /* 324 * REG_SKIP is a special value that tell us that the register in 325 * question isn't implemented on target but don't trigger a BUG(). This 326 * is used to cleanly implement adreno_gpu_write64() and 327 * adreno_gpu_read64() in a generic fashion 328 */ 329 if (gpu->reg_offsets[offset_name] == REG_SKIP) 330 return false; 331 332 return true; 333 } 334 335 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu, 336 enum adreno_regs offset_name) 337 { 338 u32 reg = gpu->reg_offsets[offset_name]; 339 u32 val = 0; 340 if(adreno_reg_check(gpu,offset_name)) 341 val = gpu_read(&gpu->base, reg - 1); 342 return val; 343 } 344 345 static inline void adreno_gpu_write(struct adreno_gpu *gpu, 346 enum adreno_regs offset_name, u32 data) 347 { 348 u32 reg = gpu->reg_offsets[offset_name]; 349 if(adreno_reg_check(gpu, offset_name)) 350 gpu_write(&gpu->base, reg - 1, data); 351 } 352 353 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev); 354 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 355 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev); 356 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev); 357 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev); 358 359 static inline void adreno_gpu_write64(struct adreno_gpu *gpu, 360 enum adreno_regs lo, enum adreno_regs hi, u64 data) 361 { 362 adreno_gpu_write(gpu, lo, lower_32_bits(data)); 363 adreno_gpu_write(gpu, hi, upper_32_bits(data)); 364 } 365 366 static inline uint32_t get_wptr(struct msm_ringbuffer *ring) 367 { 368 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2); 369 } 370 371 /* 372 * Given a register and a count, return a value to program into 373 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len 374 * registers starting at _reg. 375 * 376 * The register base needs to be a multiple of the length. If it is not, the 377 * hardware will quietly mask off the bits for you and shift the size. For 378 * example, if you intend the protection to start at 0x07 for a length of 4 379 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might 380 * expose registers you intended to protect! 381 */ 382 #define ADRENO_PROTECT_RW(_reg, _len) \ 383 ((1 << 30) | (1 << 29) | \ 384 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 385 386 /* 387 * Same as above, but allow reads over the range. For areas of mixed use (such 388 * as performance counters) this allows us to protect a much larger range with a 389 * single register 390 */ 391 #define ADRENO_PROTECT_RDONLY(_reg, _len) \ 392 ((1 << 29) \ 393 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF)) 394 395 396 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ 397 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \ 398 interval, timeout) 399 400 #endif /* __ADRENO_GPU_H__ */ 401