1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
22 
23 enum {
24 	ADRENO_FW_PM4 = 0,
25 	ADRENO_FW_SQE = 0, /* a6xx */
26 	ADRENO_FW_PFP = 1,
27 	ADRENO_FW_GMU = 1, /* a6xx */
28 	ADRENO_FW_GPMU = 2,
29 	ADRENO_FW_MAX,
30 };
31 
32 enum adreno_quirks {
33 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
34 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
35 	ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
36 };
37 
38 struct adreno_rev {
39 	uint8_t  core;
40 	uint8_t  major;
41 	uint8_t  minor;
42 	uint8_t  patchid;
43 };
44 
45 #define ADRENO_REV(core, major, minor, patchid) \
46 	((struct adreno_rev){ core, major, minor, patchid })
47 
48 struct adreno_gpu_funcs {
49 	struct msm_gpu_funcs base;
50 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
51 };
52 
53 struct adreno_reglist {
54 	u32 offset;
55 	u32 value;
56 };
57 
58 extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
59 
60 struct adreno_info {
61 	struct adreno_rev rev;
62 	uint32_t revn;
63 	const char *name;
64 	const char *fw[ADRENO_FW_MAX];
65 	uint32_t gmem;
66 	enum adreno_quirks quirks;
67 	struct msm_gpu *(*init)(struct drm_device *dev);
68 	const char *zapfw;
69 	u32 inactive_period;
70 	const struct adreno_reglist *hwcg;
71 };
72 
73 const struct adreno_info *adreno_info(struct adreno_rev rev);
74 
75 struct adreno_gpu {
76 	struct msm_gpu base;
77 	struct adreno_rev rev;
78 	const struct adreno_info *info;
79 	uint32_t gmem;  /* actual gmem size */
80 	uint32_t revn;  /* numeric revision name */
81 	const struct adreno_gpu_funcs *funcs;
82 
83 	/* interesting register offsets to dump: */
84 	const unsigned int *registers;
85 
86 	/*
87 	 * Are we loading fw from legacy path?  Prior to addition
88 	 * of gpu firmware to linux-firmware, the fw files were
89 	 * placed in toplevel firmware directory, following qcom's
90 	 * android kernel.  But linux-firmware preferred they be
91 	 * placed in a 'qcom' subdirectory.
92 	 *
93 	 * For backwards compatibility, we try first to load from
94 	 * the new path, using request_firmware_direct() to avoid
95 	 * any potential timeout waiting for usermode helper, then
96 	 * fall back to the old path (with direct load).  And
97 	 * finally fall back to request_firmware() with the new
98 	 * path to allow the usermode helper.
99 	 */
100 	enum {
101 		FW_LOCATION_UNKNOWN = 0,
102 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
103 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
104 		FW_LOCATION_HELPER,
105 	} fwloc;
106 
107 	/* firmware: */
108 	const struct firmware *fw[ADRENO_FW_MAX];
109 
110 	/*
111 	 * Register offsets are different between some GPUs.
112 	 * GPU specific offsets will be exported by GPU specific
113 	 * code (a3xx_gpu.c) and stored in this common location.
114 	 */
115 	const unsigned int *reg_offsets;
116 };
117 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
118 
119 struct adreno_ocmem {
120 	struct ocmem *ocmem;
121 	unsigned long base;
122 	void *hdl;
123 };
124 
125 /* platform config data (ie. from DT, or pdata) */
126 struct adreno_platform_config {
127 	struct adreno_rev rev;
128 };
129 
130 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
131 
132 #define spin_until(X) ({                                   \
133 	int __ret = -ETIMEDOUT;                            \
134 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
135 	do {                                               \
136 		if (X) {                                   \
137 			__ret = 0;                         \
138 			break;                             \
139 		}                                          \
140 	} while (time_before(jiffies, __t));               \
141 	__ret;                                             \
142 })
143 
144 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
145 {
146 	return (gpu->revn < 300);
147 }
148 
149 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
150 {
151 	return (gpu->revn < 210);
152 }
153 
154 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
155 {
156 	return gpu->revn == 225;
157 }
158 
159 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
160 {
161 	return gpu->revn == 305;
162 }
163 
164 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
165 {
166 	/* yes, 307, because a305c is 306 */
167 	return gpu->revn == 307;
168 }
169 
170 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
171 {
172 	return gpu->revn == 320;
173 }
174 
175 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
176 {
177 	return gpu->revn == 330;
178 }
179 
180 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
181 {
182 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
183 }
184 
185 static inline int adreno_is_a405(struct adreno_gpu *gpu)
186 {
187 	return gpu->revn == 405;
188 }
189 
190 static inline int adreno_is_a420(struct adreno_gpu *gpu)
191 {
192 	return gpu->revn == 420;
193 }
194 
195 static inline int adreno_is_a430(struct adreno_gpu *gpu)
196 {
197        return gpu->revn == 430;
198 }
199 
200 static inline int adreno_is_a508(struct adreno_gpu *gpu)
201 {
202 	return gpu->revn == 508;
203 }
204 
205 static inline int adreno_is_a509(struct adreno_gpu *gpu)
206 {
207 	return gpu->revn == 509;
208 }
209 
210 static inline int adreno_is_a510(struct adreno_gpu *gpu)
211 {
212 	return gpu->revn == 510;
213 }
214 
215 static inline int adreno_is_a512(struct adreno_gpu *gpu)
216 {
217 	return gpu->revn == 512;
218 }
219 
220 static inline int adreno_is_a530(struct adreno_gpu *gpu)
221 {
222 	return gpu->revn == 530;
223 }
224 
225 static inline int adreno_is_a540(struct adreno_gpu *gpu)
226 {
227 	return gpu->revn == 540;
228 }
229 
230 static inline int adreno_is_a618(struct adreno_gpu *gpu)
231 {
232        return gpu->revn == 618;
233 }
234 
235 static inline int adreno_is_a630(struct adreno_gpu *gpu)
236 {
237        return gpu->revn == 630;
238 }
239 
240 static inline int adreno_is_a640(struct adreno_gpu *gpu)
241 {
242        return gpu->revn == 640;
243 }
244 
245 static inline int adreno_is_a650(struct adreno_gpu *gpu)
246 {
247        return gpu->revn == 650;
248 }
249 
250 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
251 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
252 		const char *fwname);
253 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
254 		const struct firmware *fw, u64 *iova);
255 int adreno_hw_init(struct msm_gpu *gpu);
256 void adreno_recover(struct msm_gpu *gpu);
257 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
258 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
259 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
260 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
261 		struct drm_printer *p);
262 #endif
263 void adreno_dump_info(struct msm_gpu *gpu);
264 void adreno_dump(struct msm_gpu *gpu);
265 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
266 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
267 
268 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
269 			  struct adreno_ocmem *ocmem);
270 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
271 
272 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
273 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
274 		int nr_rings);
275 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
276 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
277 
278 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
279 
280 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
281 int adreno_gpu_state_put(struct msm_gpu_state *state);
282 
283 /*
284  * Common helper function to initialize the default address space for arm-smmu
285  * attached targets
286  */
287 struct msm_gem_address_space *
288 adreno_iommu_create_address_space(struct msm_gpu *gpu,
289 		struct platform_device *pdev);
290 
291 void adreno_set_llc_attributes(struct iommu_domain *iommu);
292 
293 /*
294  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
295  * out of secure mode
296  */
297 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
298 
299 /* ringbuffer helpers (the parts that are adreno specific) */
300 
301 static inline void
302 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
303 {
304 	adreno_wait_ring(ring, cnt+1);
305 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
306 }
307 
308 /* no-op packet: */
309 static inline void
310 OUT_PKT2(struct msm_ringbuffer *ring)
311 {
312 	adreno_wait_ring(ring, 1);
313 	OUT_RING(ring, CP_TYPE2_PKT);
314 }
315 
316 static inline void
317 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
318 {
319 	adreno_wait_ring(ring, cnt+1);
320 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
321 }
322 
323 static inline u32 PM4_PARITY(u32 val)
324 {
325 	return (0x9669 >> (0xF & (val ^
326 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
327 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
328 		(val >> 28)))) & 1;
329 }
330 
331 /* Maximum number of values that can be executed for one opcode */
332 #define TYPE4_MAX_PAYLOAD 127
333 
334 #define PKT4(_reg, _cnt) \
335 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
336 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
337 
338 static inline void
339 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
340 {
341 	adreno_wait_ring(ring, cnt + 1);
342 	OUT_RING(ring, PKT4(regindx, cnt));
343 }
344 
345 static inline void
346 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
347 {
348 	adreno_wait_ring(ring, cnt + 1);
349 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
350 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
351 }
352 
353 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
354 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
355 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
356 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
357 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
358 
359 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
360 {
361 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
362 }
363 
364 /*
365  * Given a register and a count, return a value to program into
366  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
367  * registers starting at _reg.
368  *
369  * The register base needs to be a multiple of the length. If it is not, the
370  * hardware will quietly mask off the bits for you and shift the size. For
371  * example, if you intend the protection to start at 0x07 for a length of 4
372  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
373  * expose registers you intended to protect!
374  */
375 #define ADRENO_PROTECT_RW(_reg, _len) \
376 	((1 << 30) | (1 << 29) | \
377 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
378 
379 /*
380  * Same as above, but allow reads over the range. For areas of mixed use (such
381  * as performance counters) this allows us to protect a much larger range with a
382  * single register
383  */
384 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
385 	((1 << 29) \
386 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
387 
388 
389 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
390 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
391 		interval, timeout)
392 
393 #endif /* __ADRENO_GPU_H__ */
394