1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_opp.h> 7 #include <soc/qcom/cmd-db.h> 8 9 #include "a6xx_gpu.h" 10 #include "a6xx_gmu.xml.h" 11 12 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 13 { 14 struct a6xx_gmu *gmu = data; 15 u32 status; 16 17 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 18 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 19 20 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 21 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 22 23 /* Temporary until we can recover safely */ 24 BUG(); 25 } 26 27 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 28 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 29 30 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 31 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 32 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 33 34 return IRQ_HANDLED; 35 } 36 37 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 38 { 39 struct a6xx_gmu *gmu = data; 40 u32 status; 41 42 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 43 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 44 45 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 46 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 47 48 /* Temporary until we can recover safely */ 49 BUG(); 50 } 51 52 return IRQ_HANDLED; 53 } 54 55 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 56 { 57 u32 val; 58 59 /* This can be called from gpu state code so make sure GMU is valid */ 60 if (IS_ERR_OR_NULL(gmu->mmio)) 61 return false; 62 63 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 64 65 return !(val & 66 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 67 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 68 } 69 70 /* Check to see if the GX rail is still powered */ 71 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 72 { 73 u32 val; 74 75 /* This can be called from gpu state code so make sure GMU is valid */ 76 if (IS_ERR_OR_NULL(gmu->mmio)) 77 return false; 78 79 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 80 81 return !(val & 82 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 83 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 84 } 85 86 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 87 { 88 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 89 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 90 struct msm_gpu *gpu = &adreno_gpu->base; 91 int ret; 92 93 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 94 95 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 96 ((3 & 0xf) << 28) | index); 97 98 /* 99 * Send an invalid index as a vote for the bus bandwidth and let the 100 * firmware decide on the right vote 101 */ 102 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 103 104 /* Set and clear the OOB for DCVS to trigger the GMU */ 105 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 106 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 107 108 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 109 if (ret) 110 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 111 112 gmu->freq = gmu->gpu_freqs[index]; 113 114 /* 115 * Eventually we will want to scale the path vote with the frequency but 116 * for now leave it at max so that the performance is nominal. 117 */ 118 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 119 } 120 121 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 122 { 123 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 124 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 125 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 126 u32 perf_index = 0; 127 128 if (freq == gmu->freq) 129 return; 130 131 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 132 if (freq == gmu->gpu_freqs[perf_index]) 133 break; 134 135 __a6xx_gmu_set_freq(gmu, perf_index); 136 } 137 138 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 139 { 140 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 141 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 142 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 143 144 return gmu->freq; 145 } 146 147 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 148 { 149 u32 val; 150 int local = gmu->idle_level; 151 152 /* SPTP and IFPC both report as IFPC */ 153 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 154 local = GMU_IDLE_STATE_IFPC; 155 156 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 157 158 if (val == local) { 159 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 160 !a6xx_gmu_gx_is_on(gmu)) 161 return true; 162 } 163 164 return false; 165 } 166 167 /* Wait for the GMU to get to its most idle state */ 168 int a6xx_gmu_wait_for_idle(struct a6xx_gpu *a6xx_gpu) 169 { 170 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 171 172 return spin_until(a6xx_gmu_check_idle_level(gmu)); 173 } 174 175 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 176 { 177 int ret; 178 u32 val; 179 180 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 181 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 182 183 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 184 val == 0xbabeface, 100, 10000); 185 186 if (ret) 187 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 188 189 return ret; 190 } 191 192 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 193 { 194 u32 val; 195 int ret; 196 197 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 198 199 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 200 val & 1, 100, 10000); 201 if (ret) 202 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 203 204 return ret; 205 } 206 207 /* Trigger a OOB (out of band) request to the GMU */ 208 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 209 { 210 int ret; 211 u32 val; 212 int request, ack; 213 const char *name; 214 215 switch (state) { 216 case GMU_OOB_GPU_SET: 217 request = GMU_OOB_GPU_SET_REQUEST; 218 ack = GMU_OOB_GPU_SET_ACK; 219 name = "GPU_SET"; 220 break; 221 case GMU_OOB_BOOT_SLUMBER: 222 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 223 ack = GMU_OOB_BOOT_SLUMBER_ACK; 224 name = "BOOT_SLUMBER"; 225 break; 226 case GMU_OOB_DCVS_SET: 227 request = GMU_OOB_DCVS_REQUEST; 228 ack = GMU_OOB_DCVS_ACK; 229 name = "GPU_DCVS"; 230 break; 231 default: 232 return -EINVAL; 233 } 234 235 /* Trigger the equested OOB operation */ 236 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 237 238 /* Wait for the acknowledge interrupt */ 239 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 240 val & (1 << ack), 100, 10000); 241 242 if (ret) 243 DRM_DEV_ERROR(gmu->dev, 244 "Timeout waiting for GMU OOB set %s: 0x%x\n", 245 name, 246 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 247 248 /* Clear the acknowledge interrupt */ 249 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 250 251 return ret; 252 } 253 254 /* Clear a pending OOB state in the GMU */ 255 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 256 { 257 switch (state) { 258 case GMU_OOB_GPU_SET: 259 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 260 1 << GMU_OOB_GPU_SET_CLEAR); 261 break; 262 case GMU_OOB_BOOT_SLUMBER: 263 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 264 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 265 break; 266 case GMU_OOB_DCVS_SET: 267 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 268 1 << GMU_OOB_DCVS_CLEAR); 269 break; 270 } 271 } 272 273 /* Enable CPU control of SPTP power power collapse */ 274 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 275 { 276 int ret; 277 u32 val; 278 279 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 280 281 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 282 (val & 0x38) == 0x28, 1, 100); 283 284 if (ret) { 285 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 286 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 287 } 288 289 return 0; 290 } 291 292 /* Disable CPU control of SPTP power power collapse */ 293 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 294 { 295 u32 val; 296 int ret; 297 298 /* Make sure retention is on */ 299 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 300 301 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 302 303 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 304 (val & 0x04), 100, 10000); 305 306 if (ret) 307 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 308 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 309 } 310 311 /* Let the GMU know we are starting a boot sequence */ 312 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 313 { 314 u32 vote; 315 316 /* Let the GMU know we are getting ready for boot */ 317 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 318 319 /* Choose the "default" power level as the highest available */ 320 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 321 322 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 323 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 324 325 /* Let the GMU know the boot sequence has started */ 326 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 327 } 328 329 /* Let the GMU know that we are about to go into slumber */ 330 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 331 { 332 int ret; 333 334 /* Disable the power counter so the GMU isn't busy */ 335 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 336 337 /* Disable SPTP_PC if the CPU is responsible for it */ 338 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 339 a6xx_sptprac_disable(gmu); 340 341 /* Tell the GMU to get ready to slumber */ 342 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 343 344 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 345 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 346 347 if (!ret) { 348 /* Check to see if the GMU really did slumber */ 349 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 350 != 0x0f) { 351 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 352 ret = -ETIMEDOUT; 353 } 354 } 355 356 /* Put fence into allow mode */ 357 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 358 return ret; 359 } 360 361 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 362 { 363 int ret; 364 u32 val; 365 366 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 367 /* Wait for the register to finish posting */ 368 wmb(); 369 370 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 371 val & (1 << 1), 100, 10000); 372 if (ret) { 373 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 374 return ret; 375 } 376 377 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 378 !val, 100, 10000); 379 380 if (ret) { 381 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 382 return ret; 383 } 384 385 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 386 387 /* Set up CX GMU counter 0 to count busy ticks */ 388 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 389 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 390 391 /* Enable the power counter */ 392 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 393 return 0; 394 } 395 396 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 397 { 398 int ret; 399 u32 val; 400 401 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 402 403 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 404 val, val & (1 << 16), 100, 10000); 405 if (ret) 406 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 407 408 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 409 } 410 411 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 412 { 413 return msm_writel(value, ptr + (offset << 2)); 414 } 415 416 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 417 const char *name); 418 419 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 420 { 421 struct platform_device *pdev = to_platform_device(gmu->dev); 422 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 423 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 424 425 if (!pdcptr || !seqptr) 426 goto err; 427 428 /* Disable SDE clock gating */ 429 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 430 431 /* Setup RSC PDC handshake for sleep and wakeup */ 432 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 433 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 434 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 435 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 436 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 437 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 438 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 439 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 440 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 441 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 442 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 443 444 /* Load RSC sequencer uCode for sleep and wakeup */ 445 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 446 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 447 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 448 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 449 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 450 451 /* Load PDC sequencer uCode for power up and power down sequence */ 452 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 453 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 454 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 455 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 456 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 457 458 /* Set TCS commands used by PDC sequence for low power modes */ 459 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 460 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 461 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 462 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 463 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 464 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 465 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 466 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 467 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 468 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 469 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 470 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 471 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 472 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 473 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 474 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 475 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 476 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 477 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 478 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 479 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 480 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 481 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 482 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 483 484 /* Setup GPU PDC */ 485 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 486 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 487 488 /* ensure no writes happen before the uCode is fully written */ 489 wmb(); 490 491 err: 492 devm_iounmap(gmu->dev, pdcptr); 493 devm_iounmap(gmu->dev, seqptr); 494 } 495 496 /* 497 * The lowest 16 bits of this value are the number of XO clock cycles for main 498 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 499 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 500 */ 501 502 #define GMU_PWR_COL_HYST 0x000a1680 503 504 /* Set up the idle state for the GMU */ 505 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 506 { 507 /* Disable GMU WB/RB buffer */ 508 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 509 510 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 511 512 switch (gmu->idle_level) { 513 case GMU_IDLE_STATE_IFPC: 514 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 515 GMU_PWR_COL_HYST); 516 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 517 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 518 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 519 /* Fall through */ 520 case GMU_IDLE_STATE_SPTP: 521 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 522 GMU_PWR_COL_HYST); 523 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 524 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 525 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 526 } 527 528 /* Enable RPMh GPU client */ 529 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 530 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 531 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 532 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 533 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 534 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 535 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 536 } 537 538 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 539 { 540 static bool rpmh_init; 541 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 542 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 543 int i, ret; 544 u32 chipid; 545 u32 *image; 546 547 if (state == GMU_WARM_BOOT) { 548 ret = a6xx_rpmh_start(gmu); 549 if (ret) 550 return ret; 551 } else { 552 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 553 "GMU firmware is not loaded\n")) 554 return -ENOENT; 555 556 /* Sanity check the size of the firmware that was loaded */ 557 if (adreno_gpu->fw[ADRENO_FW_GMU]->size > 0x8000) { 558 DRM_DEV_ERROR(gmu->dev, 559 "GMU firmware is bigger than the available region\n"); 560 return -EINVAL; 561 } 562 563 /* Turn on register retention */ 564 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 565 566 /* We only need to load the RPMh microcode once */ 567 if (!rpmh_init) { 568 a6xx_gmu_rpmh_init(gmu); 569 rpmh_init = true; 570 } else if (state != GMU_RESET) { 571 ret = a6xx_rpmh_start(gmu); 572 if (ret) 573 return ret; 574 } 575 576 image = (u32 *) adreno_gpu->fw[ADRENO_FW_GMU]->data; 577 578 for (i = 0; i < adreno_gpu->fw[ADRENO_FW_GMU]->size >> 2; i++) 579 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, 580 image[i]); 581 } 582 583 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 584 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 585 586 /* Write the iova of the HFI table */ 587 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova); 588 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 589 590 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 591 (1 << 31) | (0xa << 18) | (0xa0)); 592 593 chipid = adreno_gpu->rev.core << 24; 594 chipid |= adreno_gpu->rev.major << 16; 595 chipid |= adreno_gpu->rev.minor << 12; 596 chipid |= adreno_gpu->rev.patchid << 8; 597 598 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 599 600 /* Set up the lowest idle level on the GMU */ 601 a6xx_gmu_power_config(gmu); 602 603 ret = a6xx_gmu_start(gmu); 604 if (ret) 605 return ret; 606 607 ret = a6xx_gmu_gfx_rail_on(gmu); 608 if (ret) 609 return ret; 610 611 /* Enable SPTP_PC if the CPU is responsible for it */ 612 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 613 ret = a6xx_sptprac_enable(gmu); 614 if (ret) 615 return ret; 616 } 617 618 ret = a6xx_gmu_hfi_start(gmu); 619 if (ret) 620 return ret; 621 622 /* FIXME: Do we need this wmb() here? */ 623 wmb(); 624 625 return 0; 626 } 627 628 #define A6XX_HFI_IRQ_MASK \ 629 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 630 631 #define A6XX_GMU_IRQ_MASK \ 632 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 633 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 634 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 635 636 static void a6xx_gmu_irq_enable(struct a6xx_gmu *gmu) 637 { 638 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 639 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 640 641 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, 642 ~A6XX_GMU_IRQ_MASK); 643 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, 644 ~A6XX_HFI_IRQ_MASK); 645 646 enable_irq(gmu->gmu_irq); 647 enable_irq(gmu->hfi_irq); 648 } 649 650 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 651 { 652 disable_irq(gmu->gmu_irq); 653 disable_irq(gmu->hfi_irq); 654 655 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 656 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 657 } 658 659 int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) 660 { 661 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 662 int ret; 663 u32 val; 664 665 /* Flush all the queues */ 666 a6xx_hfi_stop(gmu); 667 668 /* Stop the interrupts */ 669 a6xx_gmu_irq_disable(gmu); 670 671 /* Force off SPTP in case the GMU is managing it */ 672 a6xx_sptprac_disable(gmu); 673 674 /* Make sure there are no outstanding RPMh votes */ 675 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 676 (val & 1), 100, 10000); 677 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 678 (val & 1), 100, 10000); 679 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 680 (val & 1), 100, 10000); 681 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 682 (val & 1), 100, 1000); 683 684 /* Force off the GX GSDC */ 685 regulator_force_disable(gmu->gx); 686 687 /* Disable the resources */ 688 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 689 pm_runtime_put_sync(gmu->dev); 690 691 /* Re-enable the resources */ 692 pm_runtime_get_sync(gmu->dev); 693 694 /* Use a known rate to bring up the GMU */ 695 clk_set_rate(gmu->core_clk, 200000000); 696 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 697 if (ret) 698 goto out; 699 700 a6xx_gmu_irq_enable(gmu); 701 702 ret = a6xx_gmu_fw_start(gmu, GMU_RESET); 703 if (!ret) 704 ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT); 705 706 /* Set the GPU back to the highest power frequency */ 707 __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); 708 709 out: 710 if (ret) 711 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 712 713 return ret; 714 } 715 716 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 717 { 718 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 719 struct msm_gpu *gpu = &adreno_gpu->base; 720 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 721 int status, ret; 722 723 if (WARN(!gmu->mmio, "The GMU is not set up yet\n")) 724 return 0; 725 726 /* Turn on the resources */ 727 pm_runtime_get_sync(gmu->dev); 728 729 /* Use a known rate to bring up the GMU */ 730 clk_set_rate(gmu->core_clk, 200000000); 731 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 732 if (ret) 733 goto out; 734 735 /* Set the bus quota to a reasonable value for boot */ 736 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 737 738 a6xx_gmu_irq_enable(gmu); 739 740 /* Check to see if we are doing a cold or warm boot */ 741 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 742 GMU_WARM_BOOT : GMU_COLD_BOOT; 743 744 ret = a6xx_gmu_fw_start(gmu, status); 745 if (ret) 746 goto out; 747 748 ret = a6xx_hfi_start(gmu, status); 749 750 /* Set the GPU to the highest power frequency */ 751 __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); 752 753 out: 754 /* Make sure to turn off the boot OOB request on error */ 755 if (ret) 756 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 757 758 return ret; 759 } 760 761 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 762 { 763 u32 reg; 764 765 if (!gmu->mmio) 766 return true; 767 768 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 769 770 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 771 return false; 772 773 return true; 774 } 775 776 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 777 { 778 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 779 struct msm_gpu *gpu = &adreno_gpu->base; 780 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 781 u32 val; 782 783 /* 784 * The GMU may still be in slumber unless the GPU started so check and 785 * skip putting it back into slumber if so 786 */ 787 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 788 789 if (val != 0xf) { 790 int ret = a6xx_gmu_wait_for_idle(a6xx_gpu); 791 792 /* Temporary until we can recover safely */ 793 BUG_ON(ret); 794 795 /* tell the GMU we want to slumber */ 796 a6xx_gmu_notify_slumber(gmu); 797 798 ret = gmu_poll_timeout(gmu, 799 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 800 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 801 100, 10000); 802 803 /* 804 * Let the user know we failed to slumber but don't worry too 805 * much because we are powering down anyway 806 */ 807 808 if (ret) 809 DRM_DEV_ERROR(gmu->dev, 810 "Unable to slumber GMU: status = 0%x/0%x\n", 811 gmu_read(gmu, 812 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 813 gmu_read(gmu, 814 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 815 } 816 817 /* Turn off HFI */ 818 a6xx_hfi_stop(gmu); 819 820 /* Stop the interrupts and mask the hardware */ 821 a6xx_gmu_irq_disable(gmu); 822 823 /* Tell RPMh to power off the GPU */ 824 a6xx_rpmh_stop(gmu); 825 826 /* Remove the bus vote */ 827 icc_set_bw(gpu->icc_path, 0, 0); 828 829 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 830 831 pm_runtime_put_sync(gmu->dev); 832 833 return 0; 834 } 835 836 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo) 837 { 838 int count, i; 839 u64 iova; 840 841 if (IS_ERR_OR_NULL(bo)) 842 return; 843 844 count = bo->size >> PAGE_SHIFT; 845 iova = bo->iova; 846 847 for (i = 0; i < count; i++, iova += PAGE_SIZE) { 848 iommu_unmap(gmu->domain, iova, PAGE_SIZE); 849 __free_pages(bo->pages[i], 0); 850 } 851 852 kfree(bo->pages); 853 kfree(bo); 854 } 855 856 static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, 857 size_t size) 858 { 859 struct a6xx_gmu_bo *bo; 860 int ret, count, i; 861 862 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 863 if (!bo) 864 return ERR_PTR(-ENOMEM); 865 866 bo->size = PAGE_ALIGN(size); 867 868 count = bo->size >> PAGE_SHIFT; 869 870 bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL); 871 if (!bo->pages) { 872 kfree(bo); 873 return ERR_PTR(-ENOMEM); 874 } 875 876 for (i = 0; i < count; i++) { 877 bo->pages[i] = alloc_page(GFP_KERNEL); 878 if (!bo->pages[i]) 879 goto err; 880 } 881 882 bo->iova = gmu->uncached_iova_base; 883 884 for (i = 0; i < count; i++) { 885 ret = iommu_map(gmu->domain, 886 bo->iova + (PAGE_SIZE * i), 887 page_to_phys(bo->pages[i]), PAGE_SIZE, 888 IOMMU_READ | IOMMU_WRITE); 889 890 if (ret) { 891 DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer object\n"); 892 893 for (i = i - 1 ; i >= 0; i--) 894 iommu_unmap(gmu->domain, 895 bo->iova + (PAGE_SIZE * i), 896 PAGE_SIZE); 897 898 goto err; 899 } 900 } 901 902 bo->virt = vmap(bo->pages, count, VM_IOREMAP, 903 pgprot_writecombine(PAGE_KERNEL)); 904 if (!bo->virt) 905 goto err; 906 907 /* Align future IOVA addresses on 1MB boundaries */ 908 gmu->uncached_iova_base += ALIGN(size, SZ_1M); 909 910 return bo; 911 912 err: 913 for (i = 0; i < count; i++) { 914 if (bo->pages[i]) 915 __free_pages(bo->pages[i], 0); 916 } 917 918 kfree(bo->pages); 919 kfree(bo); 920 921 return ERR_PTR(-ENOMEM); 922 } 923 924 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 925 { 926 int ret; 927 928 /* 929 * The GMU address space is hardcoded to treat the range 930 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared 931 * between the GMU and the CPU will live in this space 932 */ 933 gmu->uncached_iova_base = 0x60000000; 934 935 936 gmu->domain = iommu_domain_alloc(&platform_bus_type); 937 if (!gmu->domain) 938 return -ENODEV; 939 940 ret = iommu_attach_device(gmu->domain, gmu->dev); 941 942 if (ret) { 943 iommu_domain_free(gmu->domain); 944 gmu->domain = NULL; 945 } 946 947 return ret; 948 } 949 950 /* Return the 'arc-level' for the given frequency */ 951 static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) 952 { 953 struct dev_pm_opp *opp; 954 struct device_node *np; 955 u32 val = 0; 956 957 if (!freq) 958 return 0; 959 960 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 961 if (IS_ERR(opp)) 962 return 0; 963 964 np = dev_pm_opp_get_of_node(opp); 965 966 if (np) { 967 of_property_read_u32(np, "opp-level", &val); 968 of_node_put(np); 969 } 970 971 dev_pm_opp_put(opp); 972 973 return val; 974 } 975 976 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 977 unsigned long *freqs, int freqs_count, const char *id) 978 { 979 int i, j; 980 const u16 *pri, *sec; 981 size_t pri_count, sec_count; 982 983 pri = cmd_db_read_aux_data(id, &pri_count); 984 if (IS_ERR(pri)) 985 return PTR_ERR(pri); 986 /* 987 * The data comes back as an array of unsigned shorts so adjust the 988 * count accordingly 989 */ 990 pri_count >>= 1; 991 if (!pri_count) 992 return -EINVAL; 993 994 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 995 if (IS_ERR(sec)) 996 return PTR_ERR(sec); 997 998 sec_count >>= 1; 999 if (!sec_count) 1000 return -EINVAL; 1001 1002 /* Construct a vote for each frequency */ 1003 for (i = 0; i < freqs_count; i++) { 1004 u8 pindex = 0, sindex = 0; 1005 u32 level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1006 1007 /* Get the primary index that matches the arc level */ 1008 for (j = 0; j < pri_count; j++) { 1009 if (pri[j] >= level) { 1010 pindex = j; 1011 break; 1012 } 1013 } 1014 1015 if (j == pri_count) { 1016 DRM_DEV_ERROR(dev, 1017 "Level %u not found in in the RPMh list\n", 1018 level); 1019 DRM_DEV_ERROR(dev, "Available levels:\n"); 1020 for (j = 0; j < pri_count; j++) 1021 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1022 1023 return -EINVAL; 1024 } 1025 1026 /* 1027 * Look for a level in in the secondary list that matches. If 1028 * nothing fits, use the maximum non zero vote 1029 */ 1030 1031 for (j = 0; j < sec_count; j++) { 1032 if (sec[j] >= level) { 1033 sindex = j; 1034 break; 1035 } else if (sec[j]) { 1036 sindex = j; 1037 } 1038 } 1039 1040 /* Construct the vote */ 1041 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1042 (sindex << 8) | pindex; 1043 } 1044 1045 return 0; 1046 } 1047 1048 /* 1049 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1050 * to construct the list of votes on the CPU and send it over. Query the RPMh 1051 * voltage levels and build the votes 1052 */ 1053 1054 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1055 { 1056 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1057 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1058 struct msm_gpu *gpu = &adreno_gpu->base; 1059 int ret; 1060 1061 /* Build the GX votes */ 1062 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1063 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1064 1065 /* Build the CX votes */ 1066 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1067 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1068 1069 return ret; 1070 } 1071 1072 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1073 u32 size) 1074 { 1075 int count = dev_pm_opp_get_opp_count(dev); 1076 struct dev_pm_opp *opp; 1077 int i, index = 0; 1078 unsigned long freq = 1; 1079 1080 /* 1081 * The OPP table doesn't contain the "off" frequency level so we need to 1082 * add 1 to the table size to account for it 1083 */ 1084 1085 if (WARN(count + 1 > size, 1086 "The GMU frequency table is being truncated\n")) 1087 count = size - 1; 1088 1089 /* Set the "off" frequency */ 1090 freqs[index++] = 0; 1091 1092 for (i = 0; i < count; i++) { 1093 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1094 if (IS_ERR(opp)) 1095 break; 1096 1097 dev_pm_opp_put(opp); 1098 freqs[index++] = freq++; 1099 } 1100 1101 return index; 1102 } 1103 1104 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1105 { 1106 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1107 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1108 struct msm_gpu *gpu = &adreno_gpu->base; 1109 1110 int ret = 0; 1111 1112 /* 1113 * The GMU handles its own frequency switching so build a list of 1114 * available frequencies to send during initialization 1115 */ 1116 ret = dev_pm_opp_of_add_table(gmu->dev); 1117 if (ret) { 1118 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1119 return ret; 1120 } 1121 1122 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1123 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1124 1125 /* 1126 * The GMU also handles GPU frequency switching so build a list 1127 * from the GPU OPP table 1128 */ 1129 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1130 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1131 1132 /* Build the list of RPMh votes that we'll send to the GMU */ 1133 return a6xx_gmu_rpmh_votes_init(gmu); 1134 } 1135 1136 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1137 { 1138 int ret = msm_clk_bulk_get(gmu->dev, &gmu->clocks); 1139 1140 if (ret < 1) 1141 return ret; 1142 1143 gmu->nr_clocks = ret; 1144 1145 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1146 gmu->nr_clocks, "gmu"); 1147 1148 return 0; 1149 } 1150 1151 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1152 const char *name) 1153 { 1154 void __iomem *ret; 1155 struct resource *res = platform_get_resource_byname(pdev, 1156 IORESOURCE_MEM, name); 1157 1158 if (!res) { 1159 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1160 return ERR_PTR(-EINVAL); 1161 } 1162 1163 ret = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1164 if (!ret) { 1165 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1166 return ERR_PTR(-EINVAL); 1167 } 1168 1169 return ret; 1170 } 1171 1172 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1173 const char *name, irq_handler_t handler) 1174 { 1175 int irq, ret; 1176 1177 irq = platform_get_irq_byname(pdev, name); 1178 1179 ret = devm_request_irq(&pdev->dev, irq, handler, IRQF_TRIGGER_HIGH, 1180 name, gmu); 1181 if (ret) { 1182 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s\n", name); 1183 return ret; 1184 } 1185 1186 disable_irq(irq); 1187 1188 return irq; 1189 } 1190 1191 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1192 { 1193 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1194 1195 if (IS_ERR_OR_NULL(gmu->mmio)) 1196 return; 1197 1198 pm_runtime_disable(gmu->dev); 1199 a6xx_gmu_stop(a6xx_gpu); 1200 1201 a6xx_gmu_irq_disable(gmu); 1202 a6xx_gmu_memory_free(gmu, gmu->hfi); 1203 1204 iommu_detach_device(gmu->domain, gmu->dev); 1205 1206 iommu_domain_free(gmu->domain); 1207 } 1208 1209 int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1210 { 1211 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1212 struct platform_device *pdev = of_find_device_by_node(node); 1213 int ret; 1214 1215 if (!pdev) 1216 return -ENODEV; 1217 1218 gmu->dev = &pdev->dev; 1219 1220 of_dma_configure(gmu->dev, node, true); 1221 1222 /* Fow now, don't do anything fancy until we get our feet under us */ 1223 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1224 1225 pm_runtime_enable(gmu->dev); 1226 gmu->gx = devm_regulator_get(gmu->dev, "vdd"); 1227 1228 /* Get the list of clocks */ 1229 ret = a6xx_gmu_clocks_probe(gmu); 1230 if (ret) 1231 return ret; 1232 1233 /* Set up the IOMMU context bank */ 1234 ret = a6xx_gmu_memory_probe(gmu); 1235 if (ret) 1236 return ret; 1237 1238 /* Allocate memory for for the HFI queues */ 1239 gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1240 if (IS_ERR(gmu->hfi)) 1241 goto err; 1242 1243 /* Allocate memory for the GMU debug region */ 1244 gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1245 if (IS_ERR(gmu->debug)) 1246 goto err; 1247 1248 /* Map the GMU registers */ 1249 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1250 if (IS_ERR(gmu->mmio)) 1251 goto err; 1252 1253 /* Get the HFI and GMU interrupts */ 1254 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1255 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1256 1257 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1258 goto err; 1259 1260 /* Get the power levels for the GMU and GPU */ 1261 a6xx_gmu_pwrlevels_probe(gmu); 1262 1263 /* Set up the HFI queues */ 1264 a6xx_hfi_init(gmu); 1265 1266 return 0; 1267 err: 1268 a6xx_gmu_memory_free(gmu, gmu->hfi); 1269 1270 if (gmu->domain) { 1271 iommu_detach_device(gmu->domain, gmu->dev); 1272 1273 iommu_domain_free(gmu->domain); 1274 } 1275 1276 return -ENODEV; 1277 } 1278