1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 10 #include "a6xx_gpu.h" 11 #include "a6xx_gmu.xml.h" 12 13 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 14 { 15 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 16 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 17 struct msm_gpu *gpu = &adreno_gpu->base; 18 struct drm_device *dev = gpu->dev; 19 struct msm_drm_private *priv = dev->dev_private; 20 21 /* FIXME: add a banner here */ 22 gmu->hung = true; 23 24 /* Turn off the hangcheck timer while we are resetting */ 25 del_timer(&gpu->hangcheck_timer); 26 27 /* Queue the GPU handler because we need to treat this as a recovery */ 28 queue_work(priv->wq, &gpu->recover_work); 29 } 30 31 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 32 { 33 struct a6xx_gmu *gmu = data; 34 u32 status; 35 36 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 37 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 38 39 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 40 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 41 42 a6xx_gmu_fault(gmu); 43 } 44 45 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 46 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 49 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 50 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 51 52 return IRQ_HANDLED; 53 } 54 55 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 56 { 57 struct a6xx_gmu *gmu = data; 58 u32 status; 59 60 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 61 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 62 63 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 64 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 65 66 a6xx_gmu_fault(gmu); 67 } 68 69 return IRQ_HANDLED; 70 } 71 72 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 73 { 74 u32 val; 75 76 /* This can be called from gpu state code so make sure GMU is valid */ 77 if (IS_ERR_OR_NULL(gmu->mmio)) 78 return false; 79 80 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 81 82 return !(val & 83 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 84 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 85 } 86 87 /* Check to see if the GX rail is still powered */ 88 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 89 { 90 u32 val; 91 92 /* This can be called from gpu state code so make sure GMU is valid */ 93 if (IS_ERR_OR_NULL(gmu->mmio)) 94 return false; 95 96 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 97 98 return !(val & 99 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 100 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 101 } 102 103 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 104 { 105 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 106 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 107 struct msm_gpu *gpu = &adreno_gpu->base; 108 int ret; 109 110 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 111 112 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 113 ((3 & 0xf) << 28) | index); 114 115 /* 116 * Send an invalid index as a vote for the bus bandwidth and let the 117 * firmware decide on the right vote 118 */ 119 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 120 121 /* Set and clear the OOB for DCVS to trigger the GMU */ 122 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 123 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 124 125 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 126 if (ret) 127 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 128 129 gmu->freq = gmu->gpu_freqs[index]; 130 131 /* 132 * Eventually we will want to scale the path vote with the frequency but 133 * for now leave it at max so that the performance is nominal. 134 */ 135 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 136 } 137 138 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 139 { 140 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 141 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 142 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 143 u32 perf_index = 0; 144 145 if (freq == gmu->freq) 146 return; 147 148 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 149 if (freq == gmu->gpu_freqs[perf_index]) 150 break; 151 152 __a6xx_gmu_set_freq(gmu, perf_index); 153 } 154 155 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 156 { 157 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 158 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 159 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 160 161 return gmu->freq; 162 } 163 164 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 165 { 166 u32 val; 167 int local = gmu->idle_level; 168 169 /* SPTP and IFPC both report as IFPC */ 170 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 171 local = GMU_IDLE_STATE_IFPC; 172 173 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 174 175 if (val == local) { 176 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 177 !a6xx_gmu_gx_is_on(gmu)) 178 return true; 179 } 180 181 return false; 182 } 183 184 /* Wait for the GMU to get to its most idle state */ 185 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 186 { 187 return spin_until(a6xx_gmu_check_idle_level(gmu)); 188 } 189 190 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 191 { 192 int ret; 193 u32 val; 194 195 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 196 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 197 198 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 199 val == 0xbabeface, 100, 10000); 200 201 if (ret) 202 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 203 204 return ret; 205 } 206 207 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 208 { 209 u32 val; 210 int ret; 211 212 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 213 214 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 215 val & 1, 100, 10000); 216 if (ret) 217 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 218 219 return ret; 220 } 221 222 /* Trigger a OOB (out of band) request to the GMU */ 223 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 224 { 225 int ret; 226 u32 val; 227 int request, ack; 228 const char *name; 229 230 switch (state) { 231 case GMU_OOB_GPU_SET: 232 request = GMU_OOB_GPU_SET_REQUEST; 233 ack = GMU_OOB_GPU_SET_ACK; 234 name = "GPU_SET"; 235 break; 236 case GMU_OOB_BOOT_SLUMBER: 237 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 238 ack = GMU_OOB_BOOT_SLUMBER_ACK; 239 name = "BOOT_SLUMBER"; 240 break; 241 case GMU_OOB_DCVS_SET: 242 request = GMU_OOB_DCVS_REQUEST; 243 ack = GMU_OOB_DCVS_ACK; 244 name = "GPU_DCVS"; 245 break; 246 default: 247 return -EINVAL; 248 } 249 250 /* Trigger the equested OOB operation */ 251 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 252 253 /* Wait for the acknowledge interrupt */ 254 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 255 val & (1 << ack), 100, 10000); 256 257 if (ret) 258 DRM_DEV_ERROR(gmu->dev, 259 "Timeout waiting for GMU OOB set %s: 0x%x\n", 260 name, 261 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 262 263 /* Clear the acknowledge interrupt */ 264 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 265 266 return ret; 267 } 268 269 /* Clear a pending OOB state in the GMU */ 270 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 271 { 272 switch (state) { 273 case GMU_OOB_GPU_SET: 274 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 275 1 << GMU_OOB_GPU_SET_CLEAR); 276 break; 277 case GMU_OOB_BOOT_SLUMBER: 278 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 279 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 280 break; 281 case GMU_OOB_DCVS_SET: 282 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 283 1 << GMU_OOB_DCVS_CLEAR); 284 break; 285 } 286 } 287 288 /* Enable CPU control of SPTP power power collapse */ 289 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 290 { 291 int ret; 292 u32 val; 293 294 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 295 296 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 297 (val & 0x38) == 0x28, 1, 100); 298 299 if (ret) { 300 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 301 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 302 } 303 304 return 0; 305 } 306 307 /* Disable CPU control of SPTP power power collapse */ 308 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 309 { 310 u32 val; 311 int ret; 312 313 /* Make sure retention is on */ 314 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 315 316 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 317 318 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 319 (val & 0x04), 100, 10000); 320 321 if (ret) 322 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 323 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 324 } 325 326 /* Let the GMU know we are starting a boot sequence */ 327 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 328 { 329 u32 vote; 330 331 /* Let the GMU know we are getting ready for boot */ 332 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 333 334 /* Choose the "default" power level as the highest available */ 335 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 336 337 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 338 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 339 340 /* Let the GMU know the boot sequence has started */ 341 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 342 } 343 344 /* Let the GMU know that we are about to go into slumber */ 345 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 346 { 347 int ret; 348 349 /* Disable the power counter so the GMU isn't busy */ 350 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 351 352 /* Disable SPTP_PC if the CPU is responsible for it */ 353 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 354 a6xx_sptprac_disable(gmu); 355 356 /* Tell the GMU to get ready to slumber */ 357 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 358 359 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 360 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 361 362 if (!ret) { 363 /* Check to see if the GMU really did slumber */ 364 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 365 != 0x0f) { 366 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 367 ret = -ETIMEDOUT; 368 } 369 } 370 371 /* Put fence into allow mode */ 372 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 373 return ret; 374 } 375 376 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 377 { 378 int ret; 379 u32 val; 380 381 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 382 /* Wait for the register to finish posting */ 383 wmb(); 384 385 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 386 val & (1 << 1), 100, 10000); 387 if (ret) { 388 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 389 return ret; 390 } 391 392 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 393 !val, 100, 10000); 394 395 if (ret) { 396 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 397 return ret; 398 } 399 400 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 401 402 /* Set up CX GMU counter 0 to count busy ticks */ 403 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 404 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 405 406 /* Enable the power counter */ 407 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 408 return 0; 409 } 410 411 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 412 { 413 int ret; 414 u32 val; 415 416 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 417 418 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 419 val, val & (1 << 16), 100, 10000); 420 if (ret) 421 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 422 423 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 424 } 425 426 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 427 { 428 return msm_writel(value, ptr + (offset << 2)); 429 } 430 431 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 432 const char *name); 433 434 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 435 { 436 struct platform_device *pdev = to_platform_device(gmu->dev); 437 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 438 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 439 440 if (!pdcptr || !seqptr) 441 goto err; 442 443 /* Disable SDE clock gating */ 444 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 445 446 /* Setup RSC PDC handshake for sleep and wakeup */ 447 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 448 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 449 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 450 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 451 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 452 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 453 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 454 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 455 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 456 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 457 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 458 459 /* Load RSC sequencer uCode for sleep and wakeup */ 460 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 461 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 462 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 463 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 464 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 465 466 /* Load PDC sequencer uCode for power up and power down sequence */ 467 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 468 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 469 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 470 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 471 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 472 473 /* Set TCS commands used by PDC sequence for low power modes */ 474 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 475 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 476 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 477 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 478 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 479 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 480 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 481 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 482 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 483 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 484 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 485 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 486 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 487 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 488 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 489 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 490 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 491 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 492 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 493 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 494 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 495 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 496 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 497 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 498 499 /* Setup GPU PDC */ 500 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 501 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 502 503 /* ensure no writes happen before the uCode is fully written */ 504 wmb(); 505 506 err: 507 devm_iounmap(gmu->dev, pdcptr); 508 devm_iounmap(gmu->dev, seqptr); 509 } 510 511 /* 512 * The lowest 16 bits of this value are the number of XO clock cycles for main 513 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 514 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 515 */ 516 517 #define GMU_PWR_COL_HYST 0x000a1680 518 519 /* Set up the idle state for the GMU */ 520 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 521 { 522 /* Disable GMU WB/RB buffer */ 523 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 524 525 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 526 527 switch (gmu->idle_level) { 528 case GMU_IDLE_STATE_IFPC: 529 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 530 GMU_PWR_COL_HYST); 531 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 532 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 533 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 534 /* Fall through */ 535 case GMU_IDLE_STATE_SPTP: 536 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 537 GMU_PWR_COL_HYST); 538 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 539 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 540 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 541 } 542 543 /* Enable RPMh GPU client */ 544 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 545 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 546 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 547 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 548 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 549 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 550 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 551 } 552 553 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 554 { 555 static bool rpmh_init; 556 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 557 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 558 int i, ret; 559 u32 chipid; 560 u32 *image; 561 562 if (state == GMU_WARM_BOOT) { 563 ret = a6xx_rpmh_start(gmu); 564 if (ret) 565 return ret; 566 } else { 567 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 568 "GMU firmware is not loaded\n")) 569 return -ENOENT; 570 571 /* Sanity check the size of the firmware that was loaded */ 572 if (adreno_gpu->fw[ADRENO_FW_GMU]->size > 0x8000) { 573 DRM_DEV_ERROR(gmu->dev, 574 "GMU firmware is bigger than the available region\n"); 575 return -EINVAL; 576 } 577 578 /* Turn on register retention */ 579 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 580 581 /* We only need to load the RPMh microcode once */ 582 if (!rpmh_init) { 583 a6xx_gmu_rpmh_init(gmu); 584 rpmh_init = true; 585 } else { 586 ret = a6xx_rpmh_start(gmu); 587 if (ret) 588 return ret; 589 } 590 591 image = (u32 *) adreno_gpu->fw[ADRENO_FW_GMU]->data; 592 593 for (i = 0; i < adreno_gpu->fw[ADRENO_FW_GMU]->size >> 2; i++) 594 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, 595 image[i]); 596 } 597 598 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 599 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 600 601 /* Write the iova of the HFI table */ 602 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova); 603 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 604 605 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 606 (1 << 31) | (0xa << 18) | (0xa0)); 607 608 chipid = adreno_gpu->rev.core << 24; 609 chipid |= adreno_gpu->rev.major << 16; 610 chipid |= adreno_gpu->rev.minor << 12; 611 chipid |= adreno_gpu->rev.patchid << 8; 612 613 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 614 615 /* Set up the lowest idle level on the GMU */ 616 a6xx_gmu_power_config(gmu); 617 618 ret = a6xx_gmu_start(gmu); 619 if (ret) 620 return ret; 621 622 ret = a6xx_gmu_gfx_rail_on(gmu); 623 if (ret) 624 return ret; 625 626 /* Enable SPTP_PC if the CPU is responsible for it */ 627 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 628 ret = a6xx_sptprac_enable(gmu); 629 if (ret) 630 return ret; 631 } 632 633 ret = a6xx_gmu_hfi_start(gmu); 634 if (ret) 635 return ret; 636 637 /* FIXME: Do we need this wmb() here? */ 638 wmb(); 639 640 return 0; 641 } 642 643 #define A6XX_HFI_IRQ_MASK \ 644 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 645 646 #define A6XX_GMU_IRQ_MASK \ 647 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 648 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 649 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 650 651 static void a6xx_gmu_irq_enable(struct a6xx_gmu *gmu) 652 { 653 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 654 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 655 656 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, 657 ~A6XX_GMU_IRQ_MASK); 658 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, 659 ~A6XX_HFI_IRQ_MASK); 660 661 enable_irq(gmu->gmu_irq); 662 enable_irq(gmu->hfi_irq); 663 } 664 665 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 666 { 667 disable_irq(gmu->gmu_irq); 668 disable_irq(gmu->hfi_irq); 669 670 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 671 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 672 } 673 674 /* Force the GMU off in case it isn't responsive */ 675 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 676 { 677 u32 val; 678 679 /* Flush all the queues */ 680 a6xx_hfi_stop(gmu); 681 682 /* Stop the interrupts */ 683 a6xx_gmu_irq_disable(gmu); 684 685 /* Force off SPTP in case the GMU is managing it */ 686 a6xx_sptprac_disable(gmu); 687 688 /* Make sure there are no outstanding RPMh votes */ 689 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 690 (val & 1), 100, 10000); 691 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 692 (val & 1), 100, 10000); 693 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 694 (val & 1), 100, 10000); 695 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 696 (val & 1), 100, 1000); 697 } 698 699 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 700 { 701 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 702 struct msm_gpu *gpu = &adreno_gpu->base; 703 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 704 int status, ret; 705 706 if (WARN(!gmu->mmio, "The GMU is not set up yet\n")) 707 return 0; 708 709 gmu->hung = false; 710 711 /* Turn on the resources */ 712 pm_runtime_get_sync(gmu->dev); 713 714 /* Use a known rate to bring up the GMU */ 715 clk_set_rate(gmu->core_clk, 200000000); 716 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 717 if (ret) 718 goto out; 719 720 /* Set the bus quota to a reasonable value for boot */ 721 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 722 723 a6xx_gmu_irq_enable(gmu); 724 725 /* Check to see if we are doing a cold or warm boot */ 726 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 727 GMU_WARM_BOOT : GMU_COLD_BOOT; 728 729 ret = a6xx_gmu_fw_start(gmu, status); 730 if (ret) 731 goto out; 732 733 ret = a6xx_hfi_start(gmu, status); 734 735 /* Set the GPU to the highest power frequency */ 736 __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); 737 738 /* 739 * "enable" the GX power domain which won't actually do anything but it 740 * will make sure that the refcounting is correct in case we need to 741 * bring down the GX after a GMU failure 742 */ 743 if (!IS_ERR(gmu->gxpd)) 744 pm_runtime_get(gmu->gxpd); 745 746 out: 747 /* Make sure to turn off the boot OOB request on error */ 748 if (ret) 749 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 750 751 return ret; 752 } 753 754 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 755 { 756 u32 reg; 757 758 if (!gmu->mmio) 759 return true; 760 761 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 762 763 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 764 return false; 765 766 return true; 767 } 768 769 /* Gracefully try to shut down the GMU and by extension the GPU */ 770 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 771 { 772 u32 val; 773 774 /* 775 * The GMU may still be in slumber unless the GPU started so check and 776 * skip putting it back into slumber if so 777 */ 778 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 779 780 if (val != 0xf) { 781 int ret = a6xx_gmu_wait_for_idle(gmu); 782 783 /* If the GMU isn't responding assume it is hung */ 784 if (ret) { 785 a6xx_gmu_force_off(gmu); 786 return; 787 } 788 789 /* tell the GMU we want to slumber */ 790 a6xx_gmu_notify_slumber(gmu); 791 792 ret = gmu_poll_timeout(gmu, 793 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 794 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 795 100, 10000); 796 797 /* 798 * Let the user know we failed to slumber but don't worry too 799 * much because we are powering down anyway 800 */ 801 802 if (ret) 803 DRM_DEV_ERROR(gmu->dev, 804 "Unable to slumber GMU: status = 0%x/0%x\n", 805 gmu_read(gmu, 806 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 807 gmu_read(gmu, 808 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 809 } 810 811 /* Turn off HFI */ 812 a6xx_hfi_stop(gmu); 813 814 /* Stop the interrupts and mask the hardware */ 815 a6xx_gmu_irq_disable(gmu); 816 817 /* Tell RPMh to power off the GPU */ 818 a6xx_rpmh_stop(gmu); 819 } 820 821 822 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 823 { 824 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 825 struct msm_gpu *gpu = &a6xx_gpu->base.base; 826 827 /* 828 * Force the GMU off if we detected a hang, otherwise try to shut it 829 * down gracefully 830 */ 831 if (gmu->hung) 832 a6xx_gmu_force_off(gmu); 833 else 834 a6xx_gmu_shutdown(gmu); 835 836 /* Remove the bus vote */ 837 icc_set_bw(gpu->icc_path, 0, 0); 838 839 /* 840 * Make sure the GX domain is off before turning off the GMU (CX) 841 * domain. Usually the GMU does this but only if the shutdown sequence 842 * was successful 843 */ 844 if (!IS_ERR(gmu->gxpd)) 845 pm_runtime_put_sync(gmu->gxpd); 846 847 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 848 849 pm_runtime_put_sync(gmu->dev); 850 851 return 0; 852 } 853 854 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo) 855 { 856 int count, i; 857 u64 iova; 858 859 if (IS_ERR_OR_NULL(bo)) 860 return; 861 862 count = bo->size >> PAGE_SHIFT; 863 iova = bo->iova; 864 865 for (i = 0; i < count; i++, iova += PAGE_SIZE) { 866 iommu_unmap(gmu->domain, iova, PAGE_SIZE); 867 __free_pages(bo->pages[i], 0); 868 } 869 870 kfree(bo->pages); 871 kfree(bo); 872 } 873 874 static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, 875 size_t size) 876 { 877 struct a6xx_gmu_bo *bo; 878 int ret, count, i; 879 880 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 881 if (!bo) 882 return ERR_PTR(-ENOMEM); 883 884 bo->size = PAGE_ALIGN(size); 885 886 count = bo->size >> PAGE_SHIFT; 887 888 bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL); 889 if (!bo->pages) { 890 kfree(bo); 891 return ERR_PTR(-ENOMEM); 892 } 893 894 for (i = 0; i < count; i++) { 895 bo->pages[i] = alloc_page(GFP_KERNEL); 896 if (!bo->pages[i]) 897 goto err; 898 } 899 900 bo->iova = gmu->uncached_iova_base; 901 902 for (i = 0; i < count; i++) { 903 ret = iommu_map(gmu->domain, 904 bo->iova + (PAGE_SIZE * i), 905 page_to_phys(bo->pages[i]), PAGE_SIZE, 906 IOMMU_READ | IOMMU_WRITE); 907 908 if (ret) { 909 DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer object\n"); 910 911 for (i = i - 1 ; i >= 0; i--) 912 iommu_unmap(gmu->domain, 913 bo->iova + (PAGE_SIZE * i), 914 PAGE_SIZE); 915 916 goto err; 917 } 918 } 919 920 bo->virt = vmap(bo->pages, count, VM_IOREMAP, 921 pgprot_writecombine(PAGE_KERNEL)); 922 if (!bo->virt) 923 goto err; 924 925 /* Align future IOVA addresses on 1MB boundaries */ 926 gmu->uncached_iova_base += ALIGN(size, SZ_1M); 927 928 return bo; 929 930 err: 931 for (i = 0; i < count; i++) { 932 if (bo->pages[i]) 933 __free_pages(bo->pages[i], 0); 934 } 935 936 kfree(bo->pages); 937 kfree(bo); 938 939 return ERR_PTR(-ENOMEM); 940 } 941 942 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 943 { 944 int ret; 945 946 /* 947 * The GMU address space is hardcoded to treat the range 948 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared 949 * between the GMU and the CPU will live in this space 950 */ 951 gmu->uncached_iova_base = 0x60000000; 952 953 954 gmu->domain = iommu_domain_alloc(&platform_bus_type); 955 if (!gmu->domain) 956 return -ENODEV; 957 958 ret = iommu_attach_device(gmu->domain, gmu->dev); 959 960 if (ret) { 961 iommu_domain_free(gmu->domain); 962 gmu->domain = NULL; 963 } 964 965 return ret; 966 } 967 968 /* Return the 'arc-level' for the given frequency */ 969 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 970 unsigned long freq) 971 { 972 struct dev_pm_opp *opp; 973 unsigned int val; 974 975 if (!freq) 976 return 0; 977 978 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 979 if (IS_ERR(opp)) 980 return 0; 981 982 val = dev_pm_opp_get_level(opp); 983 984 dev_pm_opp_put(opp); 985 986 return val; 987 } 988 989 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 990 unsigned long *freqs, int freqs_count, const char *id) 991 { 992 int i, j; 993 const u16 *pri, *sec; 994 size_t pri_count, sec_count; 995 996 pri = cmd_db_read_aux_data(id, &pri_count); 997 if (IS_ERR(pri)) 998 return PTR_ERR(pri); 999 /* 1000 * The data comes back as an array of unsigned shorts so adjust the 1001 * count accordingly 1002 */ 1003 pri_count >>= 1; 1004 if (!pri_count) 1005 return -EINVAL; 1006 1007 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1008 if (IS_ERR(sec)) 1009 return PTR_ERR(sec); 1010 1011 sec_count >>= 1; 1012 if (!sec_count) 1013 return -EINVAL; 1014 1015 /* Construct a vote for each frequency */ 1016 for (i = 0; i < freqs_count; i++) { 1017 u8 pindex = 0, sindex = 0; 1018 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1019 1020 /* Get the primary index that matches the arc level */ 1021 for (j = 0; j < pri_count; j++) { 1022 if (pri[j] >= level) { 1023 pindex = j; 1024 break; 1025 } 1026 } 1027 1028 if (j == pri_count) { 1029 DRM_DEV_ERROR(dev, 1030 "Level %u not found in in the RPMh list\n", 1031 level); 1032 DRM_DEV_ERROR(dev, "Available levels:\n"); 1033 for (j = 0; j < pri_count; j++) 1034 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1035 1036 return -EINVAL; 1037 } 1038 1039 /* 1040 * Look for a level in in the secondary list that matches. If 1041 * nothing fits, use the maximum non zero vote 1042 */ 1043 1044 for (j = 0; j < sec_count; j++) { 1045 if (sec[j] >= level) { 1046 sindex = j; 1047 break; 1048 } else if (sec[j]) { 1049 sindex = j; 1050 } 1051 } 1052 1053 /* Construct the vote */ 1054 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1055 (sindex << 8) | pindex; 1056 } 1057 1058 return 0; 1059 } 1060 1061 /* 1062 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1063 * to construct the list of votes on the CPU and send it over. Query the RPMh 1064 * voltage levels and build the votes 1065 */ 1066 1067 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1068 { 1069 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1070 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1071 struct msm_gpu *gpu = &adreno_gpu->base; 1072 int ret; 1073 1074 /* Build the GX votes */ 1075 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1076 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1077 1078 /* Build the CX votes */ 1079 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1080 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1081 1082 return ret; 1083 } 1084 1085 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1086 u32 size) 1087 { 1088 int count = dev_pm_opp_get_opp_count(dev); 1089 struct dev_pm_opp *opp; 1090 int i, index = 0; 1091 unsigned long freq = 1; 1092 1093 /* 1094 * The OPP table doesn't contain the "off" frequency level so we need to 1095 * add 1 to the table size to account for it 1096 */ 1097 1098 if (WARN(count + 1 > size, 1099 "The GMU frequency table is being truncated\n")) 1100 count = size - 1; 1101 1102 /* Set the "off" frequency */ 1103 freqs[index++] = 0; 1104 1105 for (i = 0; i < count; i++) { 1106 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1107 if (IS_ERR(opp)) 1108 break; 1109 1110 dev_pm_opp_put(opp); 1111 freqs[index++] = freq++; 1112 } 1113 1114 return index; 1115 } 1116 1117 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1118 { 1119 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1120 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1121 struct msm_gpu *gpu = &adreno_gpu->base; 1122 1123 int ret = 0; 1124 1125 /* 1126 * The GMU handles its own frequency switching so build a list of 1127 * available frequencies to send during initialization 1128 */ 1129 ret = dev_pm_opp_of_add_table(gmu->dev); 1130 if (ret) { 1131 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1132 return ret; 1133 } 1134 1135 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1136 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1137 1138 /* 1139 * The GMU also handles GPU frequency switching so build a list 1140 * from the GPU OPP table 1141 */ 1142 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1143 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1144 1145 /* Build the list of RPMh votes that we'll send to the GMU */ 1146 return a6xx_gmu_rpmh_votes_init(gmu); 1147 } 1148 1149 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1150 { 1151 int ret = msm_clk_bulk_get(gmu->dev, &gmu->clocks); 1152 1153 if (ret < 1) 1154 return ret; 1155 1156 gmu->nr_clocks = ret; 1157 1158 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1159 gmu->nr_clocks, "gmu"); 1160 1161 return 0; 1162 } 1163 1164 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1165 const char *name) 1166 { 1167 void __iomem *ret; 1168 struct resource *res = platform_get_resource_byname(pdev, 1169 IORESOURCE_MEM, name); 1170 1171 if (!res) { 1172 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1173 return ERR_PTR(-EINVAL); 1174 } 1175 1176 ret = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1177 if (!ret) { 1178 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1179 return ERR_PTR(-EINVAL); 1180 } 1181 1182 return ret; 1183 } 1184 1185 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1186 const char *name, irq_handler_t handler) 1187 { 1188 int irq, ret; 1189 1190 irq = platform_get_irq_byname(pdev, name); 1191 1192 ret = devm_request_irq(&pdev->dev, irq, handler, IRQF_TRIGGER_HIGH, 1193 name, gmu); 1194 if (ret) { 1195 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s\n", name); 1196 return ret; 1197 } 1198 1199 disable_irq(irq); 1200 1201 return irq; 1202 } 1203 1204 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1205 { 1206 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1207 1208 if (IS_ERR_OR_NULL(gmu->mmio)) 1209 return; 1210 1211 a6xx_gmu_stop(a6xx_gpu); 1212 1213 pm_runtime_disable(gmu->dev); 1214 1215 if (!IS_ERR(gmu->gxpd)) { 1216 pm_runtime_disable(gmu->gxpd); 1217 dev_pm_domain_detach(gmu->gxpd, false); 1218 } 1219 1220 a6xx_gmu_irq_disable(gmu); 1221 a6xx_gmu_memory_free(gmu, gmu->hfi); 1222 1223 iommu_detach_device(gmu->domain, gmu->dev); 1224 1225 iommu_domain_free(gmu->domain); 1226 } 1227 1228 int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1229 { 1230 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1231 struct platform_device *pdev = of_find_device_by_node(node); 1232 int ret; 1233 1234 if (!pdev) 1235 return -ENODEV; 1236 1237 gmu->dev = &pdev->dev; 1238 1239 of_dma_configure(gmu->dev, node, true); 1240 1241 /* Fow now, don't do anything fancy until we get our feet under us */ 1242 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1243 1244 pm_runtime_enable(gmu->dev); 1245 1246 /* Get the list of clocks */ 1247 ret = a6xx_gmu_clocks_probe(gmu); 1248 if (ret) 1249 return ret; 1250 1251 /* Set up the IOMMU context bank */ 1252 ret = a6xx_gmu_memory_probe(gmu); 1253 if (ret) 1254 return ret; 1255 1256 /* Allocate memory for for the HFI queues */ 1257 gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1258 if (IS_ERR(gmu->hfi)) 1259 goto err; 1260 1261 /* Allocate memory for the GMU debug region */ 1262 gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1263 if (IS_ERR(gmu->debug)) 1264 goto err; 1265 1266 /* Map the GMU registers */ 1267 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1268 if (IS_ERR(gmu->mmio)) 1269 goto err; 1270 1271 /* Get the HFI and GMU interrupts */ 1272 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1273 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1274 1275 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1276 goto err; 1277 1278 /* 1279 * Get a link to the GX power domain to reset the GPU in case of GMU 1280 * crash 1281 */ 1282 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1283 1284 /* Get the power levels for the GMU and GPU */ 1285 a6xx_gmu_pwrlevels_probe(gmu); 1286 1287 /* Set up the HFI queues */ 1288 a6xx_hfi_init(gmu); 1289 1290 return 0; 1291 err: 1292 a6xx_gmu_memory_free(gmu, gmu->hfi); 1293 1294 if (gmu->domain) { 1295 iommu_detach_device(gmu->domain, gmu->dev); 1296 1297 iommu_domain_free(gmu->domain); 1298 } 1299 1300 return -ENODEV; 1301 } 1302