1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_gpu_trace.h" 15 #include "msm_mmu.h" 16 17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 18 { 19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 21 struct msm_gpu *gpu = &adreno_gpu->base; 22 struct drm_device *dev = gpu->dev; 23 struct msm_drm_private *priv = dev->dev_private; 24 25 /* FIXME: add a banner here */ 26 gmu->hung = true; 27 28 /* Turn off the hangcheck timer while we are resetting */ 29 del_timer(&gpu->hangcheck_timer); 30 31 /* Queue the GPU handler because we need to treat this as a recovery */ 32 queue_work(priv->wq, &gpu->recover_work); 33 } 34 35 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 36 { 37 struct a6xx_gmu *gmu = data; 38 u32 status; 39 40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 42 43 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 45 46 a6xx_gmu_fault(gmu); 47 } 48 49 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 50 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 51 52 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 53 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 54 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 55 56 return IRQ_HANDLED; 57 } 58 59 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 60 { 61 struct a6xx_gmu *gmu = data; 62 u32 status; 63 64 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 65 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 66 67 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 68 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 69 70 a6xx_gmu_fault(gmu); 71 } 72 73 return IRQ_HANDLED; 74 } 75 76 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 77 { 78 u32 val; 79 80 /* This can be called from gpu state code so make sure GMU is valid */ 81 if (!gmu->initialized) 82 return false; 83 84 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 85 86 return !(val & 87 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 88 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 89 } 90 91 /* Check to see if the GX rail is still powered */ 92 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 93 { 94 u32 val; 95 96 /* This can be called from gpu state code so make sure GMU is valid */ 97 if (!gmu->initialized) 98 return false; 99 100 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 101 102 return !(val & 103 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 104 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 105 } 106 107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 108 { 109 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 110 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 111 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 112 u32 perf_index; 113 unsigned long gpu_freq; 114 int ret = 0; 115 116 gpu_freq = dev_pm_opp_get_freq(opp); 117 118 if (gpu_freq == gmu->freq) 119 return; 120 121 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 122 if (gpu_freq == gmu->gpu_freqs[perf_index]) 123 break; 124 125 gmu->current_perf_index = perf_index; 126 gmu->freq = gmu->gpu_freqs[perf_index]; 127 128 trace_msm_gmu_freq_change(gmu->freq, perf_index); 129 130 /* 131 * This can get called from devfreq while the hardware is idle. Don't 132 * bring up the power if it isn't already active 133 */ 134 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 135 return; 136 137 if (!gmu->legacy) { 138 a6xx_hfi_set_freq(gmu, perf_index); 139 dev_pm_opp_set_bw(&gpu->pdev->dev, opp); 140 pm_runtime_put(gmu->dev); 141 return; 142 } 143 144 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 145 146 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 147 ((3 & 0xf) << 28) | perf_index); 148 149 /* 150 * Send an invalid index as a vote for the bus bandwidth and let the 151 * firmware decide on the right vote 152 */ 153 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 154 155 /* Set and clear the OOB for DCVS to trigger the GMU */ 156 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 157 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 158 159 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 160 if (ret) 161 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 162 163 dev_pm_opp_set_bw(&gpu->pdev->dev, opp); 164 pm_runtime_put(gmu->dev); 165 } 166 167 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 168 { 169 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 170 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 171 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 172 173 return gmu->freq; 174 } 175 176 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 177 { 178 u32 val; 179 int local = gmu->idle_level; 180 181 /* SPTP and IFPC both report as IFPC */ 182 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 183 local = GMU_IDLE_STATE_IFPC; 184 185 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 186 187 if (val == local) { 188 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 189 !a6xx_gmu_gx_is_on(gmu)) 190 return true; 191 } 192 193 return false; 194 } 195 196 /* Wait for the GMU to get to its most idle state */ 197 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 198 { 199 return spin_until(a6xx_gmu_check_idle_level(gmu)); 200 } 201 202 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 203 { 204 int ret; 205 u32 val; 206 u32 mask, reset_val; 207 208 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); 209 if (val <= 0x20010004) { 210 mask = 0xffffffff; 211 reset_val = 0xbabeface; 212 } else { 213 mask = 0x1ff; 214 reset_val = 0x100; 215 } 216 217 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 218 219 /* Set the log wptr index 220 * note: downstream saves the value in poweroff and restores it here 221 */ 222 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 223 224 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 225 226 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 227 (val & mask) == reset_val, 100, 10000); 228 229 if (ret) 230 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 231 232 return ret; 233 } 234 235 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 236 { 237 u32 val; 238 int ret; 239 240 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 241 242 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 243 val & 1, 100, 10000); 244 if (ret) 245 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 246 247 return ret; 248 } 249 250 /* Trigger a OOB (out of band) request to the GMU */ 251 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 252 { 253 int ret; 254 u32 val; 255 int request, ack; 256 const char *name; 257 258 switch (state) { 259 case GMU_OOB_GPU_SET: 260 if (gmu->legacy) { 261 request = GMU_OOB_GPU_SET_REQUEST; 262 ack = GMU_OOB_GPU_SET_ACK; 263 } else { 264 request = GMU_OOB_GPU_SET_REQUEST_NEW; 265 ack = GMU_OOB_GPU_SET_ACK_NEW; 266 } 267 name = "GPU_SET"; 268 break; 269 case GMU_OOB_BOOT_SLUMBER: 270 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 271 ack = GMU_OOB_BOOT_SLUMBER_ACK; 272 name = "BOOT_SLUMBER"; 273 break; 274 case GMU_OOB_DCVS_SET: 275 request = GMU_OOB_DCVS_REQUEST; 276 ack = GMU_OOB_DCVS_ACK; 277 name = "GPU_DCVS"; 278 break; 279 default: 280 return -EINVAL; 281 } 282 283 /* Trigger the equested OOB operation */ 284 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 285 286 /* Wait for the acknowledge interrupt */ 287 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 288 val & (1 << ack), 100, 10000); 289 290 if (ret) 291 DRM_DEV_ERROR(gmu->dev, 292 "Timeout waiting for GMU OOB set %s: 0x%x\n", 293 name, 294 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 295 296 /* Clear the acknowledge interrupt */ 297 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 298 299 return ret; 300 } 301 302 /* Clear a pending OOB state in the GMU */ 303 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 304 { 305 if (!gmu->legacy) { 306 WARN_ON(state != GMU_OOB_GPU_SET); 307 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 308 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 309 return; 310 } 311 312 switch (state) { 313 case GMU_OOB_GPU_SET: 314 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 315 1 << GMU_OOB_GPU_SET_CLEAR); 316 break; 317 case GMU_OOB_BOOT_SLUMBER: 318 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 319 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 320 break; 321 case GMU_OOB_DCVS_SET: 322 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 323 1 << GMU_OOB_DCVS_CLEAR); 324 break; 325 } 326 } 327 328 /* Enable CPU control of SPTP power power collapse */ 329 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 330 { 331 int ret; 332 u32 val; 333 334 if (!gmu->legacy) 335 return 0; 336 337 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 338 339 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 340 (val & 0x38) == 0x28, 1, 100); 341 342 if (ret) { 343 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 344 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 345 } 346 347 return 0; 348 } 349 350 /* Disable CPU control of SPTP power power collapse */ 351 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 352 { 353 u32 val; 354 int ret; 355 356 if (!gmu->legacy) 357 return; 358 359 /* Make sure retention is on */ 360 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 361 362 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 363 364 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 365 (val & 0x04), 100, 10000); 366 367 if (ret) 368 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 369 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 370 } 371 372 /* Let the GMU know we are starting a boot sequence */ 373 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 374 { 375 u32 vote; 376 377 /* Let the GMU know we are getting ready for boot */ 378 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 379 380 /* Choose the "default" power level as the highest available */ 381 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 382 383 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 384 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 385 386 /* Let the GMU know the boot sequence has started */ 387 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 388 } 389 390 /* Let the GMU know that we are about to go into slumber */ 391 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 392 { 393 int ret; 394 395 /* Disable the power counter so the GMU isn't busy */ 396 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 397 398 /* Disable SPTP_PC if the CPU is responsible for it */ 399 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 400 a6xx_sptprac_disable(gmu); 401 402 if (!gmu->legacy) { 403 ret = a6xx_hfi_send_prep_slumber(gmu); 404 goto out; 405 } 406 407 /* Tell the GMU to get ready to slumber */ 408 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 409 410 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 411 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 412 413 if (!ret) { 414 /* Check to see if the GMU really did slumber */ 415 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 416 != 0x0f) { 417 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 418 ret = -ETIMEDOUT; 419 } 420 } 421 422 out: 423 /* Put fence into allow mode */ 424 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 425 return ret; 426 } 427 428 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 429 { 430 int ret; 431 u32 val; 432 433 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 434 /* Wait for the register to finish posting */ 435 wmb(); 436 437 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 438 val & (1 << 1), 100, 10000); 439 if (ret) { 440 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 441 return ret; 442 } 443 444 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 445 !val, 100, 10000); 446 447 if (ret) { 448 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 449 return ret; 450 } 451 452 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 453 454 /* Set up CX GMU counter 0 to count busy ticks */ 455 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 456 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 457 458 /* Enable the power counter */ 459 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 460 return 0; 461 } 462 463 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 464 { 465 int ret; 466 u32 val; 467 468 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 469 470 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 471 val, val & (1 << 16), 100, 10000); 472 if (ret) 473 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 474 475 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 476 } 477 478 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 479 { 480 return msm_writel(value, ptr + (offset << 2)); 481 } 482 483 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 484 const char *name); 485 486 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 487 { 488 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 489 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 490 struct platform_device *pdev = to_platform_device(gmu->dev); 491 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 492 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 493 uint32_t pdc_address_offset; 494 495 if (!pdcptr || !seqptr) 496 goto err; 497 498 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) 499 pdc_address_offset = 0x30090; 500 else if (adreno_is_a650(adreno_gpu)) 501 pdc_address_offset = 0x300a0; 502 else 503 pdc_address_offset = 0x30080; 504 505 /* Disable SDE clock gating */ 506 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 507 508 /* Setup RSC PDC handshake for sleep and wakeup */ 509 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 510 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 511 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 512 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 513 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 514 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 515 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 516 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 517 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 518 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 519 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 520 521 /* Load RSC sequencer uCode for sleep and wakeup */ 522 if (adreno_is_a650(adreno_gpu)) { 523 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); 524 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); 525 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); 526 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); 527 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); 528 } else { 529 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 530 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 531 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 532 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 533 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 534 } 535 536 /* Load PDC sequencer uCode for power up and power down sequence */ 537 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 538 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 539 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 540 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 541 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 542 543 /* Set TCS commands used by PDC sequence for low power modes */ 544 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 546 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 547 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 549 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 551 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 553 554 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 555 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 557 558 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 559 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 560 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 561 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 562 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 564 565 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 566 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 567 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) 568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 569 else 570 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 571 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 572 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 573 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 574 575 /* Setup GPU PDC */ 576 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 577 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 578 579 /* ensure no writes happen before the uCode is fully written */ 580 wmb(); 581 582 err: 583 if (!IS_ERR_OR_NULL(pdcptr)) 584 iounmap(pdcptr); 585 if (!IS_ERR_OR_NULL(seqptr)) 586 iounmap(seqptr); 587 } 588 589 /* 590 * The lowest 16 bits of this value are the number of XO clock cycles for main 591 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 592 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 593 */ 594 595 #define GMU_PWR_COL_HYST 0x000a1680 596 597 /* Set up the idle state for the GMU */ 598 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 599 { 600 /* Disable GMU WB/RB buffer */ 601 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 602 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 603 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 604 605 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 606 607 switch (gmu->idle_level) { 608 case GMU_IDLE_STATE_IFPC: 609 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 610 GMU_PWR_COL_HYST); 611 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 612 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 613 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 614 fallthrough; 615 case GMU_IDLE_STATE_SPTP: 616 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 617 GMU_PWR_COL_HYST); 618 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 619 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 620 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 621 } 622 623 /* Enable RPMh GPU client */ 624 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 625 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 626 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 627 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 628 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 629 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 630 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 631 } 632 633 struct block_header { 634 u32 addr; 635 u32 size; 636 u32 type; 637 u32 value; 638 u32 data[]; 639 }; 640 641 /* this should be a general kernel helper */ 642 static int in_range(u32 addr, u32 start, u32 size) 643 { 644 return addr >= start && addr < start + size; 645 } 646 647 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 648 { 649 if (!in_range(blk->addr, bo->iova, bo->size)) 650 return false; 651 652 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 653 return true; 654 } 655 656 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 657 { 658 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 659 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 660 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 661 const struct block_header *blk; 662 u32 reg_offset; 663 664 u32 itcm_base = 0x00000000; 665 u32 dtcm_base = 0x00040000; 666 667 if (adreno_is_a650(adreno_gpu)) 668 dtcm_base = 0x10004000; 669 670 if (gmu->legacy) { 671 /* Sanity check the size of the firmware that was loaded */ 672 if (fw_image->size > 0x8000) { 673 DRM_DEV_ERROR(gmu->dev, 674 "GMU firmware is bigger than the available region\n"); 675 return -EINVAL; 676 } 677 678 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 679 (u32*) fw_image->data, fw_image->size); 680 return 0; 681 } 682 683 684 for (blk = (const struct block_header *) fw_image->data; 685 (const u8*) blk < fw_image->data + fw_image->size; 686 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 687 if (blk->size == 0) 688 continue; 689 690 if (in_range(blk->addr, itcm_base, SZ_16K)) { 691 reg_offset = (blk->addr - itcm_base) >> 2; 692 gmu_write_bulk(gmu, 693 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 694 blk->data, blk->size); 695 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 696 reg_offset = (blk->addr - dtcm_base) >> 2; 697 gmu_write_bulk(gmu, 698 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 699 blk->data, blk->size); 700 } else if (!fw_block_mem(&gmu->icache, blk) && 701 !fw_block_mem(&gmu->dcache, blk) && 702 !fw_block_mem(&gmu->dummy, blk)) { 703 DRM_DEV_ERROR(gmu->dev, 704 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 705 blk->addr, blk->size, blk->data[0]); 706 } 707 } 708 709 return 0; 710 } 711 712 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 713 { 714 static bool rpmh_init; 715 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 716 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 717 int ret; 718 u32 chipid; 719 720 if (adreno_is_a650(adreno_gpu)) 721 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 722 723 if (state == GMU_WARM_BOOT) { 724 ret = a6xx_rpmh_start(gmu); 725 if (ret) 726 return ret; 727 } else { 728 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 729 "GMU firmware is not loaded\n")) 730 return -ENOENT; 731 732 /* Turn on register retention */ 733 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 734 735 /* We only need to load the RPMh microcode once */ 736 if (!rpmh_init) { 737 a6xx_gmu_rpmh_init(gmu); 738 rpmh_init = true; 739 } else { 740 ret = a6xx_rpmh_start(gmu); 741 if (ret) 742 return ret; 743 } 744 745 ret = a6xx_gmu_fw_load(gmu); 746 if (ret) 747 return ret; 748 } 749 750 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 751 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 752 753 /* Write the iova of the HFI table */ 754 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 755 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 756 757 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 758 (1 << 31) | (0xa << 18) | (0xa0)); 759 760 chipid = adreno_gpu->rev.core << 24; 761 chipid |= adreno_gpu->rev.major << 16; 762 chipid |= adreno_gpu->rev.minor << 12; 763 chipid |= adreno_gpu->rev.patchid << 8; 764 765 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 766 767 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 768 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 769 770 /* Set up the lowest idle level on the GMU */ 771 a6xx_gmu_power_config(gmu); 772 773 ret = a6xx_gmu_start(gmu); 774 if (ret) 775 return ret; 776 777 if (gmu->legacy) { 778 ret = a6xx_gmu_gfx_rail_on(gmu); 779 if (ret) 780 return ret; 781 } 782 783 /* Enable SPTP_PC if the CPU is responsible for it */ 784 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 785 ret = a6xx_sptprac_enable(gmu); 786 if (ret) 787 return ret; 788 } 789 790 ret = a6xx_gmu_hfi_start(gmu); 791 if (ret) 792 return ret; 793 794 /* FIXME: Do we need this wmb() here? */ 795 wmb(); 796 797 return 0; 798 } 799 800 #define A6XX_HFI_IRQ_MASK \ 801 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 802 803 #define A6XX_GMU_IRQ_MASK \ 804 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 805 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 806 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 807 808 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 809 { 810 disable_irq(gmu->gmu_irq); 811 disable_irq(gmu->hfi_irq); 812 813 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 814 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 815 } 816 817 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 818 { 819 u32 val; 820 821 /* Make sure there are no outstanding RPMh votes */ 822 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 823 (val & 1), 100, 10000); 824 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 825 (val & 1), 100, 10000); 826 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 827 (val & 1), 100, 10000); 828 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 829 (val & 1), 100, 1000); 830 } 831 832 /* Force the GMU off in case it isn't responsive */ 833 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 834 { 835 /* Flush all the queues */ 836 a6xx_hfi_stop(gmu); 837 838 /* Stop the interrupts */ 839 a6xx_gmu_irq_disable(gmu); 840 841 /* Force off SPTP in case the GMU is managing it */ 842 a6xx_sptprac_disable(gmu); 843 844 /* Make sure there are no outstanding RPMh votes */ 845 a6xx_gmu_rpmh_off(gmu); 846 } 847 848 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 849 { 850 struct dev_pm_opp *gpu_opp; 851 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 852 853 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 854 if (IS_ERR_OR_NULL(gpu_opp)) 855 return; 856 857 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ 858 a6xx_gmu_set_freq(gpu, gpu_opp); 859 dev_pm_opp_put(gpu_opp); 860 } 861 862 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 863 { 864 struct dev_pm_opp *gpu_opp; 865 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 866 867 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 868 if (IS_ERR_OR_NULL(gpu_opp)) 869 return; 870 871 dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp); 872 dev_pm_opp_put(gpu_opp); 873 } 874 875 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 876 { 877 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 878 struct msm_gpu *gpu = &adreno_gpu->base; 879 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 880 int status, ret; 881 882 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 883 return 0; 884 885 gmu->hung = false; 886 887 /* Turn on the resources */ 888 pm_runtime_get_sync(gmu->dev); 889 890 /* 891 * "enable" the GX power domain which won't actually do anything but it 892 * will make sure that the refcounting is correct in case we need to 893 * bring down the GX after a GMU failure 894 */ 895 if (!IS_ERR_OR_NULL(gmu->gxpd)) 896 pm_runtime_get_sync(gmu->gxpd); 897 898 /* Use a known rate to bring up the GMU */ 899 clk_set_rate(gmu->core_clk, 200000000); 900 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 901 if (ret) { 902 pm_runtime_put(gmu->gxpd); 903 pm_runtime_put(gmu->dev); 904 return ret; 905 } 906 907 /* Set the bus quota to a reasonable value for boot */ 908 a6xx_gmu_set_initial_bw(gpu, gmu); 909 910 /* Enable the GMU interrupt */ 911 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 912 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 913 enable_irq(gmu->gmu_irq); 914 915 /* Check to see if we are doing a cold or warm boot */ 916 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 917 GMU_WARM_BOOT : GMU_COLD_BOOT; 918 919 /* 920 * Warm boot path does not work on newer GPUs 921 * Presumably this is because icache/dcache regions must be restored 922 */ 923 if (!gmu->legacy) 924 status = GMU_COLD_BOOT; 925 926 ret = a6xx_gmu_fw_start(gmu, status); 927 if (ret) 928 goto out; 929 930 ret = a6xx_hfi_start(gmu, status); 931 if (ret) 932 goto out; 933 934 /* 935 * Turn on the GMU firmware fault interrupt after we know the boot 936 * sequence is successful 937 */ 938 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 939 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 940 enable_irq(gmu->hfi_irq); 941 942 /* Set the GPU to the current freq */ 943 a6xx_gmu_set_initial_freq(gpu, gmu); 944 945 out: 946 /* On failure, shut down the GMU to leave it in a good state */ 947 if (ret) { 948 disable_irq(gmu->gmu_irq); 949 a6xx_rpmh_stop(gmu); 950 pm_runtime_put(gmu->gxpd); 951 pm_runtime_put(gmu->dev); 952 } 953 954 return ret; 955 } 956 957 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 958 { 959 u32 reg; 960 961 if (!gmu->initialized) 962 return true; 963 964 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 965 966 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 967 return false; 968 969 return true; 970 } 971 972 #define GBIF_CLIENT_HALT_MASK BIT(0) 973 #define GBIF_ARB_HALT_MASK BIT(1) 974 975 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 976 { 977 struct msm_gpu *gpu = &adreno_gpu->base; 978 979 if (!a6xx_has_gbif(adreno_gpu)) { 980 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 981 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 982 0xf) == 0xf); 983 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 984 985 return; 986 } 987 988 /* Halt new client requests on GBIF */ 989 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 990 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 991 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 992 993 /* Halt all AXI requests on GBIF */ 994 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 995 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 996 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 997 998 /* The GBIF halt needs to be explicitly cleared */ 999 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1000 } 1001 1002 /* Gracefully try to shut down the GMU and by extension the GPU */ 1003 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 1004 { 1005 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1006 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1007 u32 val; 1008 1009 /* 1010 * The GMU may still be in slumber unless the GPU started so check and 1011 * skip putting it back into slumber if so 1012 */ 1013 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 1014 1015 if (val != 0xf) { 1016 int ret = a6xx_gmu_wait_for_idle(gmu); 1017 1018 /* If the GMU isn't responding assume it is hung */ 1019 if (ret) { 1020 a6xx_gmu_force_off(gmu); 1021 return; 1022 } 1023 1024 a6xx_bus_clear_pending_transactions(adreno_gpu); 1025 1026 /* tell the GMU we want to slumber */ 1027 a6xx_gmu_notify_slumber(gmu); 1028 1029 ret = gmu_poll_timeout(gmu, 1030 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1031 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1032 100, 10000); 1033 1034 /* 1035 * Let the user know we failed to slumber but don't worry too 1036 * much because we are powering down anyway 1037 */ 1038 1039 if (ret) 1040 DRM_DEV_ERROR(gmu->dev, 1041 "Unable to slumber GMU: status = 0%x/0%x\n", 1042 gmu_read(gmu, 1043 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1044 gmu_read(gmu, 1045 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1046 } 1047 1048 /* Turn off HFI */ 1049 a6xx_hfi_stop(gmu); 1050 1051 /* Stop the interrupts and mask the hardware */ 1052 a6xx_gmu_irq_disable(gmu); 1053 1054 /* Tell RPMh to power off the GPU */ 1055 a6xx_rpmh_stop(gmu); 1056 } 1057 1058 1059 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1060 { 1061 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1062 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1063 1064 if (!pm_runtime_active(gmu->dev)) 1065 return 0; 1066 1067 /* 1068 * Force the GMU off if we detected a hang, otherwise try to shut it 1069 * down gracefully 1070 */ 1071 if (gmu->hung) 1072 a6xx_gmu_force_off(gmu); 1073 else 1074 a6xx_gmu_shutdown(gmu); 1075 1076 /* Remove the bus vote */ 1077 dev_pm_opp_set_bw(&gpu->pdev->dev, NULL); 1078 1079 /* 1080 * Make sure the GX domain is off before turning off the GMU (CX) 1081 * domain. Usually the GMU does this but only if the shutdown sequence 1082 * was successful 1083 */ 1084 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1085 pm_runtime_put_sync(gmu->gxpd); 1086 1087 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1088 1089 pm_runtime_put_sync(gmu->dev); 1090 1091 return 0; 1092 } 1093 1094 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1095 { 1096 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 1097 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 1098 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false); 1099 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false); 1100 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false); 1101 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false); 1102 1103 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1104 msm_gem_address_space_put(gmu->aspace); 1105 } 1106 1107 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1108 size_t size, u64 iova) 1109 { 1110 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1111 struct drm_device *dev = a6xx_gpu->base.base.dev; 1112 uint32_t flags = MSM_BO_WC; 1113 u64 range_start, range_end; 1114 int ret; 1115 1116 size = PAGE_ALIGN(size); 1117 if (!iova) { 1118 /* no fixed address - use GMU's uncached range */ 1119 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1120 range_end = 0x80000000; 1121 } else { 1122 /* range for fixed address */ 1123 range_start = iova; 1124 range_end = iova + size; 1125 /* use IOMMU_PRIV for icache/dcache */ 1126 flags |= MSM_BO_MAP_PRIV; 1127 } 1128 1129 bo->obj = msm_gem_new(dev, size, flags); 1130 if (IS_ERR(bo->obj)) 1131 return PTR_ERR(bo->obj); 1132 1133 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1134 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 1135 if (ret) { 1136 drm_gem_object_put(bo->obj); 1137 return ret; 1138 } 1139 1140 bo->virt = msm_gem_get_vaddr(bo->obj); 1141 bo->size = size; 1142 1143 return 0; 1144 } 1145 1146 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1147 { 1148 struct iommu_domain *domain; 1149 struct msm_mmu *mmu; 1150 1151 domain = iommu_domain_alloc(&platform_bus_type); 1152 if (!domain) 1153 return -ENODEV; 1154 1155 mmu = msm_iommu_new(gmu->dev, domain); 1156 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); 1157 if (IS_ERR(gmu->aspace)) { 1158 iommu_domain_free(domain); 1159 return PTR_ERR(gmu->aspace); 1160 } 1161 1162 return 0; 1163 } 1164 1165 /* Return the 'arc-level' for the given frequency */ 1166 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1167 unsigned long freq) 1168 { 1169 struct dev_pm_opp *opp; 1170 unsigned int val; 1171 1172 if (!freq) 1173 return 0; 1174 1175 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1176 if (IS_ERR(opp)) 1177 return 0; 1178 1179 val = dev_pm_opp_get_level(opp); 1180 1181 dev_pm_opp_put(opp); 1182 1183 return val; 1184 } 1185 1186 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1187 unsigned long *freqs, int freqs_count, const char *id) 1188 { 1189 int i, j; 1190 const u16 *pri, *sec; 1191 size_t pri_count, sec_count; 1192 1193 pri = cmd_db_read_aux_data(id, &pri_count); 1194 if (IS_ERR(pri)) 1195 return PTR_ERR(pri); 1196 /* 1197 * The data comes back as an array of unsigned shorts so adjust the 1198 * count accordingly 1199 */ 1200 pri_count >>= 1; 1201 if (!pri_count) 1202 return -EINVAL; 1203 1204 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1205 if (IS_ERR(sec)) 1206 return PTR_ERR(sec); 1207 1208 sec_count >>= 1; 1209 if (!sec_count) 1210 return -EINVAL; 1211 1212 /* Construct a vote for each frequency */ 1213 for (i = 0; i < freqs_count; i++) { 1214 u8 pindex = 0, sindex = 0; 1215 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1216 1217 /* Get the primary index that matches the arc level */ 1218 for (j = 0; j < pri_count; j++) { 1219 if (pri[j] >= level) { 1220 pindex = j; 1221 break; 1222 } 1223 } 1224 1225 if (j == pri_count) { 1226 DRM_DEV_ERROR(dev, 1227 "Level %u not found in the RPMh list\n", 1228 level); 1229 DRM_DEV_ERROR(dev, "Available levels:\n"); 1230 for (j = 0; j < pri_count; j++) 1231 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1232 1233 return -EINVAL; 1234 } 1235 1236 /* 1237 * Look for a level in in the secondary list that matches. If 1238 * nothing fits, use the maximum non zero vote 1239 */ 1240 1241 for (j = 0; j < sec_count; j++) { 1242 if (sec[j] >= level) { 1243 sindex = j; 1244 break; 1245 } else if (sec[j]) { 1246 sindex = j; 1247 } 1248 } 1249 1250 /* Construct the vote */ 1251 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1252 (sindex << 8) | pindex; 1253 } 1254 1255 return 0; 1256 } 1257 1258 /* 1259 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1260 * to construct the list of votes on the CPU and send it over. Query the RPMh 1261 * voltage levels and build the votes 1262 */ 1263 1264 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1265 { 1266 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1267 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1268 struct msm_gpu *gpu = &adreno_gpu->base; 1269 int ret; 1270 1271 /* Build the GX votes */ 1272 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1273 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1274 1275 /* Build the CX votes */ 1276 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1277 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1278 1279 return ret; 1280 } 1281 1282 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1283 u32 size) 1284 { 1285 int count = dev_pm_opp_get_opp_count(dev); 1286 struct dev_pm_opp *opp; 1287 int i, index = 0; 1288 unsigned long freq = 1; 1289 1290 /* 1291 * The OPP table doesn't contain the "off" frequency level so we need to 1292 * add 1 to the table size to account for it 1293 */ 1294 1295 if (WARN(count + 1 > size, 1296 "The GMU frequency table is being truncated\n")) 1297 count = size - 1; 1298 1299 /* Set the "off" frequency */ 1300 freqs[index++] = 0; 1301 1302 for (i = 0; i < count; i++) { 1303 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1304 if (IS_ERR(opp)) 1305 break; 1306 1307 dev_pm_opp_put(opp); 1308 freqs[index++] = freq++; 1309 } 1310 1311 return index; 1312 } 1313 1314 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1315 { 1316 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1317 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1318 struct msm_gpu *gpu = &adreno_gpu->base; 1319 1320 int ret = 0; 1321 1322 /* 1323 * The GMU handles its own frequency switching so build a list of 1324 * available frequencies to send during initialization 1325 */ 1326 ret = dev_pm_opp_of_add_table(gmu->dev); 1327 if (ret) { 1328 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1329 return ret; 1330 } 1331 1332 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1333 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1334 1335 /* 1336 * The GMU also handles GPU frequency switching so build a list 1337 * from the GPU OPP table 1338 */ 1339 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1340 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1341 1342 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1343 1344 /* Build the list of RPMh votes that we'll send to the GMU */ 1345 return a6xx_gmu_rpmh_votes_init(gmu); 1346 } 1347 1348 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1349 { 1350 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1351 1352 if (ret < 1) 1353 return ret; 1354 1355 gmu->nr_clocks = ret; 1356 1357 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1358 gmu->nr_clocks, "gmu"); 1359 1360 return 0; 1361 } 1362 1363 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1364 const char *name) 1365 { 1366 void __iomem *ret; 1367 struct resource *res = platform_get_resource_byname(pdev, 1368 IORESOURCE_MEM, name); 1369 1370 if (!res) { 1371 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1372 return ERR_PTR(-EINVAL); 1373 } 1374 1375 ret = ioremap(res->start, resource_size(res)); 1376 if (!ret) { 1377 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1378 return ERR_PTR(-EINVAL); 1379 } 1380 1381 return ret; 1382 } 1383 1384 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1385 const char *name, irq_handler_t handler) 1386 { 1387 int irq, ret; 1388 1389 irq = platform_get_irq_byname(pdev, name); 1390 1391 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1392 if (ret) { 1393 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1394 name, ret); 1395 return ret; 1396 } 1397 1398 disable_irq(irq); 1399 1400 return irq; 1401 } 1402 1403 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1404 { 1405 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1406 struct platform_device *pdev = to_platform_device(gmu->dev); 1407 1408 if (!gmu->initialized) 1409 return; 1410 1411 pm_runtime_force_suspend(gmu->dev); 1412 1413 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1414 pm_runtime_disable(gmu->gxpd); 1415 dev_pm_domain_detach(gmu->gxpd, false); 1416 } 1417 1418 iounmap(gmu->mmio); 1419 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1420 iounmap(gmu->rscc); 1421 gmu->mmio = NULL; 1422 gmu->rscc = NULL; 1423 1424 a6xx_gmu_memory_free(gmu); 1425 1426 free_irq(gmu->gmu_irq, gmu); 1427 free_irq(gmu->hfi_irq, gmu); 1428 1429 /* Drop reference taken in of_find_device_by_node */ 1430 put_device(gmu->dev); 1431 1432 gmu->initialized = false; 1433 } 1434 1435 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1436 { 1437 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1438 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1439 struct platform_device *pdev = of_find_device_by_node(node); 1440 int ret; 1441 1442 if (!pdev) 1443 return -ENODEV; 1444 1445 gmu->dev = &pdev->dev; 1446 1447 of_dma_configure(gmu->dev, node, true); 1448 1449 /* Fow now, don't do anything fancy until we get our feet under us */ 1450 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1451 1452 pm_runtime_enable(gmu->dev); 1453 1454 /* Get the list of clocks */ 1455 ret = a6xx_gmu_clocks_probe(gmu); 1456 if (ret) 1457 goto err_put_device; 1458 1459 ret = a6xx_gmu_memory_probe(gmu); 1460 if (ret) 1461 goto err_put_device; 1462 1463 /* Allocate memory for the GMU dummy page */ 1464 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); 1465 if (ret) 1466 goto err_memory; 1467 1468 if (adreno_is_a650(adreno_gpu)) { 1469 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1470 SZ_16M - SZ_16K, 0x04000); 1471 if (ret) 1472 goto err_memory; 1473 } else if (adreno_is_a640(adreno_gpu)) { 1474 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1475 SZ_256K - SZ_16K, 0x04000); 1476 if (ret) 1477 goto err_memory; 1478 1479 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1480 SZ_256K - SZ_16K, 0x44000); 1481 if (ret) 1482 goto err_memory; 1483 } else { 1484 /* HFI v1, has sptprac */ 1485 gmu->legacy = true; 1486 1487 /* Allocate memory for the GMU debug region */ 1488 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1489 if (ret) 1490 goto err_memory; 1491 } 1492 1493 /* Allocate memory for for the HFI queues */ 1494 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1495 if (ret) 1496 goto err_memory; 1497 1498 /* Allocate memory for the GMU log region */ 1499 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0); 1500 if (ret) 1501 goto err_memory; 1502 1503 /* Map the GMU registers */ 1504 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1505 if (IS_ERR(gmu->mmio)) { 1506 ret = PTR_ERR(gmu->mmio); 1507 goto err_memory; 1508 } 1509 1510 if (adreno_is_a650(adreno_gpu)) { 1511 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1512 if (IS_ERR(gmu->rscc)) 1513 goto err_mmio; 1514 } else { 1515 gmu->rscc = gmu->mmio + 0x23000; 1516 } 1517 1518 /* Get the HFI and GMU interrupts */ 1519 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1520 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1521 1522 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1523 goto err_mmio; 1524 1525 /* 1526 * Get a link to the GX power domain to reset the GPU in case of GMU 1527 * crash 1528 */ 1529 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1530 1531 /* Get the power levels for the GMU and GPU */ 1532 a6xx_gmu_pwrlevels_probe(gmu); 1533 1534 /* Set up the HFI queues */ 1535 a6xx_hfi_init(gmu); 1536 1537 gmu->initialized = true; 1538 1539 return 0; 1540 1541 err_mmio: 1542 iounmap(gmu->mmio); 1543 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1544 iounmap(gmu->rscc); 1545 free_irq(gmu->gmu_irq, gmu); 1546 free_irq(gmu->hfi_irq, gmu); 1547 1548 ret = -ENODEV; 1549 1550 err_memory: 1551 a6xx_gmu_memory_free(gmu); 1552 err_put_device: 1553 /* Drop reference taken in of_find_device_by_node */ 1554 put_device(gmu->dev); 1555 1556 return ret; 1557 } 1558