1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_mmu.h" 15 16 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 17 { 18 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 19 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 20 struct msm_gpu *gpu = &adreno_gpu->base; 21 struct drm_device *dev = gpu->dev; 22 struct msm_drm_private *priv = dev->dev_private; 23 24 /* FIXME: add a banner here */ 25 gmu->hung = true; 26 27 /* Turn off the hangcheck timer while we are resetting */ 28 del_timer(&gpu->hangcheck_timer); 29 30 /* Queue the GPU handler because we need to treat this as a recovery */ 31 queue_work(priv->wq, &gpu->recover_work); 32 } 33 34 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 35 { 36 struct a6xx_gmu *gmu = data; 37 u32 status; 38 39 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 40 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 41 42 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 43 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 44 45 a6xx_gmu_fault(gmu); 46 } 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 49 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 52 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 53 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 54 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 59 { 60 struct a6xx_gmu *gmu = data; 61 u32 status; 62 63 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 64 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 65 66 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 67 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 68 69 a6xx_gmu_fault(gmu); 70 } 71 72 return IRQ_HANDLED; 73 } 74 75 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 76 { 77 u32 val; 78 79 /* This can be called from gpu state code so make sure GMU is valid */ 80 if (!gmu->initialized) 81 return false; 82 83 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 84 85 return !(val & 86 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 87 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 88 } 89 90 /* Check to see if the GX rail is still powered */ 91 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 92 { 93 u32 val; 94 95 /* This can be called from gpu state code so make sure GMU is valid */ 96 if (!gmu->initialized) 97 return false; 98 99 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 100 101 return !(val & 102 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 103 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 104 } 105 106 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 107 { 108 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 109 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 110 struct msm_gpu *gpu = &adreno_gpu->base; 111 int ret; 112 113 /* 114 * This can get called from devfreq while the hardware is idle. Don't 115 * bring up the power if it isn't already active 116 */ 117 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 118 return; 119 120 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 121 122 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 123 ((3 & 0xf) << 28) | index); 124 125 /* 126 * Send an invalid index as a vote for the bus bandwidth and let the 127 * firmware decide on the right vote 128 */ 129 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 130 131 /* Set and clear the OOB for DCVS to trigger the GMU */ 132 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 133 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 134 135 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 136 if (ret) 137 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 138 139 /* 140 * Eventually we will want to scale the path vote with the frequency but 141 * for now leave it at max so that the performance is nominal. 142 */ 143 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 144 pm_runtime_put(gmu->dev); 145 } 146 147 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 148 { 149 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 150 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 151 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 152 u32 perf_index = 0; 153 154 if (freq == gmu->freq) 155 return; 156 157 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 158 if (freq == gmu->gpu_freqs[perf_index]) 159 break; 160 161 gmu->current_perf_index = perf_index; 162 163 if (gmu->legacy) 164 __a6xx_gmu_set_freq(gmu, perf_index); 165 else 166 a6xx_hfi_set_freq(gmu, perf_index); 167 168 gmu->freq = gmu->gpu_freqs[perf_index]; 169 } 170 171 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 172 { 173 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 174 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 175 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 176 177 return gmu->freq; 178 } 179 180 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 181 { 182 u32 val; 183 int local = gmu->idle_level; 184 185 /* SPTP and IFPC both report as IFPC */ 186 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 187 local = GMU_IDLE_STATE_IFPC; 188 189 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 190 191 if (val == local) { 192 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 193 !a6xx_gmu_gx_is_on(gmu)) 194 return true; 195 } 196 197 return false; 198 } 199 200 /* Wait for the GMU to get to its most idle state */ 201 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 202 { 203 return spin_until(a6xx_gmu_check_idle_level(gmu)); 204 } 205 206 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 207 { 208 int ret; 209 u32 val; 210 211 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 212 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 213 214 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 215 val == 0xbabeface, 100, 10000); 216 217 if (ret) 218 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 219 220 return ret; 221 } 222 223 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 224 { 225 u32 val; 226 int ret; 227 228 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 229 230 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 231 val & 1, 100, 10000); 232 if (ret) 233 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 234 235 return ret; 236 } 237 238 /* Trigger a OOB (out of band) request to the GMU */ 239 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 240 { 241 int ret; 242 u32 val; 243 int request, ack; 244 const char *name; 245 246 switch (state) { 247 case GMU_OOB_GPU_SET: 248 if (gmu->legacy) { 249 request = GMU_OOB_GPU_SET_REQUEST; 250 ack = GMU_OOB_GPU_SET_ACK; 251 } else { 252 request = GMU_OOB_GPU_SET_REQUEST_NEW; 253 ack = GMU_OOB_GPU_SET_ACK_NEW; 254 } 255 name = "GPU_SET"; 256 break; 257 case GMU_OOB_BOOT_SLUMBER: 258 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 259 ack = GMU_OOB_BOOT_SLUMBER_ACK; 260 name = "BOOT_SLUMBER"; 261 break; 262 case GMU_OOB_DCVS_SET: 263 request = GMU_OOB_DCVS_REQUEST; 264 ack = GMU_OOB_DCVS_ACK; 265 name = "GPU_DCVS"; 266 break; 267 default: 268 return -EINVAL; 269 } 270 271 /* Trigger the equested OOB operation */ 272 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 273 274 /* Wait for the acknowledge interrupt */ 275 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 276 val & (1 << ack), 100, 10000); 277 278 if (ret) 279 DRM_DEV_ERROR(gmu->dev, 280 "Timeout waiting for GMU OOB set %s: 0x%x\n", 281 name, 282 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 283 284 /* Clear the acknowledge interrupt */ 285 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 286 287 return ret; 288 } 289 290 /* Clear a pending OOB state in the GMU */ 291 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 292 { 293 if (!gmu->legacy) { 294 WARN_ON(state != GMU_OOB_GPU_SET); 295 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 296 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 297 return; 298 } 299 300 switch (state) { 301 case GMU_OOB_GPU_SET: 302 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 303 1 << GMU_OOB_GPU_SET_CLEAR); 304 break; 305 case GMU_OOB_BOOT_SLUMBER: 306 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 307 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 308 break; 309 case GMU_OOB_DCVS_SET: 310 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 311 1 << GMU_OOB_DCVS_CLEAR); 312 break; 313 } 314 } 315 316 /* Enable CPU control of SPTP power power collapse */ 317 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 318 { 319 int ret; 320 u32 val; 321 322 if (!gmu->legacy) 323 return 0; 324 325 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 326 327 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 328 (val & 0x38) == 0x28, 1, 100); 329 330 if (ret) { 331 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 332 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 333 } 334 335 return 0; 336 } 337 338 /* Disable CPU control of SPTP power power collapse */ 339 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 340 { 341 u32 val; 342 int ret; 343 344 if (!gmu->legacy) 345 return; 346 347 /* Make sure retention is on */ 348 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 349 350 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 351 352 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 353 (val & 0x04), 100, 10000); 354 355 if (ret) 356 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 357 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 358 } 359 360 /* Let the GMU know we are starting a boot sequence */ 361 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 362 { 363 u32 vote; 364 365 /* Let the GMU know we are getting ready for boot */ 366 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 367 368 /* Choose the "default" power level as the highest available */ 369 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 370 371 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 372 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 373 374 /* Let the GMU know the boot sequence has started */ 375 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 376 } 377 378 /* Let the GMU know that we are about to go into slumber */ 379 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 380 { 381 int ret; 382 383 /* Disable the power counter so the GMU isn't busy */ 384 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 385 386 /* Disable SPTP_PC if the CPU is responsible for it */ 387 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 388 a6xx_sptprac_disable(gmu); 389 390 if (!gmu->legacy) { 391 ret = a6xx_hfi_send_prep_slumber(gmu); 392 goto out; 393 } 394 395 /* Tell the GMU to get ready to slumber */ 396 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 397 398 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 399 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 400 401 if (!ret) { 402 /* Check to see if the GMU really did slumber */ 403 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 404 != 0x0f) { 405 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 406 ret = -ETIMEDOUT; 407 } 408 } 409 410 out: 411 /* Put fence into allow mode */ 412 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 413 return ret; 414 } 415 416 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 417 { 418 int ret; 419 u32 val; 420 421 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 422 /* Wait for the register to finish posting */ 423 wmb(); 424 425 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 426 val & (1 << 1), 100, 10000); 427 if (ret) { 428 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 429 return ret; 430 } 431 432 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 433 !val, 100, 10000); 434 435 if (ret) { 436 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 437 return ret; 438 } 439 440 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 441 442 /* Set up CX GMU counter 0 to count busy ticks */ 443 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 444 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 445 446 /* Enable the power counter */ 447 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 448 return 0; 449 } 450 451 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 452 { 453 int ret; 454 u32 val; 455 456 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 457 458 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 459 val, val & (1 << 16), 100, 10000); 460 if (ret) 461 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 462 463 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 464 } 465 466 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 467 { 468 return msm_writel(value, ptr + (offset << 2)); 469 } 470 471 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 472 const char *name); 473 474 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 475 { 476 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 477 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 478 struct platform_device *pdev = to_platform_device(gmu->dev); 479 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 480 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 481 482 if (!pdcptr || !seqptr) 483 goto err; 484 485 /* Disable SDE clock gating */ 486 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 487 488 /* Setup RSC PDC handshake for sleep and wakeup */ 489 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 490 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 491 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 492 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 493 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 494 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 495 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 496 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 497 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 498 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 499 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 500 501 /* Load RSC sequencer uCode for sleep and wakeup */ 502 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 503 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 504 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 505 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 506 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 507 508 /* Load PDC sequencer uCode for power up and power down sequence */ 509 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 510 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 511 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 512 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 513 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 514 515 /* Set TCS commands used by PDC sequence for low power modes */ 516 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 517 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 518 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 519 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 520 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 521 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 522 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 523 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 524 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 525 526 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 527 if (adreno_is_a618(adreno_gpu)) 528 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090); 529 else 530 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 531 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 532 533 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 534 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 535 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 536 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 537 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 538 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 539 540 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 541 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 542 if (adreno_is_a618(adreno_gpu)) 543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 544 else 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 546 547 548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 549 if (adreno_is_a618(adreno_gpu)) 550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090); 551 else 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 554 555 /* Setup GPU PDC */ 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 558 559 /* ensure no writes happen before the uCode is fully written */ 560 wmb(); 561 562 err: 563 if (!IS_ERR_OR_NULL(pdcptr)) 564 iounmap(pdcptr); 565 if (!IS_ERR_OR_NULL(seqptr)) 566 iounmap(seqptr); 567 } 568 569 /* 570 * The lowest 16 bits of this value are the number of XO clock cycles for main 571 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 572 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 573 */ 574 575 #define GMU_PWR_COL_HYST 0x000a1680 576 577 /* Set up the idle state for the GMU */ 578 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 579 { 580 /* Disable GMU WB/RB buffer */ 581 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 582 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 583 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 584 585 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 586 587 switch (gmu->idle_level) { 588 case GMU_IDLE_STATE_IFPC: 589 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 590 GMU_PWR_COL_HYST); 591 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 592 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 593 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 594 /* Fall through */ 595 case GMU_IDLE_STATE_SPTP: 596 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 597 GMU_PWR_COL_HYST); 598 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 599 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 600 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 601 } 602 603 /* Enable RPMh GPU client */ 604 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 605 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 606 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 607 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 608 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 609 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 610 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 611 } 612 613 struct block_header { 614 u32 addr; 615 u32 size; 616 u32 type; 617 u32 value; 618 u32 data[]; 619 }; 620 621 /* this should be a general kernel helper */ 622 static int in_range(u32 addr, u32 start, u32 size) 623 { 624 return addr >= start && addr < start + size; 625 } 626 627 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 628 { 629 if (!in_range(blk->addr, bo->iova, bo->size)) 630 return false; 631 632 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 633 return true; 634 } 635 636 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 637 { 638 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 639 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 640 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 641 const struct block_header *blk; 642 u32 reg_offset; 643 644 u32 itcm_base = 0x00000000; 645 u32 dtcm_base = 0x00040000; 646 647 if (adreno_is_a650(adreno_gpu)) 648 dtcm_base = 0x10004000; 649 650 if (gmu->legacy) { 651 /* Sanity check the size of the firmware that was loaded */ 652 if (fw_image->size > 0x8000) { 653 DRM_DEV_ERROR(gmu->dev, 654 "GMU firmware is bigger than the available region\n"); 655 return -EINVAL; 656 } 657 658 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 659 (u32*) fw_image->data, fw_image->size); 660 return 0; 661 } 662 663 664 for (blk = (const struct block_header *) fw_image->data; 665 (const u8*) blk < fw_image->data + fw_image->size; 666 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 667 if (blk->size == 0) 668 continue; 669 670 if (in_range(blk->addr, itcm_base, SZ_16K)) { 671 reg_offset = (blk->addr - itcm_base) >> 2; 672 gmu_write_bulk(gmu, 673 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 674 blk->data, blk->size); 675 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 676 reg_offset = (blk->addr - dtcm_base) >> 2; 677 gmu_write_bulk(gmu, 678 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 679 blk->data, blk->size); 680 } else if (!fw_block_mem(&gmu->icache, blk) && 681 !fw_block_mem(&gmu->dcache, blk) && 682 !fw_block_mem(&gmu->dummy, blk)) { 683 DRM_DEV_ERROR(gmu->dev, 684 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 685 blk->addr, blk->size, blk->data[0]); 686 } 687 } 688 689 return 0; 690 } 691 692 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 693 { 694 static bool rpmh_init; 695 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 696 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 697 int ret; 698 u32 chipid; 699 700 if (adreno_is_a650(adreno_gpu)) 701 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 702 703 if (state == GMU_WARM_BOOT) { 704 ret = a6xx_rpmh_start(gmu); 705 if (ret) 706 return ret; 707 } else { 708 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 709 "GMU firmware is not loaded\n")) 710 return -ENOENT; 711 712 /* Turn on register retention */ 713 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 714 715 /* We only need to load the RPMh microcode once */ 716 if (!rpmh_init) { 717 a6xx_gmu_rpmh_init(gmu); 718 rpmh_init = true; 719 } else { 720 ret = a6xx_rpmh_start(gmu); 721 if (ret) 722 return ret; 723 } 724 725 ret = a6xx_gmu_fw_load(gmu); 726 if (ret) 727 return ret; 728 } 729 730 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 731 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 732 733 /* Write the iova of the HFI table */ 734 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 735 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 736 737 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 738 (1 << 31) | (0xa << 18) | (0xa0)); 739 740 chipid = adreno_gpu->rev.core << 24; 741 chipid |= adreno_gpu->rev.major << 16; 742 chipid |= adreno_gpu->rev.minor << 12; 743 chipid |= adreno_gpu->rev.patchid << 8; 744 745 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 746 747 /* Set up the lowest idle level on the GMU */ 748 a6xx_gmu_power_config(gmu); 749 750 ret = a6xx_gmu_start(gmu); 751 if (ret) 752 return ret; 753 754 if (gmu->legacy) { 755 ret = a6xx_gmu_gfx_rail_on(gmu); 756 if (ret) 757 return ret; 758 } 759 760 /* Enable SPTP_PC if the CPU is responsible for it */ 761 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 762 ret = a6xx_sptprac_enable(gmu); 763 if (ret) 764 return ret; 765 } 766 767 ret = a6xx_gmu_hfi_start(gmu); 768 if (ret) 769 return ret; 770 771 /* FIXME: Do we need this wmb() here? */ 772 wmb(); 773 774 return 0; 775 } 776 777 #define A6XX_HFI_IRQ_MASK \ 778 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 779 780 #define A6XX_GMU_IRQ_MASK \ 781 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 782 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 783 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 784 785 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 786 { 787 disable_irq(gmu->gmu_irq); 788 disable_irq(gmu->hfi_irq); 789 790 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 791 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 792 } 793 794 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 795 { 796 u32 val; 797 798 /* Make sure there are no outstanding RPMh votes */ 799 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 800 (val & 1), 100, 10000); 801 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 802 (val & 1), 100, 10000); 803 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 804 (val & 1), 100, 10000); 805 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 806 (val & 1), 100, 1000); 807 } 808 809 /* Force the GMU off in case it isn't responsive */ 810 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 811 { 812 /* Flush all the queues */ 813 a6xx_hfi_stop(gmu); 814 815 /* Stop the interrupts */ 816 a6xx_gmu_irq_disable(gmu); 817 818 /* Force off SPTP in case the GMU is managing it */ 819 a6xx_sptprac_disable(gmu); 820 821 /* Make sure there are no outstanding RPMh votes */ 822 a6xx_gmu_rpmh_off(gmu); 823 } 824 825 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 826 { 827 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 828 struct msm_gpu *gpu = &adreno_gpu->base; 829 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 830 int status, ret; 831 832 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 833 return 0; 834 835 gmu->hung = false; 836 837 /* Turn on the resources */ 838 pm_runtime_get_sync(gmu->dev); 839 840 /* Use a known rate to bring up the GMU */ 841 clk_set_rate(gmu->core_clk, 200000000); 842 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 843 if (ret) { 844 pm_runtime_put(gmu->dev); 845 return ret; 846 } 847 848 /* Set the bus quota to a reasonable value for boot */ 849 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 850 851 /* Enable the GMU interrupt */ 852 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 853 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 854 enable_irq(gmu->gmu_irq); 855 856 /* Check to see if we are doing a cold or warm boot */ 857 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 858 GMU_WARM_BOOT : GMU_COLD_BOOT; 859 860 /* 861 * Warm boot path does not work on newer GPUs 862 * Presumably this is because icache/dcache regions must be restored 863 */ 864 if (!gmu->legacy) 865 status = GMU_COLD_BOOT; 866 867 ret = a6xx_gmu_fw_start(gmu, status); 868 if (ret) 869 goto out; 870 871 ret = a6xx_hfi_start(gmu, status); 872 if (ret) 873 goto out; 874 875 /* 876 * Turn on the GMU firmware fault interrupt after we know the boot 877 * sequence is successful 878 */ 879 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 880 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 881 enable_irq(gmu->hfi_irq); 882 883 /* Set the GPU to the current freq */ 884 if (gmu->legacy) 885 __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); 886 else 887 a6xx_hfi_set_freq(gmu, gmu->current_perf_index); 888 889 /* 890 * "enable" the GX power domain which won't actually do anything but it 891 * will make sure that the refcounting is correct in case we need to 892 * bring down the GX after a GMU failure 893 */ 894 if (!IS_ERR_OR_NULL(gmu->gxpd)) 895 pm_runtime_get(gmu->gxpd); 896 897 out: 898 /* On failure, shut down the GMU to leave it in a good state */ 899 if (ret) { 900 disable_irq(gmu->gmu_irq); 901 a6xx_rpmh_stop(gmu); 902 pm_runtime_put(gmu->dev); 903 } 904 905 return ret; 906 } 907 908 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 909 { 910 u32 reg; 911 912 if (!gmu->initialized) 913 return true; 914 915 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 916 917 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 918 return false; 919 920 return true; 921 } 922 923 #define GBIF_CLIENT_HALT_MASK BIT(0) 924 #define GBIF_ARB_HALT_MASK BIT(1) 925 926 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 927 { 928 struct msm_gpu *gpu = &adreno_gpu->base; 929 930 if (!a6xx_has_gbif(adreno_gpu)) { 931 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 932 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 933 0xf) == 0xf); 934 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 935 936 return; 937 } 938 939 /* Halt new client requests on GBIF */ 940 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 941 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 942 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 943 944 /* Halt all AXI requests on GBIF */ 945 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 946 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 947 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 948 949 /* The GBIF halt needs to be explicitly cleared */ 950 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 951 } 952 953 /* Gracefully try to shut down the GMU and by extension the GPU */ 954 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 955 { 956 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 957 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 958 u32 val; 959 960 /* 961 * The GMU may still be in slumber unless the GPU started so check and 962 * skip putting it back into slumber if so 963 */ 964 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 965 966 if (val != 0xf) { 967 int ret = a6xx_gmu_wait_for_idle(gmu); 968 969 /* If the GMU isn't responding assume it is hung */ 970 if (ret) { 971 a6xx_gmu_force_off(gmu); 972 return; 973 } 974 975 a6xx_bus_clear_pending_transactions(adreno_gpu); 976 977 /* tell the GMU we want to slumber */ 978 a6xx_gmu_notify_slumber(gmu); 979 980 ret = gmu_poll_timeout(gmu, 981 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 982 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 983 100, 10000); 984 985 /* 986 * Let the user know we failed to slumber but don't worry too 987 * much because we are powering down anyway 988 */ 989 990 if (ret) 991 DRM_DEV_ERROR(gmu->dev, 992 "Unable to slumber GMU: status = 0%x/0%x\n", 993 gmu_read(gmu, 994 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 995 gmu_read(gmu, 996 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 997 } 998 999 /* Turn off HFI */ 1000 a6xx_hfi_stop(gmu); 1001 1002 /* Stop the interrupts and mask the hardware */ 1003 a6xx_gmu_irq_disable(gmu); 1004 1005 /* Tell RPMh to power off the GPU */ 1006 a6xx_rpmh_stop(gmu); 1007 } 1008 1009 1010 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1011 { 1012 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1013 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1014 1015 if (!pm_runtime_active(gmu->dev)) 1016 return 0; 1017 1018 /* 1019 * Force the GMU off if we detected a hang, otherwise try to shut it 1020 * down gracefully 1021 */ 1022 if (gmu->hung) 1023 a6xx_gmu_force_off(gmu); 1024 else 1025 a6xx_gmu_shutdown(gmu); 1026 1027 /* Remove the bus vote */ 1028 icc_set_bw(gpu->icc_path, 0, 0); 1029 1030 /* 1031 * Make sure the GX domain is off before turning off the GMU (CX) 1032 * domain. Usually the GMU does this but only if the shutdown sequence 1033 * was successful 1034 */ 1035 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1036 pm_runtime_put_sync(gmu->gxpd); 1037 1038 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1039 1040 pm_runtime_put_sync(gmu->dev); 1041 1042 return 0; 1043 } 1044 1045 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1046 { 1047 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 1048 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 1049 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false); 1050 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false); 1051 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false); 1052 1053 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1054 msm_gem_address_space_put(gmu->aspace); 1055 } 1056 1057 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1058 size_t size, u64 iova) 1059 { 1060 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1061 struct drm_device *dev = a6xx_gpu->base.base.dev; 1062 uint32_t flags = MSM_BO_WC; 1063 u64 range_start, range_end; 1064 int ret; 1065 1066 size = PAGE_ALIGN(size); 1067 if (!iova) { 1068 /* no fixed address - use GMU's uncached range */ 1069 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1070 range_end = 0x80000000; 1071 } else { 1072 /* range for fixed address */ 1073 range_start = iova; 1074 range_end = iova + size; 1075 /* use IOMMU_PRIV for icache/dcache */ 1076 flags |= MSM_BO_MAP_PRIV; 1077 } 1078 1079 bo->obj = msm_gem_new(dev, size, flags); 1080 if (IS_ERR(bo->obj)) 1081 return PTR_ERR(bo->obj); 1082 1083 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1084 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 1085 if (ret) { 1086 drm_gem_object_put(bo->obj); 1087 return ret; 1088 } 1089 1090 bo->virt = msm_gem_get_vaddr(bo->obj); 1091 bo->size = size; 1092 1093 return 0; 1094 } 1095 1096 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1097 { 1098 struct iommu_domain *domain; 1099 int ret; 1100 1101 domain = iommu_domain_alloc(&platform_bus_type); 1102 if (!domain) 1103 return -ENODEV; 1104 1105 domain->geometry.aperture_start = 0x00000000; 1106 domain->geometry.aperture_end = 0x7fffffff; 1107 1108 gmu->aspace = msm_gem_address_space_create(gmu->dev, domain, "gmu"); 1109 if (IS_ERR(gmu->aspace)) { 1110 iommu_domain_free(domain); 1111 return PTR_ERR(gmu->aspace); 1112 } 1113 1114 ret = gmu->aspace->mmu->funcs->attach(gmu->aspace->mmu); 1115 if (ret) { 1116 msm_gem_address_space_put(gmu->aspace); 1117 return ret; 1118 } 1119 1120 return 0; 1121 } 1122 1123 /* Return the 'arc-level' for the given frequency */ 1124 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1125 unsigned long freq) 1126 { 1127 struct dev_pm_opp *opp; 1128 unsigned int val; 1129 1130 if (!freq) 1131 return 0; 1132 1133 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1134 if (IS_ERR(opp)) 1135 return 0; 1136 1137 val = dev_pm_opp_get_level(opp); 1138 1139 dev_pm_opp_put(opp); 1140 1141 return val; 1142 } 1143 1144 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1145 unsigned long *freqs, int freqs_count, const char *id) 1146 { 1147 int i, j; 1148 const u16 *pri, *sec; 1149 size_t pri_count, sec_count; 1150 1151 pri = cmd_db_read_aux_data(id, &pri_count); 1152 if (IS_ERR(pri)) 1153 return PTR_ERR(pri); 1154 /* 1155 * The data comes back as an array of unsigned shorts so adjust the 1156 * count accordingly 1157 */ 1158 pri_count >>= 1; 1159 if (!pri_count) 1160 return -EINVAL; 1161 1162 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1163 if (IS_ERR(sec)) 1164 return PTR_ERR(sec); 1165 1166 sec_count >>= 1; 1167 if (!sec_count) 1168 return -EINVAL; 1169 1170 /* Construct a vote for each frequency */ 1171 for (i = 0; i < freqs_count; i++) { 1172 u8 pindex = 0, sindex = 0; 1173 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1174 1175 /* Get the primary index that matches the arc level */ 1176 for (j = 0; j < pri_count; j++) { 1177 if (pri[j] >= level) { 1178 pindex = j; 1179 break; 1180 } 1181 } 1182 1183 if (j == pri_count) { 1184 DRM_DEV_ERROR(dev, 1185 "Level %u not found in the RPMh list\n", 1186 level); 1187 DRM_DEV_ERROR(dev, "Available levels:\n"); 1188 for (j = 0; j < pri_count; j++) 1189 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1190 1191 return -EINVAL; 1192 } 1193 1194 /* 1195 * Look for a level in in the secondary list that matches. If 1196 * nothing fits, use the maximum non zero vote 1197 */ 1198 1199 for (j = 0; j < sec_count; j++) { 1200 if (sec[j] >= level) { 1201 sindex = j; 1202 break; 1203 } else if (sec[j]) { 1204 sindex = j; 1205 } 1206 } 1207 1208 /* Construct the vote */ 1209 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1210 (sindex << 8) | pindex; 1211 } 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1218 * to construct the list of votes on the CPU and send it over. Query the RPMh 1219 * voltage levels and build the votes 1220 */ 1221 1222 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1223 { 1224 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1225 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1226 struct msm_gpu *gpu = &adreno_gpu->base; 1227 int ret; 1228 1229 /* Build the GX votes */ 1230 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1231 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1232 1233 /* Build the CX votes */ 1234 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1235 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1236 1237 return ret; 1238 } 1239 1240 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1241 u32 size) 1242 { 1243 int count = dev_pm_opp_get_opp_count(dev); 1244 struct dev_pm_opp *opp; 1245 int i, index = 0; 1246 unsigned long freq = 1; 1247 1248 /* 1249 * The OPP table doesn't contain the "off" frequency level so we need to 1250 * add 1 to the table size to account for it 1251 */ 1252 1253 if (WARN(count + 1 > size, 1254 "The GMU frequency table is being truncated\n")) 1255 count = size - 1; 1256 1257 /* Set the "off" frequency */ 1258 freqs[index++] = 0; 1259 1260 for (i = 0; i < count; i++) { 1261 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1262 if (IS_ERR(opp)) 1263 break; 1264 1265 dev_pm_opp_put(opp); 1266 freqs[index++] = freq++; 1267 } 1268 1269 return index; 1270 } 1271 1272 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1273 { 1274 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1275 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1276 struct msm_gpu *gpu = &adreno_gpu->base; 1277 1278 int ret = 0; 1279 1280 /* 1281 * The GMU handles its own frequency switching so build a list of 1282 * available frequencies to send during initialization 1283 */ 1284 ret = dev_pm_opp_of_add_table(gmu->dev); 1285 if (ret) { 1286 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1287 return ret; 1288 } 1289 1290 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1291 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1292 1293 /* 1294 * The GMU also handles GPU frequency switching so build a list 1295 * from the GPU OPP table 1296 */ 1297 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1298 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1299 1300 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1301 1302 /* Build the list of RPMh votes that we'll send to the GMU */ 1303 return a6xx_gmu_rpmh_votes_init(gmu); 1304 } 1305 1306 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1307 { 1308 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1309 1310 if (ret < 1) 1311 return ret; 1312 1313 gmu->nr_clocks = ret; 1314 1315 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1316 gmu->nr_clocks, "gmu"); 1317 1318 return 0; 1319 } 1320 1321 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1322 const char *name) 1323 { 1324 void __iomem *ret; 1325 struct resource *res = platform_get_resource_byname(pdev, 1326 IORESOURCE_MEM, name); 1327 1328 if (!res) { 1329 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1330 return ERR_PTR(-EINVAL); 1331 } 1332 1333 ret = ioremap(res->start, resource_size(res)); 1334 if (!ret) { 1335 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1336 return ERR_PTR(-EINVAL); 1337 } 1338 1339 return ret; 1340 } 1341 1342 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1343 const char *name, irq_handler_t handler) 1344 { 1345 int irq, ret; 1346 1347 irq = platform_get_irq_byname(pdev, name); 1348 1349 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1350 if (ret) { 1351 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1352 name, ret); 1353 return ret; 1354 } 1355 1356 disable_irq(irq); 1357 1358 return irq; 1359 } 1360 1361 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1362 { 1363 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1364 1365 if (!gmu->initialized) 1366 return; 1367 1368 pm_runtime_force_suspend(gmu->dev); 1369 1370 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1371 pm_runtime_disable(gmu->gxpd); 1372 dev_pm_domain_detach(gmu->gxpd, false); 1373 } 1374 1375 iounmap(gmu->mmio); 1376 gmu->mmio = NULL; 1377 1378 a6xx_gmu_memory_free(gmu); 1379 1380 free_irq(gmu->gmu_irq, gmu); 1381 free_irq(gmu->hfi_irq, gmu); 1382 1383 /* Drop reference taken in of_find_device_by_node */ 1384 put_device(gmu->dev); 1385 1386 gmu->initialized = false; 1387 } 1388 1389 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1390 { 1391 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1392 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1393 struct platform_device *pdev = of_find_device_by_node(node); 1394 int ret; 1395 1396 if (!pdev) 1397 return -ENODEV; 1398 1399 gmu->dev = &pdev->dev; 1400 1401 of_dma_configure(gmu->dev, node, true); 1402 1403 /* Fow now, don't do anything fancy until we get our feet under us */ 1404 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1405 1406 pm_runtime_enable(gmu->dev); 1407 1408 /* Get the list of clocks */ 1409 ret = a6xx_gmu_clocks_probe(gmu); 1410 if (ret) 1411 goto err_put_device; 1412 1413 ret = a6xx_gmu_memory_probe(gmu); 1414 if (ret) 1415 goto err_put_device; 1416 1417 /* Allocate memory for the GMU dummy page */ 1418 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); 1419 if (ret) 1420 goto err_memory; 1421 1422 if (adreno_is_a650(adreno_gpu)) { 1423 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1424 SZ_16M - SZ_16K, 0x04000); 1425 if (ret) 1426 goto err_memory; 1427 } else if (adreno_is_a640(adreno_gpu)) { 1428 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1429 SZ_256K - SZ_16K, 0x04000); 1430 if (ret) 1431 goto err_memory; 1432 1433 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1434 SZ_256K - SZ_16K, 0x44000); 1435 if (ret) 1436 goto err_memory; 1437 } else { 1438 /* HFI v1, has sptprac */ 1439 gmu->legacy = true; 1440 1441 /* Allocate memory for the GMU debug region */ 1442 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1443 if (ret) 1444 goto err_memory; 1445 } 1446 1447 /* Allocate memory for for the HFI queues */ 1448 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1449 if (ret) 1450 goto err_memory; 1451 1452 /* Map the GMU registers */ 1453 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1454 if (IS_ERR(gmu->mmio)) { 1455 ret = PTR_ERR(gmu->mmio); 1456 goto err_memory; 1457 } 1458 1459 /* Get the HFI and GMU interrupts */ 1460 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1461 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1462 1463 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1464 goto err_mmio; 1465 1466 /* 1467 * Get a link to the GX power domain to reset the GPU in case of GMU 1468 * crash 1469 */ 1470 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1471 1472 /* Get the power levels for the GMU and GPU */ 1473 a6xx_gmu_pwrlevels_probe(gmu); 1474 1475 /* Set up the HFI queues */ 1476 a6xx_hfi_init(gmu); 1477 1478 gmu->initialized = true; 1479 1480 return 0; 1481 1482 err_mmio: 1483 iounmap(gmu->mmio); 1484 free_irq(gmu->gmu_irq, gmu); 1485 free_irq(gmu->hfi_irq, gmu); 1486 1487 ret = -ENODEV; 1488 1489 err_memory: 1490 a6xx_gmu_memory_free(gmu); 1491 err_put_device: 1492 /* Drop reference taken in of_find_device_by_node */ 1493 put_device(gmu->dev); 1494 1495 return ret; 1496 } 1497