1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_mmu.h" 15 16 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 17 { 18 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 19 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 20 struct msm_gpu *gpu = &adreno_gpu->base; 21 struct drm_device *dev = gpu->dev; 22 struct msm_drm_private *priv = dev->dev_private; 23 24 /* FIXME: add a banner here */ 25 gmu->hung = true; 26 27 /* Turn off the hangcheck timer while we are resetting */ 28 del_timer(&gpu->hangcheck_timer); 29 30 /* Queue the GPU handler because we need to treat this as a recovery */ 31 queue_work(priv->wq, &gpu->recover_work); 32 } 33 34 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 35 { 36 struct a6xx_gmu *gmu = data; 37 u32 status; 38 39 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 40 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 41 42 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 43 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 44 45 a6xx_gmu_fault(gmu); 46 } 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 49 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 52 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 53 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 54 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 59 { 60 struct a6xx_gmu *gmu = data; 61 u32 status; 62 63 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 64 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 65 66 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 67 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 68 69 a6xx_gmu_fault(gmu); 70 } 71 72 return IRQ_HANDLED; 73 } 74 75 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 76 { 77 u32 val; 78 79 /* This can be called from gpu state code so make sure GMU is valid */ 80 if (!gmu->initialized) 81 return false; 82 83 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 84 85 return !(val & 86 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 87 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 88 } 89 90 /* Check to see if the GX rail is still powered */ 91 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 92 { 93 u32 val; 94 95 /* This can be called from gpu state code so make sure GMU is valid */ 96 if (!gmu->initialized) 97 return false; 98 99 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 100 101 return !(val & 102 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 103 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 104 } 105 106 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 107 { 108 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 109 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 110 struct msm_gpu *gpu = &adreno_gpu->base; 111 int ret; 112 113 /* 114 * This can get called from devfreq while the hardware is idle. Don't 115 * bring up the power if it isn't already active 116 */ 117 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 118 return; 119 120 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 121 122 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 123 ((3 & 0xf) << 28) | index); 124 125 /* 126 * Send an invalid index as a vote for the bus bandwidth and let the 127 * firmware decide on the right vote 128 */ 129 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 130 131 /* Set and clear the OOB for DCVS to trigger the GMU */ 132 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 133 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 134 135 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 136 if (ret) 137 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 138 139 /* 140 * Eventually we will want to scale the path vote with the frequency but 141 * for now leave it at max so that the performance is nominal. 142 */ 143 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 144 pm_runtime_put(gmu->dev); 145 } 146 147 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 148 { 149 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 150 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 151 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 152 u32 perf_index = 0; 153 154 if (freq == gmu->freq) 155 return; 156 157 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 158 if (freq == gmu->gpu_freqs[perf_index]) 159 break; 160 161 gmu->current_perf_index = perf_index; 162 163 if (gmu->legacy) 164 __a6xx_gmu_set_freq(gmu, perf_index); 165 else 166 a6xx_hfi_set_freq(gmu, perf_index); 167 168 gmu->freq = gmu->gpu_freqs[perf_index]; 169 } 170 171 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 172 { 173 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 174 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 175 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 176 177 return gmu->freq; 178 } 179 180 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 181 { 182 u32 val; 183 int local = gmu->idle_level; 184 185 /* SPTP and IFPC both report as IFPC */ 186 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 187 local = GMU_IDLE_STATE_IFPC; 188 189 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 190 191 if (val == local) { 192 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 193 !a6xx_gmu_gx_is_on(gmu)) 194 return true; 195 } 196 197 return false; 198 } 199 200 /* Wait for the GMU to get to its most idle state */ 201 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 202 { 203 return spin_until(a6xx_gmu_check_idle_level(gmu)); 204 } 205 206 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 207 { 208 int ret; 209 u32 val; 210 211 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 212 213 /* Set the log wptr index 214 * note: downstream saves the value in poweroff and restores it here 215 */ 216 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 217 218 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 219 220 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 221 val == 0xbabeface, 100, 10000); 222 223 if (ret) 224 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 225 226 return ret; 227 } 228 229 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 230 { 231 u32 val; 232 int ret; 233 234 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 235 236 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 237 val & 1, 100, 10000); 238 if (ret) 239 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 240 241 return ret; 242 } 243 244 /* Trigger a OOB (out of band) request to the GMU */ 245 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 246 { 247 int ret; 248 u32 val; 249 int request, ack; 250 const char *name; 251 252 switch (state) { 253 case GMU_OOB_GPU_SET: 254 if (gmu->legacy) { 255 request = GMU_OOB_GPU_SET_REQUEST; 256 ack = GMU_OOB_GPU_SET_ACK; 257 } else { 258 request = GMU_OOB_GPU_SET_REQUEST_NEW; 259 ack = GMU_OOB_GPU_SET_ACK_NEW; 260 } 261 name = "GPU_SET"; 262 break; 263 case GMU_OOB_BOOT_SLUMBER: 264 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 265 ack = GMU_OOB_BOOT_SLUMBER_ACK; 266 name = "BOOT_SLUMBER"; 267 break; 268 case GMU_OOB_DCVS_SET: 269 request = GMU_OOB_DCVS_REQUEST; 270 ack = GMU_OOB_DCVS_ACK; 271 name = "GPU_DCVS"; 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 /* Trigger the equested OOB operation */ 278 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 279 280 /* Wait for the acknowledge interrupt */ 281 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 282 val & (1 << ack), 100, 10000); 283 284 if (ret) 285 DRM_DEV_ERROR(gmu->dev, 286 "Timeout waiting for GMU OOB set %s: 0x%x\n", 287 name, 288 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 289 290 /* Clear the acknowledge interrupt */ 291 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 292 293 return ret; 294 } 295 296 /* Clear a pending OOB state in the GMU */ 297 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 298 { 299 if (!gmu->legacy) { 300 WARN_ON(state != GMU_OOB_GPU_SET); 301 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 302 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 303 return; 304 } 305 306 switch (state) { 307 case GMU_OOB_GPU_SET: 308 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 309 1 << GMU_OOB_GPU_SET_CLEAR); 310 break; 311 case GMU_OOB_BOOT_SLUMBER: 312 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 313 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 314 break; 315 case GMU_OOB_DCVS_SET: 316 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 317 1 << GMU_OOB_DCVS_CLEAR); 318 break; 319 } 320 } 321 322 /* Enable CPU control of SPTP power power collapse */ 323 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 324 { 325 int ret; 326 u32 val; 327 328 if (!gmu->legacy) 329 return 0; 330 331 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 332 333 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 334 (val & 0x38) == 0x28, 1, 100); 335 336 if (ret) { 337 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 338 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 339 } 340 341 return 0; 342 } 343 344 /* Disable CPU control of SPTP power power collapse */ 345 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 346 { 347 u32 val; 348 int ret; 349 350 if (!gmu->legacy) 351 return; 352 353 /* Make sure retention is on */ 354 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 355 356 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 357 358 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 359 (val & 0x04), 100, 10000); 360 361 if (ret) 362 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 363 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 364 } 365 366 /* Let the GMU know we are starting a boot sequence */ 367 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 368 { 369 u32 vote; 370 371 /* Let the GMU know we are getting ready for boot */ 372 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 373 374 /* Choose the "default" power level as the highest available */ 375 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 376 377 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 378 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 379 380 /* Let the GMU know the boot sequence has started */ 381 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 382 } 383 384 /* Let the GMU know that we are about to go into slumber */ 385 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 386 { 387 int ret; 388 389 /* Disable the power counter so the GMU isn't busy */ 390 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 391 392 /* Disable SPTP_PC if the CPU is responsible for it */ 393 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 394 a6xx_sptprac_disable(gmu); 395 396 if (!gmu->legacy) { 397 ret = a6xx_hfi_send_prep_slumber(gmu); 398 goto out; 399 } 400 401 /* Tell the GMU to get ready to slumber */ 402 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 403 404 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 405 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 406 407 if (!ret) { 408 /* Check to see if the GMU really did slumber */ 409 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 410 != 0x0f) { 411 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 412 ret = -ETIMEDOUT; 413 } 414 } 415 416 out: 417 /* Put fence into allow mode */ 418 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 419 return ret; 420 } 421 422 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 423 { 424 int ret; 425 u32 val; 426 427 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 428 /* Wait for the register to finish posting */ 429 wmb(); 430 431 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 432 val & (1 << 1), 100, 10000); 433 if (ret) { 434 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 435 return ret; 436 } 437 438 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 439 !val, 100, 10000); 440 441 if (ret) { 442 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 443 return ret; 444 } 445 446 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 447 448 /* Set up CX GMU counter 0 to count busy ticks */ 449 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 450 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 451 452 /* Enable the power counter */ 453 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 454 return 0; 455 } 456 457 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 458 { 459 int ret; 460 u32 val; 461 462 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 463 464 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 465 val, val & (1 << 16), 100, 10000); 466 if (ret) 467 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 468 469 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 470 } 471 472 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 473 { 474 return msm_writel(value, ptr + (offset << 2)); 475 } 476 477 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 478 const char *name); 479 480 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 481 { 482 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 483 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 484 struct platform_device *pdev = to_platform_device(gmu->dev); 485 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 486 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 487 uint32_t pdc_address_offset; 488 489 if (!pdcptr || !seqptr) 490 goto err; 491 492 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) 493 pdc_address_offset = 0x30090; 494 else if (adreno_is_a650(adreno_gpu)) 495 pdc_address_offset = 0x300a0; 496 else 497 pdc_address_offset = 0x30080; 498 499 /* Disable SDE clock gating */ 500 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 501 502 /* Setup RSC PDC handshake for sleep and wakeup */ 503 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 504 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 505 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 506 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 507 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 508 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 509 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 510 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 511 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 512 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 513 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 514 515 /* Load RSC sequencer uCode for sleep and wakeup */ 516 if (adreno_is_a650(adreno_gpu)) { 517 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); 518 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); 519 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); 520 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); 521 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); 522 } else { 523 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 524 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 525 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 526 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 527 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 528 } 529 530 /* Load PDC sequencer uCode for power up and power down sequence */ 531 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 532 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 533 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 534 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 535 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 536 537 /* Set TCS commands used by PDC sequence for low power modes */ 538 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 539 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 540 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 541 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 542 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 544 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 546 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 547 548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 549 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 551 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 554 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 555 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 558 559 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 560 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 561 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) 562 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 563 else 564 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 565 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 566 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 567 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 568 569 /* Setup GPU PDC */ 570 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 571 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 572 573 /* ensure no writes happen before the uCode is fully written */ 574 wmb(); 575 576 err: 577 if (!IS_ERR_OR_NULL(pdcptr)) 578 iounmap(pdcptr); 579 if (!IS_ERR_OR_NULL(seqptr)) 580 iounmap(seqptr); 581 } 582 583 /* 584 * The lowest 16 bits of this value are the number of XO clock cycles for main 585 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 586 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 587 */ 588 589 #define GMU_PWR_COL_HYST 0x000a1680 590 591 /* Set up the idle state for the GMU */ 592 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 593 { 594 /* Disable GMU WB/RB buffer */ 595 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 596 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 597 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 598 599 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 600 601 switch (gmu->idle_level) { 602 case GMU_IDLE_STATE_IFPC: 603 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 604 GMU_PWR_COL_HYST); 605 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 606 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 607 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 608 /* Fall through */ 609 case GMU_IDLE_STATE_SPTP: 610 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 611 GMU_PWR_COL_HYST); 612 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 613 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 614 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 615 } 616 617 /* Enable RPMh GPU client */ 618 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 619 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 620 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 621 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 622 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 623 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 624 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 625 } 626 627 struct block_header { 628 u32 addr; 629 u32 size; 630 u32 type; 631 u32 value; 632 u32 data[]; 633 }; 634 635 /* this should be a general kernel helper */ 636 static int in_range(u32 addr, u32 start, u32 size) 637 { 638 return addr >= start && addr < start + size; 639 } 640 641 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 642 { 643 if (!in_range(blk->addr, bo->iova, bo->size)) 644 return false; 645 646 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 647 return true; 648 } 649 650 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 651 { 652 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 653 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 654 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 655 const struct block_header *blk; 656 u32 reg_offset; 657 658 u32 itcm_base = 0x00000000; 659 u32 dtcm_base = 0x00040000; 660 661 if (adreno_is_a650(adreno_gpu)) 662 dtcm_base = 0x10004000; 663 664 if (gmu->legacy) { 665 /* Sanity check the size of the firmware that was loaded */ 666 if (fw_image->size > 0x8000) { 667 DRM_DEV_ERROR(gmu->dev, 668 "GMU firmware is bigger than the available region\n"); 669 return -EINVAL; 670 } 671 672 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 673 (u32*) fw_image->data, fw_image->size); 674 return 0; 675 } 676 677 678 for (blk = (const struct block_header *) fw_image->data; 679 (const u8*) blk < fw_image->data + fw_image->size; 680 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 681 if (blk->size == 0) 682 continue; 683 684 if (in_range(blk->addr, itcm_base, SZ_16K)) { 685 reg_offset = (blk->addr - itcm_base) >> 2; 686 gmu_write_bulk(gmu, 687 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 688 blk->data, blk->size); 689 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 690 reg_offset = (blk->addr - dtcm_base) >> 2; 691 gmu_write_bulk(gmu, 692 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 693 blk->data, blk->size); 694 } else if (!fw_block_mem(&gmu->icache, blk) && 695 !fw_block_mem(&gmu->dcache, blk) && 696 !fw_block_mem(&gmu->dummy, blk)) { 697 DRM_DEV_ERROR(gmu->dev, 698 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 699 blk->addr, blk->size, blk->data[0]); 700 } 701 } 702 703 return 0; 704 } 705 706 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 707 { 708 static bool rpmh_init; 709 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 710 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 711 int ret; 712 u32 chipid; 713 714 if (adreno_is_a650(adreno_gpu)) 715 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 716 717 if (state == GMU_WARM_BOOT) { 718 ret = a6xx_rpmh_start(gmu); 719 if (ret) 720 return ret; 721 } else { 722 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 723 "GMU firmware is not loaded\n")) 724 return -ENOENT; 725 726 /* Turn on register retention */ 727 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 728 729 /* We only need to load the RPMh microcode once */ 730 if (!rpmh_init) { 731 a6xx_gmu_rpmh_init(gmu); 732 rpmh_init = true; 733 } else { 734 ret = a6xx_rpmh_start(gmu); 735 if (ret) 736 return ret; 737 } 738 739 ret = a6xx_gmu_fw_load(gmu); 740 if (ret) 741 return ret; 742 } 743 744 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 745 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 746 747 /* Write the iova of the HFI table */ 748 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 749 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 750 751 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 752 (1 << 31) | (0xa << 18) | (0xa0)); 753 754 chipid = adreno_gpu->rev.core << 24; 755 chipid |= adreno_gpu->rev.major << 16; 756 chipid |= adreno_gpu->rev.minor << 12; 757 chipid |= adreno_gpu->rev.patchid << 8; 758 759 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 760 761 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 762 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 763 764 /* Set up the lowest idle level on the GMU */ 765 a6xx_gmu_power_config(gmu); 766 767 ret = a6xx_gmu_start(gmu); 768 if (ret) 769 return ret; 770 771 if (gmu->legacy) { 772 ret = a6xx_gmu_gfx_rail_on(gmu); 773 if (ret) 774 return ret; 775 } 776 777 /* Enable SPTP_PC if the CPU is responsible for it */ 778 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 779 ret = a6xx_sptprac_enable(gmu); 780 if (ret) 781 return ret; 782 } 783 784 ret = a6xx_gmu_hfi_start(gmu); 785 if (ret) 786 return ret; 787 788 /* FIXME: Do we need this wmb() here? */ 789 wmb(); 790 791 return 0; 792 } 793 794 #define A6XX_HFI_IRQ_MASK \ 795 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 796 797 #define A6XX_GMU_IRQ_MASK \ 798 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 799 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 800 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 801 802 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 803 { 804 disable_irq(gmu->gmu_irq); 805 disable_irq(gmu->hfi_irq); 806 807 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 808 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 809 } 810 811 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 812 { 813 u32 val; 814 815 /* Make sure there are no outstanding RPMh votes */ 816 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 817 (val & 1), 100, 10000); 818 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 819 (val & 1), 100, 10000); 820 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 821 (val & 1), 100, 10000); 822 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 823 (val & 1), 100, 1000); 824 } 825 826 /* Force the GMU off in case it isn't responsive */ 827 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 828 { 829 /* Flush all the queues */ 830 a6xx_hfi_stop(gmu); 831 832 /* Stop the interrupts */ 833 a6xx_gmu_irq_disable(gmu); 834 835 /* Force off SPTP in case the GMU is managing it */ 836 a6xx_sptprac_disable(gmu); 837 838 /* Make sure there are no outstanding RPMh votes */ 839 a6xx_gmu_rpmh_off(gmu); 840 } 841 842 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 843 { 844 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 845 struct msm_gpu *gpu = &adreno_gpu->base; 846 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 847 int status, ret; 848 849 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 850 return 0; 851 852 gmu->hung = false; 853 854 /* Turn on the resources */ 855 pm_runtime_get_sync(gmu->dev); 856 857 /* Use a known rate to bring up the GMU */ 858 clk_set_rate(gmu->core_clk, 200000000); 859 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 860 if (ret) { 861 pm_runtime_put(gmu->dev); 862 return ret; 863 } 864 865 /* Set the bus quota to a reasonable value for boot */ 866 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 867 868 /* Enable the GMU interrupt */ 869 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 870 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 871 enable_irq(gmu->gmu_irq); 872 873 /* Check to see if we are doing a cold or warm boot */ 874 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 875 GMU_WARM_BOOT : GMU_COLD_BOOT; 876 877 /* 878 * Warm boot path does not work on newer GPUs 879 * Presumably this is because icache/dcache regions must be restored 880 */ 881 if (!gmu->legacy) 882 status = GMU_COLD_BOOT; 883 884 ret = a6xx_gmu_fw_start(gmu, status); 885 if (ret) 886 goto out; 887 888 ret = a6xx_hfi_start(gmu, status); 889 if (ret) 890 goto out; 891 892 /* 893 * Turn on the GMU firmware fault interrupt after we know the boot 894 * sequence is successful 895 */ 896 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 897 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 898 enable_irq(gmu->hfi_irq); 899 900 /* Set the GPU to the current freq */ 901 if (gmu->legacy) 902 __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); 903 else 904 a6xx_hfi_set_freq(gmu, gmu->current_perf_index); 905 906 /* 907 * "enable" the GX power domain which won't actually do anything but it 908 * will make sure that the refcounting is correct in case we need to 909 * bring down the GX after a GMU failure 910 */ 911 if (!IS_ERR_OR_NULL(gmu->gxpd)) 912 pm_runtime_get(gmu->gxpd); 913 914 out: 915 /* On failure, shut down the GMU to leave it in a good state */ 916 if (ret) { 917 disable_irq(gmu->gmu_irq); 918 a6xx_rpmh_stop(gmu); 919 pm_runtime_put(gmu->dev); 920 } 921 922 return ret; 923 } 924 925 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 926 { 927 u32 reg; 928 929 if (!gmu->initialized) 930 return true; 931 932 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 933 934 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 935 return false; 936 937 return true; 938 } 939 940 #define GBIF_CLIENT_HALT_MASK BIT(0) 941 #define GBIF_ARB_HALT_MASK BIT(1) 942 943 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 944 { 945 struct msm_gpu *gpu = &adreno_gpu->base; 946 947 if (!a6xx_has_gbif(adreno_gpu)) { 948 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 949 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 950 0xf) == 0xf); 951 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 952 953 return; 954 } 955 956 /* Halt new client requests on GBIF */ 957 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 958 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 959 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 960 961 /* Halt all AXI requests on GBIF */ 962 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 963 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 964 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 965 966 /* The GBIF halt needs to be explicitly cleared */ 967 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 968 } 969 970 /* Gracefully try to shut down the GMU and by extension the GPU */ 971 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 972 { 973 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 974 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 975 u32 val; 976 977 /* 978 * The GMU may still be in slumber unless the GPU started so check and 979 * skip putting it back into slumber if so 980 */ 981 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 982 983 if (val != 0xf) { 984 int ret = a6xx_gmu_wait_for_idle(gmu); 985 986 /* If the GMU isn't responding assume it is hung */ 987 if (ret) { 988 a6xx_gmu_force_off(gmu); 989 return; 990 } 991 992 a6xx_bus_clear_pending_transactions(adreno_gpu); 993 994 /* tell the GMU we want to slumber */ 995 a6xx_gmu_notify_slumber(gmu); 996 997 ret = gmu_poll_timeout(gmu, 998 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 999 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1000 100, 10000); 1001 1002 /* 1003 * Let the user know we failed to slumber but don't worry too 1004 * much because we are powering down anyway 1005 */ 1006 1007 if (ret) 1008 DRM_DEV_ERROR(gmu->dev, 1009 "Unable to slumber GMU: status = 0%x/0%x\n", 1010 gmu_read(gmu, 1011 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1012 gmu_read(gmu, 1013 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1014 } 1015 1016 /* Turn off HFI */ 1017 a6xx_hfi_stop(gmu); 1018 1019 /* Stop the interrupts and mask the hardware */ 1020 a6xx_gmu_irq_disable(gmu); 1021 1022 /* Tell RPMh to power off the GPU */ 1023 a6xx_rpmh_stop(gmu); 1024 } 1025 1026 1027 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1028 { 1029 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1030 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1031 1032 if (!pm_runtime_active(gmu->dev)) 1033 return 0; 1034 1035 /* 1036 * Force the GMU off if we detected a hang, otherwise try to shut it 1037 * down gracefully 1038 */ 1039 if (gmu->hung) 1040 a6xx_gmu_force_off(gmu); 1041 else 1042 a6xx_gmu_shutdown(gmu); 1043 1044 /* Remove the bus vote */ 1045 icc_set_bw(gpu->icc_path, 0, 0); 1046 1047 /* 1048 * Make sure the GX domain is off before turning off the GMU (CX) 1049 * domain. Usually the GMU does this but only if the shutdown sequence 1050 * was successful 1051 */ 1052 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1053 pm_runtime_put_sync(gmu->gxpd); 1054 1055 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1056 1057 pm_runtime_put_sync(gmu->dev); 1058 1059 return 0; 1060 } 1061 1062 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1063 { 1064 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 1065 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 1066 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false); 1067 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false); 1068 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false); 1069 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false); 1070 1071 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1072 msm_gem_address_space_put(gmu->aspace); 1073 } 1074 1075 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1076 size_t size, u64 iova) 1077 { 1078 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1079 struct drm_device *dev = a6xx_gpu->base.base.dev; 1080 uint32_t flags = MSM_BO_WC; 1081 u64 range_start, range_end; 1082 int ret; 1083 1084 size = PAGE_ALIGN(size); 1085 if (!iova) { 1086 /* no fixed address - use GMU's uncached range */ 1087 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1088 range_end = 0x80000000; 1089 } else { 1090 /* range for fixed address */ 1091 range_start = iova; 1092 range_end = iova + size; 1093 /* use IOMMU_PRIV for icache/dcache */ 1094 flags |= MSM_BO_MAP_PRIV; 1095 } 1096 1097 bo->obj = msm_gem_new(dev, size, flags); 1098 if (IS_ERR(bo->obj)) 1099 return PTR_ERR(bo->obj); 1100 1101 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1102 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 1103 if (ret) { 1104 drm_gem_object_put(bo->obj); 1105 return ret; 1106 } 1107 1108 bo->virt = msm_gem_get_vaddr(bo->obj); 1109 bo->size = size; 1110 1111 return 0; 1112 } 1113 1114 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1115 { 1116 struct iommu_domain *domain; 1117 int ret; 1118 1119 domain = iommu_domain_alloc(&platform_bus_type); 1120 if (!domain) 1121 return -ENODEV; 1122 1123 domain->geometry.aperture_start = 0x00000000; 1124 domain->geometry.aperture_end = 0x7fffffff; 1125 1126 gmu->aspace = msm_gem_address_space_create(gmu->dev, domain, "gmu"); 1127 if (IS_ERR(gmu->aspace)) { 1128 iommu_domain_free(domain); 1129 return PTR_ERR(gmu->aspace); 1130 } 1131 1132 ret = gmu->aspace->mmu->funcs->attach(gmu->aspace->mmu); 1133 if (ret) { 1134 msm_gem_address_space_put(gmu->aspace); 1135 return ret; 1136 } 1137 1138 return 0; 1139 } 1140 1141 /* Return the 'arc-level' for the given frequency */ 1142 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1143 unsigned long freq) 1144 { 1145 struct dev_pm_opp *opp; 1146 unsigned int val; 1147 1148 if (!freq) 1149 return 0; 1150 1151 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1152 if (IS_ERR(opp)) 1153 return 0; 1154 1155 val = dev_pm_opp_get_level(opp); 1156 1157 dev_pm_opp_put(opp); 1158 1159 return val; 1160 } 1161 1162 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1163 unsigned long *freqs, int freqs_count, const char *id) 1164 { 1165 int i, j; 1166 const u16 *pri, *sec; 1167 size_t pri_count, sec_count; 1168 1169 pri = cmd_db_read_aux_data(id, &pri_count); 1170 if (IS_ERR(pri)) 1171 return PTR_ERR(pri); 1172 /* 1173 * The data comes back as an array of unsigned shorts so adjust the 1174 * count accordingly 1175 */ 1176 pri_count >>= 1; 1177 if (!pri_count) 1178 return -EINVAL; 1179 1180 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1181 if (IS_ERR(sec)) 1182 return PTR_ERR(sec); 1183 1184 sec_count >>= 1; 1185 if (!sec_count) 1186 return -EINVAL; 1187 1188 /* Construct a vote for each frequency */ 1189 for (i = 0; i < freqs_count; i++) { 1190 u8 pindex = 0, sindex = 0; 1191 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1192 1193 /* Get the primary index that matches the arc level */ 1194 for (j = 0; j < pri_count; j++) { 1195 if (pri[j] >= level) { 1196 pindex = j; 1197 break; 1198 } 1199 } 1200 1201 if (j == pri_count) { 1202 DRM_DEV_ERROR(dev, 1203 "Level %u not found in the RPMh list\n", 1204 level); 1205 DRM_DEV_ERROR(dev, "Available levels:\n"); 1206 for (j = 0; j < pri_count; j++) 1207 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1208 1209 return -EINVAL; 1210 } 1211 1212 /* 1213 * Look for a level in in the secondary list that matches. If 1214 * nothing fits, use the maximum non zero vote 1215 */ 1216 1217 for (j = 0; j < sec_count; j++) { 1218 if (sec[j] >= level) { 1219 sindex = j; 1220 break; 1221 } else if (sec[j]) { 1222 sindex = j; 1223 } 1224 } 1225 1226 /* Construct the vote */ 1227 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1228 (sindex << 8) | pindex; 1229 } 1230 1231 return 0; 1232 } 1233 1234 /* 1235 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1236 * to construct the list of votes on the CPU and send it over. Query the RPMh 1237 * voltage levels and build the votes 1238 */ 1239 1240 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1241 { 1242 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1243 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1244 struct msm_gpu *gpu = &adreno_gpu->base; 1245 int ret; 1246 1247 /* Build the GX votes */ 1248 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1249 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1250 1251 /* Build the CX votes */ 1252 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1253 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1254 1255 return ret; 1256 } 1257 1258 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1259 u32 size) 1260 { 1261 int count = dev_pm_opp_get_opp_count(dev); 1262 struct dev_pm_opp *opp; 1263 int i, index = 0; 1264 unsigned long freq = 1; 1265 1266 /* 1267 * The OPP table doesn't contain the "off" frequency level so we need to 1268 * add 1 to the table size to account for it 1269 */ 1270 1271 if (WARN(count + 1 > size, 1272 "The GMU frequency table is being truncated\n")) 1273 count = size - 1; 1274 1275 /* Set the "off" frequency */ 1276 freqs[index++] = 0; 1277 1278 for (i = 0; i < count; i++) { 1279 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1280 if (IS_ERR(opp)) 1281 break; 1282 1283 dev_pm_opp_put(opp); 1284 freqs[index++] = freq++; 1285 } 1286 1287 return index; 1288 } 1289 1290 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1291 { 1292 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1293 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1294 struct msm_gpu *gpu = &adreno_gpu->base; 1295 1296 int ret = 0; 1297 1298 /* 1299 * The GMU handles its own frequency switching so build a list of 1300 * available frequencies to send during initialization 1301 */ 1302 ret = dev_pm_opp_of_add_table(gmu->dev); 1303 if (ret) { 1304 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1305 return ret; 1306 } 1307 1308 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1309 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1310 1311 /* 1312 * The GMU also handles GPU frequency switching so build a list 1313 * from the GPU OPP table 1314 */ 1315 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1316 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1317 1318 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1319 1320 /* Build the list of RPMh votes that we'll send to the GMU */ 1321 return a6xx_gmu_rpmh_votes_init(gmu); 1322 } 1323 1324 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1325 { 1326 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1327 1328 if (ret < 1) 1329 return ret; 1330 1331 gmu->nr_clocks = ret; 1332 1333 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1334 gmu->nr_clocks, "gmu"); 1335 1336 return 0; 1337 } 1338 1339 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1340 const char *name) 1341 { 1342 void __iomem *ret; 1343 struct resource *res = platform_get_resource_byname(pdev, 1344 IORESOURCE_MEM, name); 1345 1346 if (!res) { 1347 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1348 return ERR_PTR(-EINVAL); 1349 } 1350 1351 ret = ioremap(res->start, resource_size(res)); 1352 if (!ret) { 1353 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1354 return ERR_PTR(-EINVAL); 1355 } 1356 1357 return ret; 1358 } 1359 1360 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1361 const char *name, irq_handler_t handler) 1362 { 1363 int irq, ret; 1364 1365 irq = platform_get_irq_byname(pdev, name); 1366 1367 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1368 if (ret) { 1369 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1370 name, ret); 1371 return ret; 1372 } 1373 1374 disable_irq(irq); 1375 1376 return irq; 1377 } 1378 1379 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1380 { 1381 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1382 struct platform_device *pdev = to_platform_device(gmu->dev); 1383 1384 if (!gmu->initialized) 1385 return; 1386 1387 pm_runtime_force_suspend(gmu->dev); 1388 1389 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1390 pm_runtime_disable(gmu->gxpd); 1391 dev_pm_domain_detach(gmu->gxpd, false); 1392 } 1393 1394 iounmap(gmu->mmio); 1395 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1396 iounmap(gmu->rscc); 1397 gmu->mmio = NULL; 1398 gmu->rscc = NULL; 1399 1400 a6xx_gmu_memory_free(gmu); 1401 1402 free_irq(gmu->gmu_irq, gmu); 1403 free_irq(gmu->hfi_irq, gmu); 1404 1405 /* Drop reference taken in of_find_device_by_node */ 1406 put_device(gmu->dev); 1407 1408 gmu->initialized = false; 1409 } 1410 1411 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1412 { 1413 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1414 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1415 struct platform_device *pdev = of_find_device_by_node(node); 1416 int ret; 1417 1418 if (!pdev) 1419 return -ENODEV; 1420 1421 gmu->dev = &pdev->dev; 1422 1423 of_dma_configure(gmu->dev, node, true); 1424 1425 /* Fow now, don't do anything fancy until we get our feet under us */ 1426 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1427 1428 pm_runtime_enable(gmu->dev); 1429 1430 /* Get the list of clocks */ 1431 ret = a6xx_gmu_clocks_probe(gmu); 1432 if (ret) 1433 goto err_put_device; 1434 1435 ret = a6xx_gmu_memory_probe(gmu); 1436 if (ret) 1437 goto err_put_device; 1438 1439 /* Allocate memory for the GMU dummy page */ 1440 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); 1441 if (ret) 1442 goto err_memory; 1443 1444 if (adreno_is_a650(adreno_gpu)) { 1445 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1446 SZ_16M - SZ_16K, 0x04000); 1447 if (ret) 1448 goto err_memory; 1449 } else if (adreno_is_a640(adreno_gpu)) { 1450 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1451 SZ_256K - SZ_16K, 0x04000); 1452 if (ret) 1453 goto err_memory; 1454 1455 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1456 SZ_256K - SZ_16K, 0x44000); 1457 if (ret) 1458 goto err_memory; 1459 } else { 1460 /* HFI v1, has sptprac */ 1461 gmu->legacy = true; 1462 1463 /* Allocate memory for the GMU debug region */ 1464 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1465 if (ret) 1466 goto err_memory; 1467 } 1468 1469 /* Allocate memory for for the HFI queues */ 1470 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1471 if (ret) 1472 goto err_memory; 1473 1474 /* Allocate memory for the GMU log region */ 1475 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0); 1476 if (ret) 1477 goto err_memory; 1478 1479 /* Map the GMU registers */ 1480 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1481 if (IS_ERR(gmu->mmio)) { 1482 ret = PTR_ERR(gmu->mmio); 1483 goto err_memory; 1484 } 1485 1486 if (adreno_is_a650(adreno_gpu)) { 1487 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1488 if (IS_ERR(gmu->rscc)) 1489 goto err_mmio; 1490 } else { 1491 gmu->rscc = gmu->mmio + 0x23000; 1492 } 1493 1494 /* Get the HFI and GMU interrupts */ 1495 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1496 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1497 1498 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1499 goto err_mmio; 1500 1501 /* 1502 * Get a link to the GX power domain to reset the GPU in case of GMU 1503 * crash 1504 */ 1505 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1506 1507 /* Get the power levels for the GMU and GPU */ 1508 a6xx_gmu_pwrlevels_probe(gmu); 1509 1510 /* Set up the HFI queues */ 1511 a6xx_hfi_init(gmu); 1512 1513 gmu->initialized = true; 1514 1515 return 0; 1516 1517 err_mmio: 1518 iounmap(gmu->mmio); 1519 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1520 iounmap(gmu->rscc); 1521 free_irq(gmu->gmu_irq, gmu); 1522 free_irq(gmu->hfi_irq, gmu); 1523 1524 ret = -ENODEV; 1525 1526 err_memory: 1527 a6xx_gmu_memory_free(gmu); 1528 err_put_device: 1529 /* Drop reference taken in of_find_device_by_node */ 1530 put_device(gmu->dev); 1531 1532 return ret; 1533 } 1534