1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 10 #include "a6xx_gpu.h" 11 #include "a6xx_gmu.xml.h" 12 13 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 14 { 15 struct a6xx_gmu *gmu = data; 16 u32 status; 17 18 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 19 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 20 21 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 22 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 23 24 /* Temporary until we can recover safely */ 25 BUG(); 26 } 27 28 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 29 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 30 31 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 32 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 33 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 34 35 return IRQ_HANDLED; 36 } 37 38 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 39 { 40 struct a6xx_gmu *gmu = data; 41 u32 status; 42 43 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 44 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 45 46 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 47 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 48 49 /* Temporary until we can recover safely */ 50 BUG(); 51 } 52 53 return IRQ_HANDLED; 54 } 55 56 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 57 { 58 u32 val; 59 60 /* This can be called from gpu state code so make sure GMU is valid */ 61 if (IS_ERR_OR_NULL(gmu->mmio)) 62 return false; 63 64 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 65 66 return !(val & 67 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 68 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 69 } 70 71 /* Check to see if the GX rail is still powered */ 72 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 73 { 74 u32 val; 75 76 /* This can be called from gpu state code so make sure GMU is valid */ 77 if (IS_ERR_OR_NULL(gmu->mmio)) 78 return false; 79 80 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 81 82 return !(val & 83 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 84 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 85 } 86 87 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 88 { 89 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 90 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 91 struct msm_gpu *gpu = &adreno_gpu->base; 92 int ret; 93 94 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 95 96 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 97 ((3 & 0xf) << 28) | index); 98 99 /* 100 * Send an invalid index as a vote for the bus bandwidth and let the 101 * firmware decide on the right vote 102 */ 103 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 104 105 /* Set and clear the OOB for DCVS to trigger the GMU */ 106 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 107 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 108 109 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 110 if (ret) 111 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 112 113 gmu->freq = gmu->gpu_freqs[index]; 114 115 /* 116 * Eventually we will want to scale the path vote with the frequency but 117 * for now leave it at max so that the performance is nominal. 118 */ 119 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 120 } 121 122 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 123 { 124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 125 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 126 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 127 u32 perf_index = 0; 128 129 if (freq == gmu->freq) 130 return; 131 132 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 133 if (freq == gmu->gpu_freqs[perf_index]) 134 break; 135 136 __a6xx_gmu_set_freq(gmu, perf_index); 137 } 138 139 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 140 { 141 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 142 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 143 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 144 145 return gmu->freq; 146 } 147 148 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 149 { 150 u32 val; 151 int local = gmu->idle_level; 152 153 /* SPTP and IFPC both report as IFPC */ 154 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 155 local = GMU_IDLE_STATE_IFPC; 156 157 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 158 159 if (val == local) { 160 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 161 !a6xx_gmu_gx_is_on(gmu)) 162 return true; 163 } 164 165 return false; 166 } 167 168 /* Wait for the GMU to get to its most idle state */ 169 int a6xx_gmu_wait_for_idle(struct a6xx_gpu *a6xx_gpu) 170 { 171 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 172 173 return spin_until(a6xx_gmu_check_idle_level(gmu)); 174 } 175 176 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 177 { 178 int ret; 179 u32 val; 180 181 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 182 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 183 184 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 185 val == 0xbabeface, 100, 10000); 186 187 if (ret) 188 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 189 190 return ret; 191 } 192 193 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 194 { 195 u32 val; 196 int ret; 197 198 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 199 200 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 201 val & 1, 100, 10000); 202 if (ret) 203 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 204 205 return ret; 206 } 207 208 /* Trigger a OOB (out of band) request to the GMU */ 209 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 210 { 211 int ret; 212 u32 val; 213 int request, ack; 214 const char *name; 215 216 switch (state) { 217 case GMU_OOB_GPU_SET: 218 request = GMU_OOB_GPU_SET_REQUEST; 219 ack = GMU_OOB_GPU_SET_ACK; 220 name = "GPU_SET"; 221 break; 222 case GMU_OOB_BOOT_SLUMBER: 223 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 224 ack = GMU_OOB_BOOT_SLUMBER_ACK; 225 name = "BOOT_SLUMBER"; 226 break; 227 case GMU_OOB_DCVS_SET: 228 request = GMU_OOB_DCVS_REQUEST; 229 ack = GMU_OOB_DCVS_ACK; 230 name = "GPU_DCVS"; 231 break; 232 default: 233 return -EINVAL; 234 } 235 236 /* Trigger the equested OOB operation */ 237 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 238 239 /* Wait for the acknowledge interrupt */ 240 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 241 val & (1 << ack), 100, 10000); 242 243 if (ret) 244 DRM_DEV_ERROR(gmu->dev, 245 "Timeout waiting for GMU OOB set %s: 0x%x\n", 246 name, 247 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 248 249 /* Clear the acknowledge interrupt */ 250 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 251 252 return ret; 253 } 254 255 /* Clear a pending OOB state in the GMU */ 256 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 257 { 258 switch (state) { 259 case GMU_OOB_GPU_SET: 260 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 261 1 << GMU_OOB_GPU_SET_CLEAR); 262 break; 263 case GMU_OOB_BOOT_SLUMBER: 264 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 265 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 266 break; 267 case GMU_OOB_DCVS_SET: 268 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 269 1 << GMU_OOB_DCVS_CLEAR); 270 break; 271 } 272 } 273 274 /* Enable CPU control of SPTP power power collapse */ 275 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 276 { 277 int ret; 278 u32 val; 279 280 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 281 282 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 283 (val & 0x38) == 0x28, 1, 100); 284 285 if (ret) { 286 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 287 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 288 } 289 290 return 0; 291 } 292 293 /* Disable CPU control of SPTP power power collapse */ 294 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 295 { 296 u32 val; 297 int ret; 298 299 /* Make sure retention is on */ 300 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 301 302 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 303 304 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 305 (val & 0x04), 100, 10000); 306 307 if (ret) 308 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 309 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 310 } 311 312 /* Let the GMU know we are starting a boot sequence */ 313 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 314 { 315 u32 vote; 316 317 /* Let the GMU know we are getting ready for boot */ 318 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 319 320 /* Choose the "default" power level as the highest available */ 321 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 322 323 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 324 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 325 326 /* Let the GMU know the boot sequence has started */ 327 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 328 } 329 330 /* Let the GMU know that we are about to go into slumber */ 331 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 332 { 333 int ret; 334 335 /* Disable the power counter so the GMU isn't busy */ 336 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 337 338 /* Disable SPTP_PC if the CPU is responsible for it */ 339 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 340 a6xx_sptprac_disable(gmu); 341 342 /* Tell the GMU to get ready to slumber */ 343 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 344 345 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 346 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 347 348 if (!ret) { 349 /* Check to see if the GMU really did slumber */ 350 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 351 != 0x0f) { 352 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 353 ret = -ETIMEDOUT; 354 } 355 } 356 357 /* Put fence into allow mode */ 358 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 359 return ret; 360 } 361 362 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 363 { 364 int ret; 365 u32 val; 366 367 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 368 /* Wait for the register to finish posting */ 369 wmb(); 370 371 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 372 val & (1 << 1), 100, 10000); 373 if (ret) { 374 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 375 return ret; 376 } 377 378 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 379 !val, 100, 10000); 380 381 if (ret) { 382 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 383 return ret; 384 } 385 386 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 387 388 /* Set up CX GMU counter 0 to count busy ticks */ 389 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 390 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 391 392 /* Enable the power counter */ 393 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 394 return 0; 395 } 396 397 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 398 { 399 int ret; 400 u32 val; 401 402 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 403 404 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 405 val, val & (1 << 16), 100, 10000); 406 if (ret) 407 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 408 409 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 410 } 411 412 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 413 { 414 return msm_writel(value, ptr + (offset << 2)); 415 } 416 417 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 418 const char *name); 419 420 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 421 { 422 struct platform_device *pdev = to_platform_device(gmu->dev); 423 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 424 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 425 426 if (!pdcptr || !seqptr) 427 goto err; 428 429 /* Disable SDE clock gating */ 430 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 431 432 /* Setup RSC PDC handshake for sleep and wakeup */ 433 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 434 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 435 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 436 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 437 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 438 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 439 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 440 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 441 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 442 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 443 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 444 445 /* Load RSC sequencer uCode for sleep and wakeup */ 446 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 447 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 448 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 449 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 450 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 451 452 /* Load PDC sequencer uCode for power up and power down sequence */ 453 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 454 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 455 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 456 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 457 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 458 459 /* Set TCS commands used by PDC sequence for low power modes */ 460 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 461 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 462 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 463 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 464 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 465 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 466 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 467 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 468 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 469 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 470 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 471 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 472 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 473 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 474 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 475 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 476 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 477 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 478 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 479 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 480 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 481 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 482 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 483 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 484 485 /* Setup GPU PDC */ 486 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 487 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 488 489 /* ensure no writes happen before the uCode is fully written */ 490 wmb(); 491 492 err: 493 devm_iounmap(gmu->dev, pdcptr); 494 devm_iounmap(gmu->dev, seqptr); 495 } 496 497 /* 498 * The lowest 16 bits of this value are the number of XO clock cycles for main 499 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 500 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 501 */ 502 503 #define GMU_PWR_COL_HYST 0x000a1680 504 505 /* Set up the idle state for the GMU */ 506 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 507 { 508 /* Disable GMU WB/RB buffer */ 509 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 510 511 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 512 513 switch (gmu->idle_level) { 514 case GMU_IDLE_STATE_IFPC: 515 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 516 GMU_PWR_COL_HYST); 517 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 518 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 519 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 520 /* Fall through */ 521 case GMU_IDLE_STATE_SPTP: 522 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 523 GMU_PWR_COL_HYST); 524 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 525 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 526 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 527 } 528 529 /* Enable RPMh GPU client */ 530 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 531 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 532 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 533 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 534 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 535 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 536 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 537 } 538 539 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 540 { 541 static bool rpmh_init; 542 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 543 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 544 int i, ret; 545 u32 chipid; 546 u32 *image; 547 548 if (state == GMU_WARM_BOOT) { 549 ret = a6xx_rpmh_start(gmu); 550 if (ret) 551 return ret; 552 } else { 553 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 554 "GMU firmware is not loaded\n")) 555 return -ENOENT; 556 557 /* Sanity check the size of the firmware that was loaded */ 558 if (adreno_gpu->fw[ADRENO_FW_GMU]->size > 0x8000) { 559 DRM_DEV_ERROR(gmu->dev, 560 "GMU firmware is bigger than the available region\n"); 561 return -EINVAL; 562 } 563 564 /* Turn on register retention */ 565 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 566 567 /* We only need to load the RPMh microcode once */ 568 if (!rpmh_init) { 569 a6xx_gmu_rpmh_init(gmu); 570 rpmh_init = true; 571 } else if (state != GMU_RESET) { 572 ret = a6xx_rpmh_start(gmu); 573 if (ret) 574 return ret; 575 } 576 577 image = (u32 *) adreno_gpu->fw[ADRENO_FW_GMU]->data; 578 579 for (i = 0; i < adreno_gpu->fw[ADRENO_FW_GMU]->size >> 2; i++) 580 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, 581 image[i]); 582 } 583 584 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 585 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 586 587 /* Write the iova of the HFI table */ 588 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova); 589 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 590 591 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 592 (1 << 31) | (0xa << 18) | (0xa0)); 593 594 chipid = adreno_gpu->rev.core << 24; 595 chipid |= adreno_gpu->rev.major << 16; 596 chipid |= adreno_gpu->rev.minor << 12; 597 chipid |= adreno_gpu->rev.patchid << 8; 598 599 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 600 601 /* Set up the lowest idle level on the GMU */ 602 a6xx_gmu_power_config(gmu); 603 604 ret = a6xx_gmu_start(gmu); 605 if (ret) 606 return ret; 607 608 ret = a6xx_gmu_gfx_rail_on(gmu); 609 if (ret) 610 return ret; 611 612 /* Enable SPTP_PC if the CPU is responsible for it */ 613 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 614 ret = a6xx_sptprac_enable(gmu); 615 if (ret) 616 return ret; 617 } 618 619 ret = a6xx_gmu_hfi_start(gmu); 620 if (ret) 621 return ret; 622 623 /* FIXME: Do we need this wmb() here? */ 624 wmb(); 625 626 return 0; 627 } 628 629 #define A6XX_HFI_IRQ_MASK \ 630 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 631 632 #define A6XX_GMU_IRQ_MASK \ 633 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 634 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 635 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 636 637 static void a6xx_gmu_irq_enable(struct a6xx_gmu *gmu) 638 { 639 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 640 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 641 642 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, 643 ~A6XX_GMU_IRQ_MASK); 644 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, 645 ~A6XX_HFI_IRQ_MASK); 646 647 enable_irq(gmu->gmu_irq); 648 enable_irq(gmu->hfi_irq); 649 } 650 651 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 652 { 653 disable_irq(gmu->gmu_irq); 654 disable_irq(gmu->hfi_irq); 655 656 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 657 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 658 } 659 660 int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) 661 { 662 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 663 int ret; 664 u32 val; 665 666 /* Flush all the queues */ 667 a6xx_hfi_stop(gmu); 668 669 /* Stop the interrupts */ 670 a6xx_gmu_irq_disable(gmu); 671 672 /* Force off SPTP in case the GMU is managing it */ 673 a6xx_sptprac_disable(gmu); 674 675 /* Make sure there are no outstanding RPMh votes */ 676 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 677 (val & 1), 100, 10000); 678 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 679 (val & 1), 100, 10000); 680 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 681 (val & 1), 100, 10000); 682 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 683 (val & 1), 100, 1000); 684 685 /* 686 * Depending on the state of the GMU at this point the GX domain might 687 * have been left on. Hardware sequencing rules state that the GX has to 688 * be turned off before the CX domain so this is that one time that 689 * that calling pm_runtime_put_sync() is expected to do something useful 690 * (turn off the headswitch) 691 */ 692 if (!IS_ERR(gmu->gxpd)) 693 pm_runtime_put_sync(gmu->gxpd); 694 695 /* Disable the resources */ 696 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 697 pm_runtime_put_sync(gmu->dev); 698 699 /* Re-enable the resources */ 700 pm_runtime_get_sync(gmu->dev); 701 702 /* Use a known rate to bring up the GMU */ 703 clk_set_rate(gmu->core_clk, 200000000); 704 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 705 if (ret) 706 goto out; 707 708 a6xx_gmu_irq_enable(gmu); 709 710 ret = a6xx_gmu_fw_start(gmu, GMU_RESET); 711 if (!ret) 712 ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT); 713 714 /* Set the GPU back to the highest power frequency */ 715 __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); 716 717 out: 718 if (ret) 719 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 720 721 return ret; 722 } 723 724 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 725 { 726 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 727 struct msm_gpu *gpu = &adreno_gpu->base; 728 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 729 int status, ret; 730 731 if (WARN(!gmu->mmio, "The GMU is not set up yet\n")) 732 return 0; 733 734 /* Turn on the resources */ 735 pm_runtime_get_sync(gmu->dev); 736 737 /* Use a known rate to bring up the GMU */ 738 clk_set_rate(gmu->core_clk, 200000000); 739 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 740 if (ret) 741 goto out; 742 743 /* Set the bus quota to a reasonable value for boot */ 744 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 745 746 a6xx_gmu_irq_enable(gmu); 747 748 /* Check to see if we are doing a cold or warm boot */ 749 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 750 GMU_WARM_BOOT : GMU_COLD_BOOT; 751 752 ret = a6xx_gmu_fw_start(gmu, status); 753 if (ret) 754 goto out; 755 756 ret = a6xx_hfi_start(gmu, status); 757 758 /* Set the GPU to the highest power frequency */ 759 __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); 760 761 /* 762 * "enable" the GX power domain which won't actually do anything but it 763 * will make sure that the refcounting is correct in case we need to 764 * bring down the GX after a GMU failure 765 */ 766 if (!IS_ERR(gmu->gxpd)) 767 pm_runtime_get(gmu->gxpd); 768 769 out: 770 /* Make sure to turn off the boot OOB request on error */ 771 if (ret) 772 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 773 774 return ret; 775 } 776 777 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 778 { 779 u32 reg; 780 781 if (!gmu->mmio) 782 return true; 783 784 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 785 786 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 787 return false; 788 789 return true; 790 } 791 792 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 793 { 794 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 795 struct msm_gpu *gpu = &adreno_gpu->base; 796 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 797 u32 val; 798 799 /* 800 * The GMU may still be in slumber unless the GPU started so check and 801 * skip putting it back into slumber if so 802 */ 803 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 804 805 if (val != 0xf) { 806 int ret = a6xx_gmu_wait_for_idle(a6xx_gpu); 807 808 /* Temporary until we can recover safely */ 809 BUG_ON(ret); 810 811 /* tell the GMU we want to slumber */ 812 a6xx_gmu_notify_slumber(gmu); 813 814 ret = gmu_poll_timeout(gmu, 815 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 816 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 817 100, 10000); 818 819 /* 820 * Let the user know we failed to slumber but don't worry too 821 * much because we are powering down anyway 822 */ 823 824 if (ret) 825 DRM_DEV_ERROR(gmu->dev, 826 "Unable to slumber GMU: status = 0%x/0%x\n", 827 gmu_read(gmu, 828 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 829 gmu_read(gmu, 830 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 831 } 832 833 /* Turn off HFI */ 834 a6xx_hfi_stop(gmu); 835 836 /* Stop the interrupts and mask the hardware */ 837 a6xx_gmu_irq_disable(gmu); 838 839 /* Tell RPMh to power off the GPU */ 840 a6xx_rpmh_stop(gmu); 841 842 /* Remove the bus vote */ 843 icc_set_bw(gpu->icc_path, 0, 0); 844 845 /* 846 * Mark the GPU power domain as off. During the shutdown process the GMU 847 * should actually turn off the power so this is really just a 848 * houskeeping step 849 */ 850 if (!IS_ERR(gmu->gxpd)) 851 pm_runtime_put_sync(gmu->gxpd); 852 853 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 854 855 pm_runtime_put_sync(gmu->dev); 856 857 return 0; 858 } 859 860 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo) 861 { 862 int count, i; 863 u64 iova; 864 865 if (IS_ERR_OR_NULL(bo)) 866 return; 867 868 count = bo->size >> PAGE_SHIFT; 869 iova = bo->iova; 870 871 for (i = 0; i < count; i++, iova += PAGE_SIZE) { 872 iommu_unmap(gmu->domain, iova, PAGE_SIZE); 873 __free_pages(bo->pages[i], 0); 874 } 875 876 kfree(bo->pages); 877 kfree(bo); 878 } 879 880 static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, 881 size_t size) 882 { 883 struct a6xx_gmu_bo *bo; 884 int ret, count, i; 885 886 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 887 if (!bo) 888 return ERR_PTR(-ENOMEM); 889 890 bo->size = PAGE_ALIGN(size); 891 892 count = bo->size >> PAGE_SHIFT; 893 894 bo->pages = kcalloc(count, sizeof(struct page *), GFP_KERNEL); 895 if (!bo->pages) { 896 kfree(bo); 897 return ERR_PTR(-ENOMEM); 898 } 899 900 for (i = 0; i < count; i++) { 901 bo->pages[i] = alloc_page(GFP_KERNEL); 902 if (!bo->pages[i]) 903 goto err; 904 } 905 906 bo->iova = gmu->uncached_iova_base; 907 908 for (i = 0; i < count; i++) { 909 ret = iommu_map(gmu->domain, 910 bo->iova + (PAGE_SIZE * i), 911 page_to_phys(bo->pages[i]), PAGE_SIZE, 912 IOMMU_READ | IOMMU_WRITE); 913 914 if (ret) { 915 DRM_DEV_ERROR(gmu->dev, "Unable to map GMU buffer object\n"); 916 917 for (i = i - 1 ; i >= 0; i--) 918 iommu_unmap(gmu->domain, 919 bo->iova + (PAGE_SIZE * i), 920 PAGE_SIZE); 921 922 goto err; 923 } 924 } 925 926 bo->virt = vmap(bo->pages, count, VM_IOREMAP, 927 pgprot_writecombine(PAGE_KERNEL)); 928 if (!bo->virt) 929 goto err; 930 931 /* Align future IOVA addresses on 1MB boundaries */ 932 gmu->uncached_iova_base += ALIGN(size, SZ_1M); 933 934 return bo; 935 936 err: 937 for (i = 0; i < count; i++) { 938 if (bo->pages[i]) 939 __free_pages(bo->pages[i], 0); 940 } 941 942 kfree(bo->pages); 943 kfree(bo); 944 945 return ERR_PTR(-ENOMEM); 946 } 947 948 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 949 { 950 int ret; 951 952 /* 953 * The GMU address space is hardcoded to treat the range 954 * 0x60000000 - 0x80000000 as un-cached memory. All buffers shared 955 * between the GMU and the CPU will live in this space 956 */ 957 gmu->uncached_iova_base = 0x60000000; 958 959 960 gmu->domain = iommu_domain_alloc(&platform_bus_type); 961 if (!gmu->domain) 962 return -ENODEV; 963 964 ret = iommu_attach_device(gmu->domain, gmu->dev); 965 966 if (ret) { 967 iommu_domain_free(gmu->domain); 968 gmu->domain = NULL; 969 } 970 971 return ret; 972 } 973 974 /* Return the 'arc-level' for the given frequency */ 975 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 976 unsigned long freq) 977 { 978 struct dev_pm_opp *opp; 979 unsigned int val; 980 981 if (!freq) 982 return 0; 983 984 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 985 if (IS_ERR(opp)) 986 return 0; 987 988 val = dev_pm_opp_get_level(opp); 989 990 dev_pm_opp_put(opp); 991 992 return val; 993 } 994 995 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 996 unsigned long *freqs, int freqs_count, const char *id) 997 { 998 int i, j; 999 const u16 *pri, *sec; 1000 size_t pri_count, sec_count; 1001 1002 pri = cmd_db_read_aux_data(id, &pri_count); 1003 if (IS_ERR(pri)) 1004 return PTR_ERR(pri); 1005 /* 1006 * The data comes back as an array of unsigned shorts so adjust the 1007 * count accordingly 1008 */ 1009 pri_count >>= 1; 1010 if (!pri_count) 1011 return -EINVAL; 1012 1013 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1014 if (IS_ERR(sec)) 1015 return PTR_ERR(sec); 1016 1017 sec_count >>= 1; 1018 if (!sec_count) 1019 return -EINVAL; 1020 1021 /* Construct a vote for each frequency */ 1022 for (i = 0; i < freqs_count; i++) { 1023 u8 pindex = 0, sindex = 0; 1024 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1025 1026 /* Get the primary index that matches the arc level */ 1027 for (j = 0; j < pri_count; j++) { 1028 if (pri[j] >= level) { 1029 pindex = j; 1030 break; 1031 } 1032 } 1033 1034 if (j == pri_count) { 1035 DRM_DEV_ERROR(dev, 1036 "Level %u not found in in the RPMh list\n", 1037 level); 1038 DRM_DEV_ERROR(dev, "Available levels:\n"); 1039 for (j = 0; j < pri_count; j++) 1040 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1041 1042 return -EINVAL; 1043 } 1044 1045 /* 1046 * Look for a level in in the secondary list that matches. If 1047 * nothing fits, use the maximum non zero vote 1048 */ 1049 1050 for (j = 0; j < sec_count; j++) { 1051 if (sec[j] >= level) { 1052 sindex = j; 1053 break; 1054 } else if (sec[j]) { 1055 sindex = j; 1056 } 1057 } 1058 1059 /* Construct the vote */ 1060 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1061 (sindex << 8) | pindex; 1062 } 1063 1064 return 0; 1065 } 1066 1067 /* 1068 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1069 * to construct the list of votes on the CPU and send it over. Query the RPMh 1070 * voltage levels and build the votes 1071 */ 1072 1073 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1074 { 1075 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1076 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1077 struct msm_gpu *gpu = &adreno_gpu->base; 1078 int ret; 1079 1080 /* Build the GX votes */ 1081 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1082 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1083 1084 /* Build the CX votes */ 1085 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1086 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1087 1088 return ret; 1089 } 1090 1091 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1092 u32 size) 1093 { 1094 int count = dev_pm_opp_get_opp_count(dev); 1095 struct dev_pm_opp *opp; 1096 int i, index = 0; 1097 unsigned long freq = 1; 1098 1099 /* 1100 * The OPP table doesn't contain the "off" frequency level so we need to 1101 * add 1 to the table size to account for it 1102 */ 1103 1104 if (WARN(count + 1 > size, 1105 "The GMU frequency table is being truncated\n")) 1106 count = size - 1; 1107 1108 /* Set the "off" frequency */ 1109 freqs[index++] = 0; 1110 1111 for (i = 0; i < count; i++) { 1112 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1113 if (IS_ERR(opp)) 1114 break; 1115 1116 dev_pm_opp_put(opp); 1117 freqs[index++] = freq++; 1118 } 1119 1120 return index; 1121 } 1122 1123 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1124 { 1125 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1126 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1127 struct msm_gpu *gpu = &adreno_gpu->base; 1128 1129 int ret = 0; 1130 1131 /* 1132 * The GMU handles its own frequency switching so build a list of 1133 * available frequencies to send during initialization 1134 */ 1135 ret = dev_pm_opp_of_add_table(gmu->dev); 1136 if (ret) { 1137 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1138 return ret; 1139 } 1140 1141 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1142 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1143 1144 /* 1145 * The GMU also handles GPU frequency switching so build a list 1146 * from the GPU OPP table 1147 */ 1148 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1149 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1150 1151 /* Build the list of RPMh votes that we'll send to the GMU */ 1152 return a6xx_gmu_rpmh_votes_init(gmu); 1153 } 1154 1155 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1156 { 1157 int ret = msm_clk_bulk_get(gmu->dev, &gmu->clocks); 1158 1159 if (ret < 1) 1160 return ret; 1161 1162 gmu->nr_clocks = ret; 1163 1164 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1165 gmu->nr_clocks, "gmu"); 1166 1167 return 0; 1168 } 1169 1170 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1171 const char *name) 1172 { 1173 void __iomem *ret; 1174 struct resource *res = platform_get_resource_byname(pdev, 1175 IORESOURCE_MEM, name); 1176 1177 if (!res) { 1178 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1179 return ERR_PTR(-EINVAL); 1180 } 1181 1182 ret = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 1183 if (!ret) { 1184 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1185 return ERR_PTR(-EINVAL); 1186 } 1187 1188 return ret; 1189 } 1190 1191 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1192 const char *name, irq_handler_t handler) 1193 { 1194 int irq, ret; 1195 1196 irq = platform_get_irq_byname(pdev, name); 1197 1198 ret = devm_request_irq(&pdev->dev, irq, handler, IRQF_TRIGGER_HIGH, 1199 name, gmu); 1200 if (ret) { 1201 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s\n", name); 1202 return ret; 1203 } 1204 1205 disable_irq(irq); 1206 1207 return irq; 1208 } 1209 1210 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1211 { 1212 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1213 1214 if (IS_ERR_OR_NULL(gmu->mmio)) 1215 return; 1216 1217 a6xx_gmu_stop(a6xx_gpu); 1218 1219 pm_runtime_disable(gmu->dev); 1220 1221 if (!IS_ERR(gmu->gxpd)) { 1222 pm_runtime_disable(gmu->gxpd); 1223 dev_pm_domain_detach(gmu->gxpd, false); 1224 } 1225 1226 a6xx_gmu_irq_disable(gmu); 1227 a6xx_gmu_memory_free(gmu, gmu->hfi); 1228 1229 iommu_detach_device(gmu->domain, gmu->dev); 1230 1231 iommu_domain_free(gmu->domain); 1232 } 1233 1234 int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1235 { 1236 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1237 struct platform_device *pdev = of_find_device_by_node(node); 1238 int ret; 1239 1240 if (!pdev) 1241 return -ENODEV; 1242 1243 gmu->dev = &pdev->dev; 1244 1245 of_dma_configure(gmu->dev, node, true); 1246 1247 /* Fow now, don't do anything fancy until we get our feet under us */ 1248 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1249 1250 pm_runtime_enable(gmu->dev); 1251 1252 /* Get the list of clocks */ 1253 ret = a6xx_gmu_clocks_probe(gmu); 1254 if (ret) 1255 return ret; 1256 1257 /* Set up the IOMMU context bank */ 1258 ret = a6xx_gmu_memory_probe(gmu); 1259 if (ret) 1260 return ret; 1261 1262 /* Allocate memory for for the HFI queues */ 1263 gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1264 if (IS_ERR(gmu->hfi)) 1265 goto err; 1266 1267 /* Allocate memory for the GMU debug region */ 1268 gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1269 if (IS_ERR(gmu->debug)) 1270 goto err; 1271 1272 /* Map the GMU registers */ 1273 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1274 if (IS_ERR(gmu->mmio)) 1275 goto err; 1276 1277 /* Get the HFI and GMU interrupts */ 1278 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1279 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1280 1281 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1282 goto err; 1283 1284 /* 1285 * Get a link to the GX power domain to reset the GPU in case of GMU 1286 * crash 1287 */ 1288 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1289 1290 /* Get the power levels for the GMU and GPU */ 1291 a6xx_gmu_pwrlevels_probe(gmu); 1292 1293 /* Set up the HFI queues */ 1294 a6xx_hfi_init(gmu); 1295 1296 return 0; 1297 err: 1298 a6xx_gmu_memory_free(gmu, gmu->hfi); 1299 1300 if (gmu->domain) { 1301 iommu_detach_device(gmu->domain, gmu->dev); 1302 1303 iommu_domain_free(gmu->domain); 1304 } 1305 1306 return -ENODEV; 1307 } 1308