1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_mmu.h" 15 16 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 17 { 18 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 19 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 20 struct msm_gpu *gpu = &adreno_gpu->base; 21 struct drm_device *dev = gpu->dev; 22 struct msm_drm_private *priv = dev->dev_private; 23 24 /* FIXME: add a banner here */ 25 gmu->hung = true; 26 27 /* Turn off the hangcheck timer while we are resetting */ 28 del_timer(&gpu->hangcheck_timer); 29 30 /* Queue the GPU handler because we need to treat this as a recovery */ 31 queue_work(priv->wq, &gpu->recover_work); 32 } 33 34 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 35 { 36 struct a6xx_gmu *gmu = data; 37 u32 status; 38 39 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 40 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 41 42 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 43 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 44 45 a6xx_gmu_fault(gmu); 46 } 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 49 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 52 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 53 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 54 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 59 { 60 struct a6xx_gmu *gmu = data; 61 u32 status; 62 63 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 64 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 65 66 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 67 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 68 69 a6xx_gmu_fault(gmu); 70 } 71 72 return IRQ_HANDLED; 73 } 74 75 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 76 { 77 u32 val; 78 79 /* This can be called from gpu state code so make sure GMU is valid */ 80 if (!gmu->initialized) 81 return false; 82 83 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 84 85 return !(val & 86 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 87 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 88 } 89 90 /* Check to see if the GX rail is still powered */ 91 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 92 { 93 u32 val; 94 95 /* This can be called from gpu state code so make sure GMU is valid */ 96 if (!gmu->initialized) 97 return false; 98 99 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 100 101 return !(val & 102 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 103 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 104 } 105 106 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 107 { 108 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 109 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 110 struct msm_gpu *gpu = &adreno_gpu->base; 111 int ret; 112 113 /* 114 * This can get called from devfreq while the hardware is idle. Don't 115 * bring up the power if it isn't already active 116 */ 117 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 118 return; 119 120 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 121 122 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 123 ((3 & 0xf) << 28) | index); 124 125 /* 126 * Send an invalid index as a vote for the bus bandwidth and let the 127 * firmware decide on the right vote 128 */ 129 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 130 131 /* Set and clear the OOB for DCVS to trigger the GMU */ 132 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 133 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 134 135 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 136 if (ret) 137 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 138 139 /* 140 * Eventually we will want to scale the path vote with the frequency but 141 * for now leave it at max so that the performance is nominal. 142 */ 143 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 144 pm_runtime_put(gmu->dev); 145 } 146 147 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 148 { 149 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 150 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 151 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 152 u32 perf_index = 0; 153 154 if (freq == gmu->freq) 155 return; 156 157 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 158 if (freq == gmu->gpu_freqs[perf_index]) 159 break; 160 161 gmu->current_perf_index = perf_index; 162 163 if (gmu->legacy) 164 __a6xx_gmu_set_freq(gmu, perf_index); 165 else 166 a6xx_hfi_set_freq(gmu, perf_index); 167 168 gmu->freq = gmu->gpu_freqs[perf_index]; 169 } 170 171 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 172 { 173 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 174 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 175 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 176 177 return gmu->freq; 178 } 179 180 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 181 { 182 u32 val; 183 int local = gmu->idle_level; 184 185 /* SPTP and IFPC both report as IFPC */ 186 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 187 local = GMU_IDLE_STATE_IFPC; 188 189 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 190 191 if (val == local) { 192 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 193 !a6xx_gmu_gx_is_on(gmu)) 194 return true; 195 } 196 197 return false; 198 } 199 200 /* Wait for the GMU to get to its most idle state */ 201 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 202 { 203 return spin_until(a6xx_gmu_check_idle_level(gmu)); 204 } 205 206 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 207 { 208 int ret; 209 u32 val; 210 211 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 212 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 213 214 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 215 val == 0xbabeface, 100, 10000); 216 217 if (ret) 218 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 219 220 return ret; 221 } 222 223 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 224 { 225 u32 val; 226 int ret; 227 228 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 229 230 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 231 val & 1, 100, 10000); 232 if (ret) 233 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 234 235 return ret; 236 } 237 238 /* Trigger a OOB (out of band) request to the GMU */ 239 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 240 { 241 int ret; 242 u32 val; 243 int request, ack; 244 const char *name; 245 246 switch (state) { 247 case GMU_OOB_GPU_SET: 248 if (gmu->legacy) { 249 request = GMU_OOB_GPU_SET_REQUEST; 250 ack = GMU_OOB_GPU_SET_ACK; 251 } else { 252 request = GMU_OOB_GPU_SET_REQUEST_NEW; 253 ack = GMU_OOB_GPU_SET_ACK_NEW; 254 } 255 name = "GPU_SET"; 256 break; 257 case GMU_OOB_BOOT_SLUMBER: 258 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 259 ack = GMU_OOB_BOOT_SLUMBER_ACK; 260 name = "BOOT_SLUMBER"; 261 break; 262 case GMU_OOB_DCVS_SET: 263 request = GMU_OOB_DCVS_REQUEST; 264 ack = GMU_OOB_DCVS_ACK; 265 name = "GPU_DCVS"; 266 break; 267 default: 268 return -EINVAL; 269 } 270 271 /* Trigger the equested OOB operation */ 272 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 273 274 /* Wait for the acknowledge interrupt */ 275 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 276 val & (1 << ack), 100, 10000); 277 278 if (ret) 279 DRM_DEV_ERROR(gmu->dev, 280 "Timeout waiting for GMU OOB set %s: 0x%x\n", 281 name, 282 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 283 284 /* Clear the acknowledge interrupt */ 285 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 286 287 return ret; 288 } 289 290 /* Clear a pending OOB state in the GMU */ 291 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 292 { 293 if (!gmu->legacy) { 294 WARN_ON(state != GMU_OOB_GPU_SET); 295 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 296 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 297 return; 298 } 299 300 switch (state) { 301 case GMU_OOB_GPU_SET: 302 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 303 1 << GMU_OOB_GPU_SET_CLEAR); 304 break; 305 case GMU_OOB_BOOT_SLUMBER: 306 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 307 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 308 break; 309 case GMU_OOB_DCVS_SET: 310 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 311 1 << GMU_OOB_DCVS_CLEAR); 312 break; 313 } 314 } 315 316 /* Enable CPU control of SPTP power power collapse */ 317 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 318 { 319 int ret; 320 u32 val; 321 322 if (!gmu->legacy) 323 return 0; 324 325 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 326 327 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 328 (val & 0x38) == 0x28, 1, 100); 329 330 if (ret) { 331 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 332 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 333 } 334 335 return 0; 336 } 337 338 /* Disable CPU control of SPTP power power collapse */ 339 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 340 { 341 u32 val; 342 int ret; 343 344 if (!gmu->legacy) 345 return; 346 347 /* Make sure retention is on */ 348 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 349 350 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 351 352 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 353 (val & 0x04), 100, 10000); 354 355 if (ret) 356 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 357 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 358 } 359 360 /* Let the GMU know we are starting a boot sequence */ 361 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 362 { 363 u32 vote; 364 365 /* Let the GMU know we are getting ready for boot */ 366 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 367 368 /* Choose the "default" power level as the highest available */ 369 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 370 371 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 372 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 373 374 /* Let the GMU know the boot sequence has started */ 375 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 376 } 377 378 /* Let the GMU know that we are about to go into slumber */ 379 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 380 { 381 int ret; 382 383 /* Disable the power counter so the GMU isn't busy */ 384 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 385 386 /* Disable SPTP_PC if the CPU is responsible for it */ 387 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 388 a6xx_sptprac_disable(gmu); 389 390 if (!gmu->legacy) { 391 ret = a6xx_hfi_send_prep_slumber(gmu); 392 goto out; 393 } 394 395 /* Tell the GMU to get ready to slumber */ 396 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 397 398 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 399 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 400 401 if (!ret) { 402 /* Check to see if the GMU really did slumber */ 403 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 404 != 0x0f) { 405 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 406 ret = -ETIMEDOUT; 407 } 408 } 409 410 out: 411 /* Put fence into allow mode */ 412 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 413 return ret; 414 } 415 416 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 417 { 418 int ret; 419 u32 val; 420 421 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 422 /* Wait for the register to finish posting */ 423 wmb(); 424 425 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 426 val & (1 << 1), 100, 10000); 427 if (ret) { 428 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 429 return ret; 430 } 431 432 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 433 !val, 100, 10000); 434 435 if (ret) { 436 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 437 return ret; 438 } 439 440 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 441 442 /* Set up CX GMU counter 0 to count busy ticks */ 443 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 444 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 445 446 /* Enable the power counter */ 447 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 448 return 0; 449 } 450 451 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 452 { 453 int ret; 454 u32 val; 455 456 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 457 458 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 459 val, val & (1 << 16), 100, 10000); 460 if (ret) 461 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 462 463 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 464 } 465 466 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 467 { 468 return msm_writel(value, ptr + (offset << 2)); 469 } 470 471 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 472 const char *name); 473 474 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 475 { 476 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 477 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 478 struct platform_device *pdev = to_platform_device(gmu->dev); 479 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 480 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 481 482 if (!pdcptr || !seqptr) 483 goto err; 484 485 /* Disable SDE clock gating */ 486 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 487 488 /* Setup RSC PDC handshake for sleep and wakeup */ 489 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 490 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 491 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 492 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 493 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 494 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 495 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 496 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 497 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 498 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 499 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 500 501 /* Load RSC sequencer uCode for sleep and wakeup */ 502 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 503 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 504 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 505 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 506 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 507 508 /* Load PDC sequencer uCode for power up and power down sequence */ 509 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 510 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 511 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 512 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 513 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 514 515 /* Set TCS commands used by PDC sequence for low power modes */ 516 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 517 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 518 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 519 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 520 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 521 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 522 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 523 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 524 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 525 526 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 527 if (adreno_is_a618(adreno_gpu)) 528 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090); 529 else 530 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 531 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 532 533 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 534 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 535 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 536 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 537 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 538 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 539 540 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 541 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 542 if (adreno_is_a618(adreno_gpu)) 543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 544 else 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 546 547 548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 549 if (adreno_is_a618(adreno_gpu)) 550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090); 551 else 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 554 555 /* Setup GPU PDC */ 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 558 559 /* ensure no writes happen before the uCode is fully written */ 560 wmb(); 561 562 err: 563 if (!IS_ERR_OR_NULL(pdcptr)) 564 iounmap(pdcptr); 565 if (!IS_ERR_OR_NULL(seqptr)) 566 iounmap(seqptr); 567 } 568 569 /* 570 * The lowest 16 bits of this value are the number of XO clock cycles for main 571 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 572 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 573 */ 574 575 #define GMU_PWR_COL_HYST 0x000a1680 576 577 /* Set up the idle state for the GMU */ 578 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 579 { 580 /* Disable GMU WB/RB buffer */ 581 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 582 583 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 584 585 switch (gmu->idle_level) { 586 case GMU_IDLE_STATE_IFPC: 587 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 588 GMU_PWR_COL_HYST); 589 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 590 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 591 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 592 /* Fall through */ 593 case GMU_IDLE_STATE_SPTP: 594 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 595 GMU_PWR_COL_HYST); 596 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 597 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 598 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 599 } 600 601 /* Enable RPMh GPU client */ 602 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 603 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 604 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 605 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 606 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 607 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 608 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 609 } 610 611 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 612 { 613 static bool rpmh_init; 614 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 615 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 616 int i, ret; 617 u32 chipid; 618 u32 *image; 619 620 if (state == GMU_WARM_BOOT) { 621 ret = a6xx_rpmh_start(gmu); 622 if (ret) 623 return ret; 624 } else { 625 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 626 "GMU firmware is not loaded\n")) 627 return -ENOENT; 628 629 /* Sanity check the size of the firmware that was loaded */ 630 if (adreno_gpu->fw[ADRENO_FW_GMU]->size > 0x8000) { 631 DRM_DEV_ERROR(gmu->dev, 632 "GMU firmware is bigger than the available region\n"); 633 return -EINVAL; 634 } 635 636 /* Turn on register retention */ 637 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 638 639 /* We only need to load the RPMh microcode once */ 640 if (!rpmh_init) { 641 a6xx_gmu_rpmh_init(gmu); 642 rpmh_init = true; 643 } else { 644 ret = a6xx_rpmh_start(gmu); 645 if (ret) 646 return ret; 647 } 648 649 image = (u32 *) adreno_gpu->fw[ADRENO_FW_GMU]->data; 650 651 for (i = 0; i < adreno_gpu->fw[ADRENO_FW_GMU]->size >> 2; i++) 652 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, 653 image[i]); 654 } 655 656 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 657 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 658 659 /* Write the iova of the HFI table */ 660 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 661 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 662 663 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 664 (1 << 31) | (0xa << 18) | (0xa0)); 665 666 chipid = adreno_gpu->rev.core << 24; 667 chipid |= adreno_gpu->rev.major << 16; 668 chipid |= adreno_gpu->rev.minor << 12; 669 chipid |= adreno_gpu->rev.patchid << 8; 670 671 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 672 673 /* Set up the lowest idle level on the GMU */ 674 a6xx_gmu_power_config(gmu); 675 676 ret = a6xx_gmu_start(gmu); 677 if (ret) 678 return ret; 679 680 if (gmu->legacy) { 681 ret = a6xx_gmu_gfx_rail_on(gmu); 682 if (ret) 683 return ret; 684 } 685 686 /* Enable SPTP_PC if the CPU is responsible for it */ 687 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 688 ret = a6xx_sptprac_enable(gmu); 689 if (ret) 690 return ret; 691 } 692 693 ret = a6xx_gmu_hfi_start(gmu); 694 if (ret) 695 return ret; 696 697 /* FIXME: Do we need this wmb() here? */ 698 wmb(); 699 700 return 0; 701 } 702 703 #define A6XX_HFI_IRQ_MASK \ 704 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 705 706 #define A6XX_GMU_IRQ_MASK \ 707 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 708 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 709 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 710 711 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 712 { 713 disable_irq(gmu->gmu_irq); 714 disable_irq(gmu->hfi_irq); 715 716 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 717 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 718 } 719 720 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 721 { 722 u32 val; 723 724 /* Make sure there are no outstanding RPMh votes */ 725 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 726 (val & 1), 100, 10000); 727 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 728 (val & 1), 100, 10000); 729 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 730 (val & 1), 100, 10000); 731 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 732 (val & 1), 100, 1000); 733 } 734 735 /* Force the GMU off in case it isn't responsive */ 736 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 737 { 738 /* Flush all the queues */ 739 a6xx_hfi_stop(gmu); 740 741 /* Stop the interrupts */ 742 a6xx_gmu_irq_disable(gmu); 743 744 /* Force off SPTP in case the GMU is managing it */ 745 a6xx_sptprac_disable(gmu); 746 747 /* Make sure there are no outstanding RPMh votes */ 748 a6xx_gmu_rpmh_off(gmu); 749 } 750 751 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 752 { 753 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 754 struct msm_gpu *gpu = &adreno_gpu->base; 755 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 756 int status, ret; 757 758 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 759 return 0; 760 761 gmu->hung = false; 762 763 /* Turn on the resources */ 764 pm_runtime_get_sync(gmu->dev); 765 766 /* Use a known rate to bring up the GMU */ 767 clk_set_rate(gmu->core_clk, 200000000); 768 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 769 if (ret) { 770 pm_runtime_put(gmu->dev); 771 return ret; 772 } 773 774 /* Set the bus quota to a reasonable value for boot */ 775 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 776 777 /* Enable the GMU interrupt */ 778 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 779 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 780 enable_irq(gmu->gmu_irq); 781 782 /* Check to see if we are doing a cold or warm boot */ 783 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 784 GMU_WARM_BOOT : GMU_COLD_BOOT; 785 786 ret = a6xx_gmu_fw_start(gmu, status); 787 if (ret) 788 goto out; 789 790 ret = a6xx_hfi_start(gmu, status); 791 if (ret) 792 goto out; 793 794 /* 795 * Turn on the GMU firmware fault interrupt after we know the boot 796 * sequence is successful 797 */ 798 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 799 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 800 enable_irq(gmu->hfi_irq); 801 802 /* Set the GPU to the current freq */ 803 if (gmu->legacy) 804 __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); 805 else 806 a6xx_hfi_set_freq(gmu, gmu->current_perf_index); 807 808 /* 809 * "enable" the GX power domain which won't actually do anything but it 810 * will make sure that the refcounting is correct in case we need to 811 * bring down the GX after a GMU failure 812 */ 813 if (!IS_ERR_OR_NULL(gmu->gxpd)) 814 pm_runtime_get(gmu->gxpd); 815 816 out: 817 /* On failure, shut down the GMU to leave it in a good state */ 818 if (ret) { 819 disable_irq(gmu->gmu_irq); 820 a6xx_rpmh_stop(gmu); 821 pm_runtime_put(gmu->dev); 822 } 823 824 return ret; 825 } 826 827 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 828 { 829 u32 reg; 830 831 if (!gmu->initialized) 832 return true; 833 834 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 835 836 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 837 return false; 838 839 return true; 840 } 841 842 #define GBIF_CLIENT_HALT_MASK BIT(0) 843 #define GBIF_ARB_HALT_MASK BIT(1) 844 845 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 846 { 847 struct msm_gpu *gpu = &adreno_gpu->base; 848 849 if (!a6xx_has_gbif(adreno_gpu)) { 850 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 851 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 852 0xf) == 0xf); 853 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 854 855 return; 856 } 857 858 /* Halt new client requests on GBIF */ 859 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 860 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 861 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 862 863 /* Halt all AXI requests on GBIF */ 864 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 865 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 866 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 867 868 /* The GBIF halt needs to be explicitly cleared */ 869 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 870 } 871 872 /* Gracefully try to shut down the GMU and by extension the GPU */ 873 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 874 { 875 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 876 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 877 u32 val; 878 879 /* 880 * The GMU may still be in slumber unless the GPU started so check and 881 * skip putting it back into slumber if so 882 */ 883 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 884 885 if (val != 0xf) { 886 int ret = a6xx_gmu_wait_for_idle(gmu); 887 888 /* If the GMU isn't responding assume it is hung */ 889 if (ret) { 890 a6xx_gmu_force_off(gmu); 891 return; 892 } 893 894 a6xx_bus_clear_pending_transactions(adreno_gpu); 895 896 /* tell the GMU we want to slumber */ 897 a6xx_gmu_notify_slumber(gmu); 898 899 ret = gmu_poll_timeout(gmu, 900 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 901 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 902 100, 10000); 903 904 /* 905 * Let the user know we failed to slumber but don't worry too 906 * much because we are powering down anyway 907 */ 908 909 if (ret) 910 DRM_DEV_ERROR(gmu->dev, 911 "Unable to slumber GMU: status = 0%x/0%x\n", 912 gmu_read(gmu, 913 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 914 gmu_read(gmu, 915 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 916 } 917 918 /* Turn off HFI */ 919 a6xx_hfi_stop(gmu); 920 921 /* Stop the interrupts and mask the hardware */ 922 a6xx_gmu_irq_disable(gmu); 923 924 /* Tell RPMh to power off the GPU */ 925 a6xx_rpmh_stop(gmu); 926 } 927 928 929 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 930 { 931 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 932 struct msm_gpu *gpu = &a6xx_gpu->base.base; 933 934 if (!pm_runtime_active(gmu->dev)) 935 return 0; 936 937 /* 938 * Force the GMU off if we detected a hang, otherwise try to shut it 939 * down gracefully 940 */ 941 if (gmu->hung) 942 a6xx_gmu_force_off(gmu); 943 else 944 a6xx_gmu_shutdown(gmu); 945 946 /* Remove the bus vote */ 947 icc_set_bw(gpu->icc_path, 0, 0); 948 949 /* 950 * Make sure the GX domain is off before turning off the GMU (CX) 951 * domain. Usually the GMU does this but only if the shutdown sequence 952 * was successful 953 */ 954 if (!IS_ERR_OR_NULL(gmu->gxpd)) 955 pm_runtime_put_sync(gmu->gxpd); 956 957 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 958 959 pm_runtime_put_sync(gmu->dev); 960 961 return 0; 962 } 963 964 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 965 { 966 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 967 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 968 969 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 970 msm_gem_address_space_put(gmu->aspace); 971 } 972 973 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 974 size_t size, u64 iova) 975 { 976 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 977 struct drm_device *dev = a6xx_gpu->base.base.dev; 978 uint32_t flags = MSM_BO_WC; 979 u64 range_start, range_end; 980 int ret; 981 982 size = PAGE_ALIGN(size); 983 if (!iova) { 984 /* no fixed address - use GMU's uncached range */ 985 range_start = 0x60000000; 986 range_end = 0x80000000; 987 } else { 988 /* range for fixed address */ 989 range_start = iova; 990 range_end = iova + size; 991 } 992 993 bo->obj = msm_gem_new(dev, size, flags); 994 if (IS_ERR(bo->obj)) 995 return PTR_ERR(bo->obj); 996 997 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 998 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 999 if (ret) { 1000 drm_gem_object_put(bo->obj); 1001 return ret; 1002 } 1003 1004 bo->virt = msm_gem_get_vaddr(bo->obj); 1005 bo->size = size; 1006 1007 return 0; 1008 } 1009 1010 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1011 { 1012 struct iommu_domain *domain; 1013 int ret; 1014 1015 domain = iommu_domain_alloc(&platform_bus_type); 1016 if (!domain) 1017 return -ENODEV; 1018 1019 domain->geometry.aperture_start = 0x00000000; 1020 domain->geometry.aperture_end = 0x7fffffff; 1021 1022 gmu->aspace = msm_gem_address_space_create(gmu->dev, domain, "gmu"); 1023 if (IS_ERR(gmu->aspace)) { 1024 iommu_domain_free(domain); 1025 return PTR_ERR(gmu->aspace); 1026 } 1027 1028 ret = gmu->aspace->mmu->funcs->attach(gmu->aspace->mmu); 1029 if (ret) { 1030 msm_gem_address_space_put(gmu->aspace); 1031 return ret; 1032 } 1033 1034 return 0; 1035 } 1036 1037 /* Return the 'arc-level' for the given frequency */ 1038 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1039 unsigned long freq) 1040 { 1041 struct dev_pm_opp *opp; 1042 unsigned int val; 1043 1044 if (!freq) 1045 return 0; 1046 1047 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1048 if (IS_ERR(opp)) 1049 return 0; 1050 1051 val = dev_pm_opp_get_level(opp); 1052 1053 dev_pm_opp_put(opp); 1054 1055 return val; 1056 } 1057 1058 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1059 unsigned long *freqs, int freqs_count, const char *id) 1060 { 1061 int i, j; 1062 const u16 *pri, *sec; 1063 size_t pri_count, sec_count; 1064 1065 pri = cmd_db_read_aux_data(id, &pri_count); 1066 if (IS_ERR(pri)) 1067 return PTR_ERR(pri); 1068 /* 1069 * The data comes back as an array of unsigned shorts so adjust the 1070 * count accordingly 1071 */ 1072 pri_count >>= 1; 1073 if (!pri_count) 1074 return -EINVAL; 1075 1076 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1077 if (IS_ERR(sec)) 1078 return PTR_ERR(sec); 1079 1080 sec_count >>= 1; 1081 if (!sec_count) 1082 return -EINVAL; 1083 1084 /* Construct a vote for each frequency */ 1085 for (i = 0; i < freqs_count; i++) { 1086 u8 pindex = 0, sindex = 0; 1087 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1088 1089 /* Get the primary index that matches the arc level */ 1090 for (j = 0; j < pri_count; j++) { 1091 if (pri[j] >= level) { 1092 pindex = j; 1093 break; 1094 } 1095 } 1096 1097 if (j == pri_count) { 1098 DRM_DEV_ERROR(dev, 1099 "Level %u not found in the RPMh list\n", 1100 level); 1101 DRM_DEV_ERROR(dev, "Available levels:\n"); 1102 for (j = 0; j < pri_count; j++) 1103 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1104 1105 return -EINVAL; 1106 } 1107 1108 /* 1109 * Look for a level in in the secondary list that matches. If 1110 * nothing fits, use the maximum non zero vote 1111 */ 1112 1113 for (j = 0; j < sec_count; j++) { 1114 if (sec[j] >= level) { 1115 sindex = j; 1116 break; 1117 } else if (sec[j]) { 1118 sindex = j; 1119 } 1120 } 1121 1122 /* Construct the vote */ 1123 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1124 (sindex << 8) | pindex; 1125 } 1126 1127 return 0; 1128 } 1129 1130 /* 1131 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1132 * to construct the list of votes on the CPU and send it over. Query the RPMh 1133 * voltage levels and build the votes 1134 */ 1135 1136 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1137 { 1138 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1139 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1140 struct msm_gpu *gpu = &adreno_gpu->base; 1141 int ret; 1142 1143 /* Build the GX votes */ 1144 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1145 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1146 1147 /* Build the CX votes */ 1148 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1149 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1150 1151 return ret; 1152 } 1153 1154 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1155 u32 size) 1156 { 1157 int count = dev_pm_opp_get_opp_count(dev); 1158 struct dev_pm_opp *opp; 1159 int i, index = 0; 1160 unsigned long freq = 1; 1161 1162 /* 1163 * The OPP table doesn't contain the "off" frequency level so we need to 1164 * add 1 to the table size to account for it 1165 */ 1166 1167 if (WARN(count + 1 > size, 1168 "The GMU frequency table is being truncated\n")) 1169 count = size - 1; 1170 1171 /* Set the "off" frequency */ 1172 freqs[index++] = 0; 1173 1174 for (i = 0; i < count; i++) { 1175 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1176 if (IS_ERR(opp)) 1177 break; 1178 1179 dev_pm_opp_put(opp); 1180 freqs[index++] = freq++; 1181 } 1182 1183 return index; 1184 } 1185 1186 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1187 { 1188 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1189 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1190 struct msm_gpu *gpu = &adreno_gpu->base; 1191 1192 int ret = 0; 1193 1194 /* 1195 * The GMU handles its own frequency switching so build a list of 1196 * available frequencies to send during initialization 1197 */ 1198 ret = dev_pm_opp_of_add_table(gmu->dev); 1199 if (ret) { 1200 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1201 return ret; 1202 } 1203 1204 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1205 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1206 1207 /* 1208 * The GMU also handles GPU frequency switching so build a list 1209 * from the GPU OPP table 1210 */ 1211 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1212 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1213 1214 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1215 1216 /* Build the list of RPMh votes that we'll send to the GMU */ 1217 return a6xx_gmu_rpmh_votes_init(gmu); 1218 } 1219 1220 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1221 { 1222 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1223 1224 if (ret < 1) 1225 return ret; 1226 1227 gmu->nr_clocks = ret; 1228 1229 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1230 gmu->nr_clocks, "gmu"); 1231 1232 return 0; 1233 } 1234 1235 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1236 const char *name) 1237 { 1238 void __iomem *ret; 1239 struct resource *res = platform_get_resource_byname(pdev, 1240 IORESOURCE_MEM, name); 1241 1242 if (!res) { 1243 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1244 return ERR_PTR(-EINVAL); 1245 } 1246 1247 ret = ioremap(res->start, resource_size(res)); 1248 if (!ret) { 1249 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1250 return ERR_PTR(-EINVAL); 1251 } 1252 1253 return ret; 1254 } 1255 1256 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1257 const char *name, irq_handler_t handler) 1258 { 1259 int irq, ret; 1260 1261 irq = platform_get_irq_byname(pdev, name); 1262 1263 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1264 if (ret) { 1265 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1266 name, ret); 1267 return ret; 1268 } 1269 1270 disable_irq(irq); 1271 1272 return irq; 1273 } 1274 1275 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1276 { 1277 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1278 1279 if (!gmu->initialized) 1280 return; 1281 1282 pm_runtime_force_suspend(gmu->dev); 1283 1284 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1285 pm_runtime_disable(gmu->gxpd); 1286 dev_pm_domain_detach(gmu->gxpd, false); 1287 } 1288 1289 iounmap(gmu->mmio); 1290 gmu->mmio = NULL; 1291 1292 a6xx_gmu_memory_free(gmu); 1293 1294 free_irq(gmu->gmu_irq, gmu); 1295 free_irq(gmu->hfi_irq, gmu); 1296 1297 /* Drop reference taken in of_find_device_by_node */ 1298 put_device(gmu->dev); 1299 1300 gmu->initialized = false; 1301 } 1302 1303 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1304 { 1305 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1306 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1307 struct platform_device *pdev = of_find_device_by_node(node); 1308 int ret; 1309 1310 if (!pdev) 1311 return -ENODEV; 1312 1313 gmu->dev = &pdev->dev; 1314 1315 of_dma_configure(gmu->dev, node, true); 1316 1317 /* Fow now, don't do anything fancy until we get our feet under us */ 1318 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1319 1320 pm_runtime_enable(gmu->dev); 1321 1322 /* Get the list of clocks */ 1323 ret = a6xx_gmu_clocks_probe(gmu); 1324 if (ret) 1325 goto err_put_device; 1326 1327 ret = a6xx_gmu_memory_probe(gmu); 1328 if (ret) 1329 goto err_put_device; 1330 1331 if (!adreno_is_a640(adreno_gpu) && !adreno_is_a650(adreno_gpu)) { 1332 /* HFI v1, has sptprac */ 1333 gmu->legacy = true; 1334 1335 /* Allocate memory for the GMU debug region */ 1336 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1337 if (ret) 1338 goto err_memory; 1339 } 1340 1341 /* Allocate memory for for the HFI queues */ 1342 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1343 if (ret) 1344 goto err_memory; 1345 1346 /* Map the GMU registers */ 1347 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1348 if (IS_ERR(gmu->mmio)) { 1349 ret = PTR_ERR(gmu->mmio); 1350 goto err_memory; 1351 } 1352 1353 /* Get the HFI and GMU interrupts */ 1354 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1355 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1356 1357 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1358 goto err_mmio; 1359 1360 /* 1361 * Get a link to the GX power domain to reset the GPU in case of GMU 1362 * crash 1363 */ 1364 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1365 1366 /* Get the power levels for the GMU and GPU */ 1367 a6xx_gmu_pwrlevels_probe(gmu); 1368 1369 /* Set up the HFI queues */ 1370 a6xx_hfi_init(gmu); 1371 1372 gmu->initialized = true; 1373 1374 return 0; 1375 1376 err_mmio: 1377 iounmap(gmu->mmio); 1378 free_irq(gmu->gmu_irq, gmu); 1379 free_irq(gmu->hfi_irq, gmu); 1380 1381 ret = -ENODEV; 1382 1383 err_memory: 1384 a6xx_gmu_memory_free(gmu); 1385 err_put_device: 1386 /* Drop reference taken in of_find_device_by_node */ 1387 put_device(gmu->dev); 1388 1389 return ret; 1390 } 1391