1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_mmu.h" 15 16 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 17 { 18 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 19 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 20 struct msm_gpu *gpu = &adreno_gpu->base; 21 struct drm_device *dev = gpu->dev; 22 struct msm_drm_private *priv = dev->dev_private; 23 24 /* FIXME: add a banner here */ 25 gmu->hung = true; 26 27 /* Turn off the hangcheck timer while we are resetting */ 28 del_timer(&gpu->hangcheck_timer); 29 30 /* Queue the GPU handler because we need to treat this as a recovery */ 31 queue_work(priv->wq, &gpu->recover_work); 32 } 33 34 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 35 { 36 struct a6xx_gmu *gmu = data; 37 u32 status; 38 39 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 40 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 41 42 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 43 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 44 45 a6xx_gmu_fault(gmu); 46 } 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 49 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 52 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 53 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 54 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 59 { 60 struct a6xx_gmu *gmu = data; 61 u32 status; 62 63 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 64 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 65 66 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 67 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 68 69 a6xx_gmu_fault(gmu); 70 } 71 72 return IRQ_HANDLED; 73 } 74 75 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 76 { 77 u32 val; 78 79 /* This can be called from gpu state code so make sure GMU is valid */ 80 if (!gmu->initialized) 81 return false; 82 83 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 84 85 return !(val & 86 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 87 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 88 } 89 90 /* Check to see if the GX rail is still powered */ 91 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 92 { 93 u32 val; 94 95 /* This can be called from gpu state code so make sure GMU is valid */ 96 if (!gmu->initialized) 97 return false; 98 99 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 100 101 return !(val & 102 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 103 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 104 } 105 106 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 107 { 108 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 109 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 110 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 111 u32 perf_index; 112 unsigned long gpu_freq; 113 int ret = 0; 114 115 gpu_freq = dev_pm_opp_get_freq(opp); 116 117 if (gpu_freq == gmu->freq) 118 return; 119 120 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 121 if (gpu_freq == gmu->gpu_freqs[perf_index]) 122 break; 123 124 gmu->current_perf_index = perf_index; 125 gmu->freq = gmu->gpu_freqs[perf_index]; 126 127 /* 128 * This can get called from devfreq while the hardware is idle. Don't 129 * bring up the power if it isn't already active 130 */ 131 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 132 return; 133 134 if (!gmu->legacy) { 135 a6xx_hfi_set_freq(gmu, perf_index); 136 dev_pm_opp_set_bw(&gpu->pdev->dev, opp); 137 pm_runtime_put(gmu->dev); 138 return; 139 } 140 141 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 142 143 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 144 ((3 & 0xf) << 28) | perf_index); 145 146 /* 147 * Send an invalid index as a vote for the bus bandwidth and let the 148 * firmware decide on the right vote 149 */ 150 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 151 152 /* Set and clear the OOB for DCVS to trigger the GMU */ 153 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 154 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 155 156 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 157 if (ret) 158 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 159 160 dev_pm_opp_set_bw(&gpu->pdev->dev, opp); 161 pm_runtime_put(gmu->dev); 162 } 163 164 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 165 { 166 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 167 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 168 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 169 170 return gmu->freq; 171 } 172 173 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 174 { 175 u32 val; 176 int local = gmu->idle_level; 177 178 /* SPTP and IFPC both report as IFPC */ 179 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 180 local = GMU_IDLE_STATE_IFPC; 181 182 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 183 184 if (val == local) { 185 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 186 !a6xx_gmu_gx_is_on(gmu)) 187 return true; 188 } 189 190 return false; 191 } 192 193 /* Wait for the GMU to get to its most idle state */ 194 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 195 { 196 return spin_until(a6xx_gmu_check_idle_level(gmu)); 197 } 198 199 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 200 { 201 int ret; 202 u32 val; 203 u32 mask, reset_val; 204 205 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); 206 if (val <= 0x20010004) { 207 mask = 0xffffffff; 208 reset_val = 0xbabeface; 209 } else { 210 mask = 0x1ff; 211 reset_val = 0x100; 212 } 213 214 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 215 216 /* Set the log wptr index 217 * note: downstream saves the value in poweroff and restores it here 218 */ 219 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 220 221 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 222 223 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 224 (val & mask) == reset_val, 100, 10000); 225 226 if (ret) 227 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 228 229 return ret; 230 } 231 232 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 233 { 234 u32 val; 235 int ret; 236 237 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 238 239 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 240 val & 1, 100, 10000); 241 if (ret) 242 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 243 244 return ret; 245 } 246 247 /* Trigger a OOB (out of band) request to the GMU */ 248 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 249 { 250 int ret; 251 u32 val; 252 int request, ack; 253 const char *name; 254 255 switch (state) { 256 case GMU_OOB_GPU_SET: 257 if (gmu->legacy) { 258 request = GMU_OOB_GPU_SET_REQUEST; 259 ack = GMU_OOB_GPU_SET_ACK; 260 } else { 261 request = GMU_OOB_GPU_SET_REQUEST_NEW; 262 ack = GMU_OOB_GPU_SET_ACK_NEW; 263 } 264 name = "GPU_SET"; 265 break; 266 case GMU_OOB_BOOT_SLUMBER: 267 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 268 ack = GMU_OOB_BOOT_SLUMBER_ACK; 269 name = "BOOT_SLUMBER"; 270 break; 271 case GMU_OOB_DCVS_SET: 272 request = GMU_OOB_DCVS_REQUEST; 273 ack = GMU_OOB_DCVS_ACK; 274 name = "GPU_DCVS"; 275 break; 276 default: 277 return -EINVAL; 278 } 279 280 /* Trigger the equested OOB operation */ 281 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 282 283 /* Wait for the acknowledge interrupt */ 284 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 285 val & (1 << ack), 100, 10000); 286 287 if (ret) 288 DRM_DEV_ERROR(gmu->dev, 289 "Timeout waiting for GMU OOB set %s: 0x%x\n", 290 name, 291 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 292 293 /* Clear the acknowledge interrupt */ 294 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 295 296 return ret; 297 } 298 299 /* Clear a pending OOB state in the GMU */ 300 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 301 { 302 if (!gmu->legacy) { 303 WARN_ON(state != GMU_OOB_GPU_SET); 304 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 305 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 306 return; 307 } 308 309 switch (state) { 310 case GMU_OOB_GPU_SET: 311 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 312 1 << GMU_OOB_GPU_SET_CLEAR); 313 break; 314 case GMU_OOB_BOOT_SLUMBER: 315 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 316 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 317 break; 318 case GMU_OOB_DCVS_SET: 319 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 320 1 << GMU_OOB_DCVS_CLEAR); 321 break; 322 } 323 } 324 325 /* Enable CPU control of SPTP power power collapse */ 326 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 327 { 328 int ret; 329 u32 val; 330 331 if (!gmu->legacy) 332 return 0; 333 334 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 335 336 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 337 (val & 0x38) == 0x28, 1, 100); 338 339 if (ret) { 340 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 341 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 342 } 343 344 return 0; 345 } 346 347 /* Disable CPU control of SPTP power power collapse */ 348 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 349 { 350 u32 val; 351 int ret; 352 353 if (!gmu->legacy) 354 return; 355 356 /* Make sure retention is on */ 357 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 358 359 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 360 361 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 362 (val & 0x04), 100, 10000); 363 364 if (ret) 365 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 366 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 367 } 368 369 /* Let the GMU know we are starting a boot sequence */ 370 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 371 { 372 u32 vote; 373 374 /* Let the GMU know we are getting ready for boot */ 375 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 376 377 /* Choose the "default" power level as the highest available */ 378 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 379 380 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 381 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 382 383 /* Let the GMU know the boot sequence has started */ 384 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 385 } 386 387 /* Let the GMU know that we are about to go into slumber */ 388 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 389 { 390 int ret; 391 392 /* Disable the power counter so the GMU isn't busy */ 393 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 394 395 /* Disable SPTP_PC if the CPU is responsible for it */ 396 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 397 a6xx_sptprac_disable(gmu); 398 399 if (!gmu->legacy) { 400 ret = a6xx_hfi_send_prep_slumber(gmu); 401 goto out; 402 } 403 404 /* Tell the GMU to get ready to slumber */ 405 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 406 407 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 408 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 409 410 if (!ret) { 411 /* Check to see if the GMU really did slumber */ 412 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 413 != 0x0f) { 414 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 415 ret = -ETIMEDOUT; 416 } 417 } 418 419 out: 420 /* Put fence into allow mode */ 421 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 422 return ret; 423 } 424 425 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 426 { 427 int ret; 428 u32 val; 429 430 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 431 /* Wait for the register to finish posting */ 432 wmb(); 433 434 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 435 val & (1 << 1), 100, 10000); 436 if (ret) { 437 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 438 return ret; 439 } 440 441 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 442 !val, 100, 10000); 443 444 if (ret) { 445 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 446 return ret; 447 } 448 449 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 450 451 /* Set up CX GMU counter 0 to count busy ticks */ 452 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 453 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 454 455 /* Enable the power counter */ 456 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 457 return 0; 458 } 459 460 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 461 { 462 int ret; 463 u32 val; 464 465 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 466 467 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 468 val, val & (1 << 16), 100, 10000); 469 if (ret) 470 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 471 472 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 473 } 474 475 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 476 { 477 return msm_writel(value, ptr + (offset << 2)); 478 } 479 480 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 481 const char *name); 482 483 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 484 { 485 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 486 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 487 struct platform_device *pdev = to_platform_device(gmu->dev); 488 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 489 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 490 uint32_t pdc_address_offset; 491 492 if (!pdcptr || !seqptr) 493 goto err; 494 495 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) 496 pdc_address_offset = 0x30090; 497 else if (adreno_is_a650(adreno_gpu)) 498 pdc_address_offset = 0x300a0; 499 else 500 pdc_address_offset = 0x30080; 501 502 /* Disable SDE clock gating */ 503 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 504 505 /* Setup RSC PDC handshake for sleep and wakeup */ 506 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 507 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 508 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 509 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 510 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 511 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 512 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 513 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 514 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 515 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 516 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 517 518 /* Load RSC sequencer uCode for sleep and wakeup */ 519 if (adreno_is_a650(adreno_gpu)) { 520 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); 521 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); 522 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); 523 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); 524 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); 525 } else { 526 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 527 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 528 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 529 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 530 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 531 } 532 533 /* Load PDC sequencer uCode for power up and power down sequence */ 534 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 535 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 536 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 537 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 538 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 539 540 /* Set TCS commands used by PDC sequence for low power modes */ 541 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 542 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 544 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 546 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 547 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 548 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 549 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 550 551 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 554 555 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 558 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 559 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 560 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 561 562 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 564 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) 565 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 566 else 567 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 569 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 570 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 571 572 /* Setup GPU PDC */ 573 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 574 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 575 576 /* ensure no writes happen before the uCode is fully written */ 577 wmb(); 578 579 err: 580 if (!IS_ERR_OR_NULL(pdcptr)) 581 iounmap(pdcptr); 582 if (!IS_ERR_OR_NULL(seqptr)) 583 iounmap(seqptr); 584 } 585 586 /* 587 * The lowest 16 bits of this value are the number of XO clock cycles for main 588 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 589 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 590 */ 591 592 #define GMU_PWR_COL_HYST 0x000a1680 593 594 /* Set up the idle state for the GMU */ 595 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 596 { 597 /* Disable GMU WB/RB buffer */ 598 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 599 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 600 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 601 602 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 603 604 switch (gmu->idle_level) { 605 case GMU_IDLE_STATE_IFPC: 606 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 607 GMU_PWR_COL_HYST); 608 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 609 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 610 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 611 /* Fall through */ 612 case GMU_IDLE_STATE_SPTP: 613 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 614 GMU_PWR_COL_HYST); 615 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 616 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 617 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 618 } 619 620 /* Enable RPMh GPU client */ 621 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 622 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 623 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 624 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 625 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 626 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 627 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 628 } 629 630 struct block_header { 631 u32 addr; 632 u32 size; 633 u32 type; 634 u32 value; 635 u32 data[]; 636 }; 637 638 /* this should be a general kernel helper */ 639 static int in_range(u32 addr, u32 start, u32 size) 640 { 641 return addr >= start && addr < start + size; 642 } 643 644 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 645 { 646 if (!in_range(blk->addr, bo->iova, bo->size)) 647 return false; 648 649 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 650 return true; 651 } 652 653 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 654 { 655 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 656 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 657 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 658 const struct block_header *blk; 659 u32 reg_offset; 660 661 u32 itcm_base = 0x00000000; 662 u32 dtcm_base = 0x00040000; 663 664 if (adreno_is_a650(adreno_gpu)) 665 dtcm_base = 0x10004000; 666 667 if (gmu->legacy) { 668 /* Sanity check the size of the firmware that was loaded */ 669 if (fw_image->size > 0x8000) { 670 DRM_DEV_ERROR(gmu->dev, 671 "GMU firmware is bigger than the available region\n"); 672 return -EINVAL; 673 } 674 675 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 676 (u32*) fw_image->data, fw_image->size); 677 return 0; 678 } 679 680 681 for (blk = (const struct block_header *) fw_image->data; 682 (const u8*) blk < fw_image->data + fw_image->size; 683 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 684 if (blk->size == 0) 685 continue; 686 687 if (in_range(blk->addr, itcm_base, SZ_16K)) { 688 reg_offset = (blk->addr - itcm_base) >> 2; 689 gmu_write_bulk(gmu, 690 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 691 blk->data, blk->size); 692 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 693 reg_offset = (blk->addr - dtcm_base) >> 2; 694 gmu_write_bulk(gmu, 695 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 696 blk->data, blk->size); 697 } else if (!fw_block_mem(&gmu->icache, blk) && 698 !fw_block_mem(&gmu->dcache, blk) && 699 !fw_block_mem(&gmu->dummy, blk)) { 700 DRM_DEV_ERROR(gmu->dev, 701 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 702 blk->addr, blk->size, blk->data[0]); 703 } 704 } 705 706 return 0; 707 } 708 709 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 710 { 711 static bool rpmh_init; 712 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 713 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 714 int ret; 715 u32 chipid; 716 717 if (adreno_is_a650(adreno_gpu)) 718 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 719 720 if (state == GMU_WARM_BOOT) { 721 ret = a6xx_rpmh_start(gmu); 722 if (ret) 723 return ret; 724 } else { 725 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 726 "GMU firmware is not loaded\n")) 727 return -ENOENT; 728 729 /* Turn on register retention */ 730 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 731 732 /* We only need to load the RPMh microcode once */ 733 if (!rpmh_init) { 734 a6xx_gmu_rpmh_init(gmu); 735 rpmh_init = true; 736 } else { 737 ret = a6xx_rpmh_start(gmu); 738 if (ret) 739 return ret; 740 } 741 742 ret = a6xx_gmu_fw_load(gmu); 743 if (ret) 744 return ret; 745 } 746 747 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 748 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 749 750 /* Write the iova of the HFI table */ 751 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 752 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 753 754 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 755 (1 << 31) | (0xa << 18) | (0xa0)); 756 757 chipid = adreno_gpu->rev.core << 24; 758 chipid |= adreno_gpu->rev.major << 16; 759 chipid |= adreno_gpu->rev.minor << 12; 760 chipid |= adreno_gpu->rev.patchid << 8; 761 762 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 763 764 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 765 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 766 767 /* Set up the lowest idle level on the GMU */ 768 a6xx_gmu_power_config(gmu); 769 770 ret = a6xx_gmu_start(gmu); 771 if (ret) 772 return ret; 773 774 if (gmu->legacy) { 775 ret = a6xx_gmu_gfx_rail_on(gmu); 776 if (ret) 777 return ret; 778 } 779 780 /* Enable SPTP_PC if the CPU is responsible for it */ 781 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 782 ret = a6xx_sptprac_enable(gmu); 783 if (ret) 784 return ret; 785 } 786 787 ret = a6xx_gmu_hfi_start(gmu); 788 if (ret) 789 return ret; 790 791 /* FIXME: Do we need this wmb() here? */ 792 wmb(); 793 794 return 0; 795 } 796 797 #define A6XX_HFI_IRQ_MASK \ 798 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 799 800 #define A6XX_GMU_IRQ_MASK \ 801 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 802 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 803 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 804 805 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 806 { 807 disable_irq(gmu->gmu_irq); 808 disable_irq(gmu->hfi_irq); 809 810 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 811 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 812 } 813 814 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 815 { 816 u32 val; 817 818 /* Make sure there are no outstanding RPMh votes */ 819 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 820 (val & 1), 100, 10000); 821 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 822 (val & 1), 100, 10000); 823 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 824 (val & 1), 100, 10000); 825 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 826 (val & 1), 100, 1000); 827 } 828 829 /* Force the GMU off in case it isn't responsive */ 830 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 831 { 832 /* Flush all the queues */ 833 a6xx_hfi_stop(gmu); 834 835 /* Stop the interrupts */ 836 a6xx_gmu_irq_disable(gmu); 837 838 /* Force off SPTP in case the GMU is managing it */ 839 a6xx_sptprac_disable(gmu); 840 841 /* Make sure there are no outstanding RPMh votes */ 842 a6xx_gmu_rpmh_off(gmu); 843 } 844 845 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 846 { 847 struct dev_pm_opp *gpu_opp; 848 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 849 850 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 851 if (IS_ERR_OR_NULL(gpu_opp)) 852 return; 853 854 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ 855 a6xx_gmu_set_freq(gpu, gpu_opp); 856 dev_pm_opp_put(gpu_opp); 857 } 858 859 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 860 { 861 struct dev_pm_opp *gpu_opp; 862 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 863 864 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 865 if (IS_ERR_OR_NULL(gpu_opp)) 866 return; 867 868 dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp); 869 dev_pm_opp_put(gpu_opp); 870 } 871 872 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 873 { 874 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 875 struct msm_gpu *gpu = &adreno_gpu->base; 876 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 877 int status, ret; 878 879 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 880 return 0; 881 882 gmu->hung = false; 883 884 /* Turn on the resources */ 885 pm_runtime_get_sync(gmu->dev); 886 887 /* 888 * "enable" the GX power domain which won't actually do anything but it 889 * will make sure that the refcounting is correct in case we need to 890 * bring down the GX after a GMU failure 891 */ 892 if (!IS_ERR_OR_NULL(gmu->gxpd)) 893 pm_runtime_get_sync(gmu->gxpd); 894 895 /* Use a known rate to bring up the GMU */ 896 clk_set_rate(gmu->core_clk, 200000000); 897 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 898 if (ret) { 899 pm_runtime_put(gmu->gxpd); 900 pm_runtime_put(gmu->dev); 901 return ret; 902 } 903 904 /* Set the bus quota to a reasonable value for boot */ 905 a6xx_gmu_set_initial_bw(gpu, gmu); 906 907 /* Enable the GMU interrupt */ 908 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 909 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 910 enable_irq(gmu->gmu_irq); 911 912 /* Check to see if we are doing a cold or warm boot */ 913 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 914 GMU_WARM_BOOT : GMU_COLD_BOOT; 915 916 /* 917 * Warm boot path does not work on newer GPUs 918 * Presumably this is because icache/dcache regions must be restored 919 */ 920 if (!gmu->legacy) 921 status = GMU_COLD_BOOT; 922 923 ret = a6xx_gmu_fw_start(gmu, status); 924 if (ret) 925 goto out; 926 927 ret = a6xx_hfi_start(gmu, status); 928 if (ret) 929 goto out; 930 931 /* 932 * Turn on the GMU firmware fault interrupt after we know the boot 933 * sequence is successful 934 */ 935 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 936 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 937 enable_irq(gmu->hfi_irq); 938 939 /* Set the GPU to the current freq */ 940 a6xx_gmu_set_initial_freq(gpu, gmu); 941 942 out: 943 /* On failure, shut down the GMU to leave it in a good state */ 944 if (ret) { 945 disable_irq(gmu->gmu_irq); 946 a6xx_rpmh_stop(gmu); 947 pm_runtime_put(gmu->gxpd); 948 pm_runtime_put(gmu->dev); 949 } 950 951 return ret; 952 } 953 954 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 955 { 956 u32 reg; 957 958 if (!gmu->initialized) 959 return true; 960 961 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 962 963 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 964 return false; 965 966 return true; 967 } 968 969 #define GBIF_CLIENT_HALT_MASK BIT(0) 970 #define GBIF_ARB_HALT_MASK BIT(1) 971 972 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 973 { 974 struct msm_gpu *gpu = &adreno_gpu->base; 975 976 if (!a6xx_has_gbif(adreno_gpu)) { 977 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 978 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 979 0xf) == 0xf); 980 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 981 982 return; 983 } 984 985 /* Halt new client requests on GBIF */ 986 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 987 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 988 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 989 990 /* Halt all AXI requests on GBIF */ 991 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 992 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 993 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 994 995 /* The GBIF halt needs to be explicitly cleared */ 996 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 997 } 998 999 /* Gracefully try to shut down the GMU and by extension the GPU */ 1000 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 1001 { 1002 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1003 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1004 u32 val; 1005 1006 /* 1007 * The GMU may still be in slumber unless the GPU started so check and 1008 * skip putting it back into slumber if so 1009 */ 1010 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 1011 1012 if (val != 0xf) { 1013 int ret = a6xx_gmu_wait_for_idle(gmu); 1014 1015 /* If the GMU isn't responding assume it is hung */ 1016 if (ret) { 1017 a6xx_gmu_force_off(gmu); 1018 return; 1019 } 1020 1021 a6xx_bus_clear_pending_transactions(adreno_gpu); 1022 1023 /* tell the GMU we want to slumber */ 1024 a6xx_gmu_notify_slumber(gmu); 1025 1026 ret = gmu_poll_timeout(gmu, 1027 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1028 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1029 100, 10000); 1030 1031 /* 1032 * Let the user know we failed to slumber but don't worry too 1033 * much because we are powering down anyway 1034 */ 1035 1036 if (ret) 1037 DRM_DEV_ERROR(gmu->dev, 1038 "Unable to slumber GMU: status = 0%x/0%x\n", 1039 gmu_read(gmu, 1040 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1041 gmu_read(gmu, 1042 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1043 } 1044 1045 /* Turn off HFI */ 1046 a6xx_hfi_stop(gmu); 1047 1048 /* Stop the interrupts and mask the hardware */ 1049 a6xx_gmu_irq_disable(gmu); 1050 1051 /* Tell RPMh to power off the GPU */ 1052 a6xx_rpmh_stop(gmu); 1053 } 1054 1055 1056 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1057 { 1058 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1059 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1060 1061 if (!pm_runtime_active(gmu->dev)) 1062 return 0; 1063 1064 /* 1065 * Force the GMU off if we detected a hang, otherwise try to shut it 1066 * down gracefully 1067 */ 1068 if (gmu->hung) 1069 a6xx_gmu_force_off(gmu); 1070 else 1071 a6xx_gmu_shutdown(gmu); 1072 1073 /* Remove the bus vote */ 1074 dev_pm_opp_set_bw(&gpu->pdev->dev, NULL); 1075 1076 /* 1077 * Make sure the GX domain is off before turning off the GMU (CX) 1078 * domain. Usually the GMU does this but only if the shutdown sequence 1079 * was successful 1080 */ 1081 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1082 pm_runtime_put_sync(gmu->gxpd); 1083 1084 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1085 1086 pm_runtime_put_sync(gmu->dev); 1087 1088 return 0; 1089 } 1090 1091 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1092 { 1093 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 1094 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 1095 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false); 1096 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false); 1097 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false); 1098 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false); 1099 1100 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1101 msm_gem_address_space_put(gmu->aspace); 1102 } 1103 1104 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1105 size_t size, u64 iova) 1106 { 1107 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1108 struct drm_device *dev = a6xx_gpu->base.base.dev; 1109 uint32_t flags = MSM_BO_WC; 1110 u64 range_start, range_end; 1111 int ret; 1112 1113 size = PAGE_ALIGN(size); 1114 if (!iova) { 1115 /* no fixed address - use GMU's uncached range */ 1116 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1117 range_end = 0x80000000; 1118 } else { 1119 /* range for fixed address */ 1120 range_start = iova; 1121 range_end = iova + size; 1122 /* use IOMMU_PRIV for icache/dcache */ 1123 flags |= MSM_BO_MAP_PRIV; 1124 } 1125 1126 bo->obj = msm_gem_new(dev, size, flags); 1127 if (IS_ERR(bo->obj)) 1128 return PTR_ERR(bo->obj); 1129 1130 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1131 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 1132 if (ret) { 1133 drm_gem_object_put(bo->obj); 1134 return ret; 1135 } 1136 1137 bo->virt = msm_gem_get_vaddr(bo->obj); 1138 bo->size = size; 1139 1140 return 0; 1141 } 1142 1143 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1144 { 1145 struct iommu_domain *domain; 1146 struct msm_mmu *mmu; 1147 1148 domain = iommu_domain_alloc(&platform_bus_type); 1149 if (!domain) 1150 return -ENODEV; 1151 1152 mmu = msm_iommu_new(gmu->dev, domain); 1153 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); 1154 if (IS_ERR(gmu->aspace)) { 1155 iommu_domain_free(domain); 1156 return PTR_ERR(gmu->aspace); 1157 } 1158 1159 return 0; 1160 } 1161 1162 /* Return the 'arc-level' for the given frequency */ 1163 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1164 unsigned long freq) 1165 { 1166 struct dev_pm_opp *opp; 1167 unsigned int val; 1168 1169 if (!freq) 1170 return 0; 1171 1172 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1173 if (IS_ERR(opp)) 1174 return 0; 1175 1176 val = dev_pm_opp_get_level(opp); 1177 1178 dev_pm_opp_put(opp); 1179 1180 return val; 1181 } 1182 1183 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1184 unsigned long *freqs, int freqs_count, const char *id) 1185 { 1186 int i, j; 1187 const u16 *pri, *sec; 1188 size_t pri_count, sec_count; 1189 1190 pri = cmd_db_read_aux_data(id, &pri_count); 1191 if (IS_ERR(pri)) 1192 return PTR_ERR(pri); 1193 /* 1194 * The data comes back as an array of unsigned shorts so adjust the 1195 * count accordingly 1196 */ 1197 pri_count >>= 1; 1198 if (!pri_count) 1199 return -EINVAL; 1200 1201 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1202 if (IS_ERR(sec)) 1203 return PTR_ERR(sec); 1204 1205 sec_count >>= 1; 1206 if (!sec_count) 1207 return -EINVAL; 1208 1209 /* Construct a vote for each frequency */ 1210 for (i = 0; i < freqs_count; i++) { 1211 u8 pindex = 0, sindex = 0; 1212 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1213 1214 /* Get the primary index that matches the arc level */ 1215 for (j = 0; j < pri_count; j++) { 1216 if (pri[j] >= level) { 1217 pindex = j; 1218 break; 1219 } 1220 } 1221 1222 if (j == pri_count) { 1223 DRM_DEV_ERROR(dev, 1224 "Level %u not found in the RPMh list\n", 1225 level); 1226 DRM_DEV_ERROR(dev, "Available levels:\n"); 1227 for (j = 0; j < pri_count; j++) 1228 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1229 1230 return -EINVAL; 1231 } 1232 1233 /* 1234 * Look for a level in in the secondary list that matches. If 1235 * nothing fits, use the maximum non zero vote 1236 */ 1237 1238 for (j = 0; j < sec_count; j++) { 1239 if (sec[j] >= level) { 1240 sindex = j; 1241 break; 1242 } else if (sec[j]) { 1243 sindex = j; 1244 } 1245 } 1246 1247 /* Construct the vote */ 1248 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1249 (sindex << 8) | pindex; 1250 } 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1257 * to construct the list of votes on the CPU and send it over. Query the RPMh 1258 * voltage levels and build the votes 1259 */ 1260 1261 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1262 { 1263 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1264 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1265 struct msm_gpu *gpu = &adreno_gpu->base; 1266 int ret; 1267 1268 /* Build the GX votes */ 1269 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1270 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1271 1272 /* Build the CX votes */ 1273 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1274 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1275 1276 return ret; 1277 } 1278 1279 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1280 u32 size) 1281 { 1282 int count = dev_pm_opp_get_opp_count(dev); 1283 struct dev_pm_opp *opp; 1284 int i, index = 0; 1285 unsigned long freq = 1; 1286 1287 /* 1288 * The OPP table doesn't contain the "off" frequency level so we need to 1289 * add 1 to the table size to account for it 1290 */ 1291 1292 if (WARN(count + 1 > size, 1293 "The GMU frequency table is being truncated\n")) 1294 count = size - 1; 1295 1296 /* Set the "off" frequency */ 1297 freqs[index++] = 0; 1298 1299 for (i = 0; i < count; i++) { 1300 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1301 if (IS_ERR(opp)) 1302 break; 1303 1304 dev_pm_opp_put(opp); 1305 freqs[index++] = freq++; 1306 } 1307 1308 return index; 1309 } 1310 1311 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1312 { 1313 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1314 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1315 struct msm_gpu *gpu = &adreno_gpu->base; 1316 1317 int ret = 0; 1318 1319 /* 1320 * The GMU handles its own frequency switching so build a list of 1321 * available frequencies to send during initialization 1322 */ 1323 ret = dev_pm_opp_of_add_table(gmu->dev); 1324 if (ret) { 1325 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1326 return ret; 1327 } 1328 1329 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1330 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1331 1332 /* 1333 * The GMU also handles GPU frequency switching so build a list 1334 * from the GPU OPP table 1335 */ 1336 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1337 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1338 1339 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1340 1341 /* Build the list of RPMh votes that we'll send to the GMU */ 1342 return a6xx_gmu_rpmh_votes_init(gmu); 1343 } 1344 1345 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1346 { 1347 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1348 1349 if (ret < 1) 1350 return ret; 1351 1352 gmu->nr_clocks = ret; 1353 1354 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1355 gmu->nr_clocks, "gmu"); 1356 1357 return 0; 1358 } 1359 1360 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1361 const char *name) 1362 { 1363 void __iomem *ret; 1364 struct resource *res = platform_get_resource_byname(pdev, 1365 IORESOURCE_MEM, name); 1366 1367 if (!res) { 1368 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1369 return ERR_PTR(-EINVAL); 1370 } 1371 1372 ret = ioremap(res->start, resource_size(res)); 1373 if (!ret) { 1374 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1375 return ERR_PTR(-EINVAL); 1376 } 1377 1378 return ret; 1379 } 1380 1381 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1382 const char *name, irq_handler_t handler) 1383 { 1384 int irq, ret; 1385 1386 irq = platform_get_irq_byname(pdev, name); 1387 1388 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1389 if (ret) { 1390 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1391 name, ret); 1392 return ret; 1393 } 1394 1395 disable_irq(irq); 1396 1397 return irq; 1398 } 1399 1400 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1401 { 1402 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1403 struct platform_device *pdev = to_platform_device(gmu->dev); 1404 1405 if (!gmu->initialized) 1406 return; 1407 1408 pm_runtime_force_suspend(gmu->dev); 1409 1410 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1411 pm_runtime_disable(gmu->gxpd); 1412 dev_pm_domain_detach(gmu->gxpd, false); 1413 } 1414 1415 iounmap(gmu->mmio); 1416 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1417 iounmap(gmu->rscc); 1418 gmu->mmio = NULL; 1419 gmu->rscc = NULL; 1420 1421 a6xx_gmu_memory_free(gmu); 1422 1423 free_irq(gmu->gmu_irq, gmu); 1424 free_irq(gmu->hfi_irq, gmu); 1425 1426 /* Drop reference taken in of_find_device_by_node */ 1427 put_device(gmu->dev); 1428 1429 gmu->initialized = false; 1430 } 1431 1432 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1433 { 1434 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1435 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1436 struct platform_device *pdev = of_find_device_by_node(node); 1437 int ret; 1438 1439 if (!pdev) 1440 return -ENODEV; 1441 1442 gmu->dev = &pdev->dev; 1443 1444 of_dma_configure(gmu->dev, node, true); 1445 1446 /* Fow now, don't do anything fancy until we get our feet under us */ 1447 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1448 1449 pm_runtime_enable(gmu->dev); 1450 1451 /* Get the list of clocks */ 1452 ret = a6xx_gmu_clocks_probe(gmu); 1453 if (ret) 1454 goto err_put_device; 1455 1456 ret = a6xx_gmu_memory_probe(gmu); 1457 if (ret) 1458 goto err_put_device; 1459 1460 /* Allocate memory for the GMU dummy page */ 1461 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); 1462 if (ret) 1463 goto err_memory; 1464 1465 if (adreno_is_a650(adreno_gpu)) { 1466 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1467 SZ_16M - SZ_16K, 0x04000); 1468 if (ret) 1469 goto err_memory; 1470 } else if (adreno_is_a640(adreno_gpu)) { 1471 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1472 SZ_256K - SZ_16K, 0x04000); 1473 if (ret) 1474 goto err_memory; 1475 1476 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1477 SZ_256K - SZ_16K, 0x44000); 1478 if (ret) 1479 goto err_memory; 1480 } else { 1481 /* HFI v1, has sptprac */ 1482 gmu->legacy = true; 1483 1484 /* Allocate memory for the GMU debug region */ 1485 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1486 if (ret) 1487 goto err_memory; 1488 } 1489 1490 /* Allocate memory for for the HFI queues */ 1491 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1492 if (ret) 1493 goto err_memory; 1494 1495 /* Allocate memory for the GMU log region */ 1496 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0); 1497 if (ret) 1498 goto err_memory; 1499 1500 /* Map the GMU registers */ 1501 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1502 if (IS_ERR(gmu->mmio)) { 1503 ret = PTR_ERR(gmu->mmio); 1504 goto err_memory; 1505 } 1506 1507 if (adreno_is_a650(adreno_gpu)) { 1508 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1509 if (IS_ERR(gmu->rscc)) 1510 goto err_mmio; 1511 } else { 1512 gmu->rscc = gmu->mmio + 0x23000; 1513 } 1514 1515 /* Get the HFI and GMU interrupts */ 1516 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1517 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1518 1519 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1520 goto err_mmio; 1521 1522 /* 1523 * Get a link to the GX power domain to reset the GPU in case of GMU 1524 * crash 1525 */ 1526 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1527 1528 /* Get the power levels for the GMU and GPU */ 1529 a6xx_gmu_pwrlevels_probe(gmu); 1530 1531 /* Set up the HFI queues */ 1532 a6xx_hfi_init(gmu); 1533 1534 gmu->initialized = true; 1535 1536 return 0; 1537 1538 err_mmio: 1539 iounmap(gmu->mmio); 1540 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1541 iounmap(gmu->rscc); 1542 free_irq(gmu->gmu_irq, gmu); 1543 free_irq(gmu->hfi_irq, gmu); 1544 1545 ret = -ENODEV; 1546 1547 err_memory: 1548 a6xx_gmu_memory_free(gmu); 1549 err_put_device: 1550 /* Drop reference taken in of_find_device_by_node */ 1551 put_device(gmu->dev); 1552 1553 return ret; 1554 } 1555