1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/pm_domain.h> 7 #include <linux/pm_opp.h> 8 #include <soc/qcom/cmd-db.h> 9 #include <drm/drm_gem.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 #include "msm_gem.h" 14 #include "msm_mmu.h" 15 16 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 17 { 18 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 19 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 20 struct msm_gpu *gpu = &adreno_gpu->base; 21 struct drm_device *dev = gpu->dev; 22 struct msm_drm_private *priv = dev->dev_private; 23 24 /* FIXME: add a banner here */ 25 gmu->hung = true; 26 27 /* Turn off the hangcheck timer while we are resetting */ 28 del_timer(&gpu->hangcheck_timer); 29 30 /* Queue the GPU handler because we need to treat this as a recovery */ 31 queue_work(priv->wq, &gpu->recover_work); 32 } 33 34 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 35 { 36 struct a6xx_gmu *gmu = data; 37 u32 status; 38 39 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 40 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 41 42 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 43 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 44 45 a6xx_gmu_fault(gmu); 46 } 47 48 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 49 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 50 51 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 52 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 53 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 54 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 59 { 60 struct a6xx_gmu *gmu = data; 61 u32 status; 62 63 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 64 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 65 66 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 67 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 68 69 a6xx_gmu_fault(gmu); 70 } 71 72 return IRQ_HANDLED; 73 } 74 75 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 76 { 77 u32 val; 78 79 /* This can be called from gpu state code so make sure GMU is valid */ 80 if (!gmu->initialized) 81 return false; 82 83 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 84 85 return !(val & 86 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 87 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 88 } 89 90 /* Check to see if the GX rail is still powered */ 91 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 92 { 93 u32 val; 94 95 /* This can be called from gpu state code so make sure GMU is valid */ 96 if (!gmu->initialized) 97 return false; 98 99 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 100 101 return !(val & 102 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 103 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 104 } 105 106 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 107 { 108 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 109 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 110 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 111 u32 perf_index; 112 unsigned long gpu_freq; 113 int ret = 0; 114 115 gpu_freq = dev_pm_opp_get_freq(opp); 116 117 if (gpu_freq == gmu->freq) 118 return; 119 120 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 121 if (gpu_freq == gmu->gpu_freqs[perf_index]) 122 break; 123 124 gmu->current_perf_index = perf_index; 125 gmu->freq = gmu->gpu_freqs[perf_index]; 126 127 /* 128 * This can get called from devfreq while the hardware is idle. Don't 129 * bring up the power if it isn't already active 130 */ 131 if (pm_runtime_get_if_in_use(gmu->dev) == 0) 132 return; 133 134 if (!gmu->legacy) { 135 a6xx_hfi_set_freq(gmu, perf_index); 136 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 137 pm_runtime_put(gmu->dev); 138 return; 139 } 140 141 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 142 143 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 144 ((3 & 0xf) << 28) | perf_index); 145 146 /* 147 * Send an invalid index as a vote for the bus bandwidth and let the 148 * firmware decide on the right vote 149 */ 150 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 151 152 /* Set and clear the OOB for DCVS to trigger the GMU */ 153 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 154 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 155 156 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 157 if (ret) 158 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 159 160 /* 161 * Eventually we will want to scale the path vote with the frequency but 162 * for now leave it at max so that the performance is nominal. 163 */ 164 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 165 pm_runtime_put(gmu->dev); 166 } 167 168 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 169 { 170 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 171 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 172 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 173 174 return gmu->freq; 175 } 176 177 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 178 { 179 u32 val; 180 int local = gmu->idle_level; 181 182 /* SPTP and IFPC both report as IFPC */ 183 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 184 local = GMU_IDLE_STATE_IFPC; 185 186 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 187 188 if (val == local) { 189 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 190 !a6xx_gmu_gx_is_on(gmu)) 191 return true; 192 } 193 194 return false; 195 } 196 197 /* Wait for the GMU to get to its most idle state */ 198 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 199 { 200 return spin_until(a6xx_gmu_check_idle_level(gmu)); 201 } 202 203 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 204 { 205 int ret; 206 u32 val; 207 208 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 209 210 /* Set the log wptr index 211 * note: downstream saves the value in poweroff and restores it here 212 */ 213 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 214 215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 216 217 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 218 val == 0xbabeface, 100, 10000); 219 220 if (ret) 221 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 222 223 return ret; 224 } 225 226 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 227 { 228 u32 val; 229 int ret; 230 231 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 232 233 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 234 val & 1, 100, 10000); 235 if (ret) 236 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 237 238 return ret; 239 } 240 241 /* Trigger a OOB (out of band) request to the GMU */ 242 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 243 { 244 int ret; 245 u32 val; 246 int request, ack; 247 const char *name; 248 249 switch (state) { 250 case GMU_OOB_GPU_SET: 251 if (gmu->legacy) { 252 request = GMU_OOB_GPU_SET_REQUEST; 253 ack = GMU_OOB_GPU_SET_ACK; 254 } else { 255 request = GMU_OOB_GPU_SET_REQUEST_NEW; 256 ack = GMU_OOB_GPU_SET_ACK_NEW; 257 } 258 name = "GPU_SET"; 259 break; 260 case GMU_OOB_BOOT_SLUMBER: 261 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 262 ack = GMU_OOB_BOOT_SLUMBER_ACK; 263 name = "BOOT_SLUMBER"; 264 break; 265 case GMU_OOB_DCVS_SET: 266 request = GMU_OOB_DCVS_REQUEST; 267 ack = GMU_OOB_DCVS_ACK; 268 name = "GPU_DCVS"; 269 break; 270 default: 271 return -EINVAL; 272 } 273 274 /* Trigger the equested OOB operation */ 275 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 276 277 /* Wait for the acknowledge interrupt */ 278 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 279 val & (1 << ack), 100, 10000); 280 281 if (ret) 282 DRM_DEV_ERROR(gmu->dev, 283 "Timeout waiting for GMU OOB set %s: 0x%x\n", 284 name, 285 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 286 287 /* Clear the acknowledge interrupt */ 288 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 289 290 return ret; 291 } 292 293 /* Clear a pending OOB state in the GMU */ 294 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 295 { 296 if (!gmu->legacy) { 297 WARN_ON(state != GMU_OOB_GPU_SET); 298 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 299 1 << GMU_OOB_GPU_SET_CLEAR_NEW); 300 return; 301 } 302 303 switch (state) { 304 case GMU_OOB_GPU_SET: 305 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 306 1 << GMU_OOB_GPU_SET_CLEAR); 307 break; 308 case GMU_OOB_BOOT_SLUMBER: 309 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 310 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 311 break; 312 case GMU_OOB_DCVS_SET: 313 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 314 1 << GMU_OOB_DCVS_CLEAR); 315 break; 316 } 317 } 318 319 /* Enable CPU control of SPTP power power collapse */ 320 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 321 { 322 int ret; 323 u32 val; 324 325 if (!gmu->legacy) 326 return 0; 327 328 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 329 330 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 331 (val & 0x38) == 0x28, 1, 100); 332 333 if (ret) { 334 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 335 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 336 } 337 338 return 0; 339 } 340 341 /* Disable CPU control of SPTP power power collapse */ 342 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 343 { 344 u32 val; 345 int ret; 346 347 if (!gmu->legacy) 348 return; 349 350 /* Make sure retention is on */ 351 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 352 353 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 354 355 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 356 (val & 0x04), 100, 10000); 357 358 if (ret) 359 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 360 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 361 } 362 363 /* Let the GMU know we are starting a boot sequence */ 364 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 365 { 366 u32 vote; 367 368 /* Let the GMU know we are getting ready for boot */ 369 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 370 371 /* Choose the "default" power level as the highest available */ 372 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 373 374 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 375 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 376 377 /* Let the GMU know the boot sequence has started */ 378 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 379 } 380 381 /* Let the GMU know that we are about to go into slumber */ 382 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 383 { 384 int ret; 385 386 /* Disable the power counter so the GMU isn't busy */ 387 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 388 389 /* Disable SPTP_PC if the CPU is responsible for it */ 390 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 391 a6xx_sptprac_disable(gmu); 392 393 if (!gmu->legacy) { 394 ret = a6xx_hfi_send_prep_slumber(gmu); 395 goto out; 396 } 397 398 /* Tell the GMU to get ready to slumber */ 399 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 400 401 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 402 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 403 404 if (!ret) { 405 /* Check to see if the GMU really did slumber */ 406 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 407 != 0x0f) { 408 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 409 ret = -ETIMEDOUT; 410 } 411 } 412 413 out: 414 /* Put fence into allow mode */ 415 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 416 return ret; 417 } 418 419 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 420 { 421 int ret; 422 u32 val; 423 424 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 425 /* Wait for the register to finish posting */ 426 wmb(); 427 428 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 429 val & (1 << 1), 100, 10000); 430 if (ret) { 431 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 432 return ret; 433 } 434 435 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 436 !val, 100, 10000); 437 438 if (ret) { 439 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 440 return ret; 441 } 442 443 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 444 445 /* Set up CX GMU counter 0 to count busy ticks */ 446 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 447 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 448 449 /* Enable the power counter */ 450 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 451 return 0; 452 } 453 454 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 455 { 456 int ret; 457 u32 val; 458 459 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 460 461 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 462 val, val & (1 << 16), 100, 10000); 463 if (ret) 464 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 465 466 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 467 } 468 469 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 470 { 471 return msm_writel(value, ptr + (offset << 2)); 472 } 473 474 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 475 const char *name); 476 477 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 478 { 479 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 480 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 481 struct platform_device *pdev = to_platform_device(gmu->dev); 482 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 483 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 484 uint32_t pdc_address_offset; 485 486 if (!pdcptr || !seqptr) 487 goto err; 488 489 if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) 490 pdc_address_offset = 0x30090; 491 else if (adreno_is_a650(adreno_gpu)) 492 pdc_address_offset = 0x300a0; 493 else 494 pdc_address_offset = 0x30080; 495 496 /* Disable SDE clock gating */ 497 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 498 499 /* Setup RSC PDC handshake for sleep and wakeup */ 500 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 501 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 502 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 503 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 504 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 505 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 506 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 507 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 508 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 509 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 510 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 511 512 /* Load RSC sequencer uCode for sleep and wakeup */ 513 if (adreno_is_a650(adreno_gpu)) { 514 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); 515 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); 516 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); 517 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); 518 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); 519 } else { 520 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 521 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 522 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 523 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 524 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 525 } 526 527 /* Load PDC sequencer uCode for power up and power down sequence */ 528 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 529 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 530 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 531 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 532 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 533 534 /* Set TCS commands used by PDC sequence for low power modes */ 535 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 536 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 537 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 538 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 539 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 540 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 541 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 542 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 543 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 544 545 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 546 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 547 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 548 549 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 550 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 551 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 552 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 553 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 554 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 555 556 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 557 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 558 if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) 559 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 560 else 561 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 562 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 563 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 564 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 565 566 /* Setup GPU PDC */ 567 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 568 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 569 570 /* ensure no writes happen before the uCode is fully written */ 571 wmb(); 572 573 err: 574 if (!IS_ERR_OR_NULL(pdcptr)) 575 iounmap(pdcptr); 576 if (!IS_ERR_OR_NULL(seqptr)) 577 iounmap(seqptr); 578 } 579 580 /* 581 * The lowest 16 bits of this value are the number of XO clock cycles for main 582 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 583 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 584 */ 585 586 #define GMU_PWR_COL_HYST 0x000a1680 587 588 /* Set up the idle state for the GMU */ 589 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 590 { 591 /* Disable GMU WB/RB buffer */ 592 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 593 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 594 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 595 596 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 597 598 switch (gmu->idle_level) { 599 case GMU_IDLE_STATE_IFPC: 600 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 601 GMU_PWR_COL_HYST); 602 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 603 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 604 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 605 /* Fall through */ 606 case GMU_IDLE_STATE_SPTP: 607 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 608 GMU_PWR_COL_HYST); 609 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 610 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 611 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 612 } 613 614 /* Enable RPMh GPU client */ 615 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 616 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 617 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 618 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 619 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 620 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 621 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 622 } 623 624 struct block_header { 625 u32 addr; 626 u32 size; 627 u32 type; 628 u32 value; 629 u32 data[]; 630 }; 631 632 /* this should be a general kernel helper */ 633 static int in_range(u32 addr, u32 start, u32 size) 634 { 635 return addr >= start && addr < start + size; 636 } 637 638 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 639 { 640 if (!in_range(blk->addr, bo->iova, bo->size)) 641 return false; 642 643 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 644 return true; 645 } 646 647 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 648 { 649 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 650 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 651 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 652 const struct block_header *blk; 653 u32 reg_offset; 654 655 u32 itcm_base = 0x00000000; 656 u32 dtcm_base = 0x00040000; 657 658 if (adreno_is_a650(adreno_gpu)) 659 dtcm_base = 0x10004000; 660 661 if (gmu->legacy) { 662 /* Sanity check the size of the firmware that was loaded */ 663 if (fw_image->size > 0x8000) { 664 DRM_DEV_ERROR(gmu->dev, 665 "GMU firmware is bigger than the available region\n"); 666 return -EINVAL; 667 } 668 669 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 670 (u32*) fw_image->data, fw_image->size); 671 return 0; 672 } 673 674 675 for (blk = (const struct block_header *) fw_image->data; 676 (const u8*) blk < fw_image->data + fw_image->size; 677 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 678 if (blk->size == 0) 679 continue; 680 681 if (in_range(blk->addr, itcm_base, SZ_16K)) { 682 reg_offset = (blk->addr - itcm_base) >> 2; 683 gmu_write_bulk(gmu, 684 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 685 blk->data, blk->size); 686 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 687 reg_offset = (blk->addr - dtcm_base) >> 2; 688 gmu_write_bulk(gmu, 689 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 690 blk->data, blk->size); 691 } else if (!fw_block_mem(&gmu->icache, blk) && 692 !fw_block_mem(&gmu->dcache, blk) && 693 !fw_block_mem(&gmu->dummy, blk)) { 694 DRM_DEV_ERROR(gmu->dev, 695 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 696 blk->addr, blk->size, blk->data[0]); 697 } 698 } 699 700 return 0; 701 } 702 703 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 704 { 705 static bool rpmh_init; 706 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 707 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 708 int ret; 709 u32 chipid; 710 711 if (adreno_is_a650(adreno_gpu)) 712 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 713 714 if (state == GMU_WARM_BOOT) { 715 ret = a6xx_rpmh_start(gmu); 716 if (ret) 717 return ret; 718 } else { 719 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 720 "GMU firmware is not loaded\n")) 721 return -ENOENT; 722 723 /* Turn on register retention */ 724 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 725 726 /* We only need to load the RPMh microcode once */ 727 if (!rpmh_init) { 728 a6xx_gmu_rpmh_init(gmu); 729 rpmh_init = true; 730 } else { 731 ret = a6xx_rpmh_start(gmu); 732 if (ret) 733 return ret; 734 } 735 736 ret = a6xx_gmu_fw_load(gmu); 737 if (ret) 738 return ret; 739 } 740 741 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 742 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 743 744 /* Write the iova of the HFI table */ 745 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 746 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 747 748 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 749 (1 << 31) | (0xa << 18) | (0xa0)); 750 751 chipid = adreno_gpu->rev.core << 24; 752 chipid |= adreno_gpu->rev.major << 16; 753 chipid |= adreno_gpu->rev.minor << 12; 754 chipid |= adreno_gpu->rev.patchid << 8; 755 756 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 757 758 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 759 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 760 761 /* Set up the lowest idle level on the GMU */ 762 a6xx_gmu_power_config(gmu); 763 764 ret = a6xx_gmu_start(gmu); 765 if (ret) 766 return ret; 767 768 if (gmu->legacy) { 769 ret = a6xx_gmu_gfx_rail_on(gmu); 770 if (ret) 771 return ret; 772 } 773 774 /* Enable SPTP_PC if the CPU is responsible for it */ 775 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 776 ret = a6xx_sptprac_enable(gmu); 777 if (ret) 778 return ret; 779 } 780 781 ret = a6xx_gmu_hfi_start(gmu); 782 if (ret) 783 return ret; 784 785 /* FIXME: Do we need this wmb() here? */ 786 wmb(); 787 788 return 0; 789 } 790 791 #define A6XX_HFI_IRQ_MASK \ 792 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 793 794 #define A6XX_GMU_IRQ_MASK \ 795 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 796 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 797 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 798 799 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 800 { 801 disable_irq(gmu->gmu_irq); 802 disable_irq(gmu->hfi_irq); 803 804 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 805 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 806 } 807 808 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 809 { 810 u32 val; 811 812 /* Make sure there are no outstanding RPMh votes */ 813 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 814 (val & 1), 100, 10000); 815 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 816 (val & 1), 100, 10000); 817 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 818 (val & 1), 100, 10000); 819 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 820 (val & 1), 100, 1000); 821 } 822 823 /* Force the GMU off in case it isn't responsive */ 824 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 825 { 826 /* Flush all the queues */ 827 a6xx_hfi_stop(gmu); 828 829 /* Stop the interrupts */ 830 a6xx_gmu_irq_disable(gmu); 831 832 /* Force off SPTP in case the GMU is managing it */ 833 a6xx_sptprac_disable(gmu); 834 835 /* Make sure there are no outstanding RPMh votes */ 836 a6xx_gmu_rpmh_off(gmu); 837 } 838 839 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 840 { 841 struct dev_pm_opp *gpu_opp; 842 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 843 844 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 845 if (IS_ERR_OR_NULL(gpu_opp)) 846 return; 847 848 a6xx_gmu_set_freq(gpu, gpu_opp); 849 dev_pm_opp_put(gpu_opp); 850 } 851 852 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 853 { 854 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 855 struct msm_gpu *gpu = &adreno_gpu->base; 856 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 857 int status, ret; 858 859 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 860 return 0; 861 862 gmu->hung = false; 863 864 /* Turn on the resources */ 865 pm_runtime_get_sync(gmu->dev); 866 867 /* Use a known rate to bring up the GMU */ 868 clk_set_rate(gmu->core_clk, 200000000); 869 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 870 if (ret) { 871 pm_runtime_put(gmu->dev); 872 return ret; 873 } 874 875 /* Set the bus quota to a reasonable value for boot */ 876 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 877 878 /* Enable the GMU interrupt */ 879 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 880 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 881 enable_irq(gmu->gmu_irq); 882 883 /* Check to see if we are doing a cold or warm boot */ 884 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 885 GMU_WARM_BOOT : GMU_COLD_BOOT; 886 887 /* 888 * Warm boot path does not work on newer GPUs 889 * Presumably this is because icache/dcache regions must be restored 890 */ 891 if (!gmu->legacy) 892 status = GMU_COLD_BOOT; 893 894 ret = a6xx_gmu_fw_start(gmu, status); 895 if (ret) 896 goto out; 897 898 ret = a6xx_hfi_start(gmu, status); 899 if (ret) 900 goto out; 901 902 /* 903 * Turn on the GMU firmware fault interrupt after we know the boot 904 * sequence is successful 905 */ 906 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 907 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 908 enable_irq(gmu->hfi_irq); 909 910 /* Set the GPU to the current freq */ 911 a6xx_gmu_set_initial_freq(gpu, gmu); 912 913 /* 914 * "enable" the GX power domain which won't actually do anything but it 915 * will make sure that the refcounting is correct in case we need to 916 * bring down the GX after a GMU failure 917 */ 918 if (!IS_ERR_OR_NULL(gmu->gxpd)) 919 pm_runtime_get(gmu->gxpd); 920 921 out: 922 /* On failure, shut down the GMU to leave it in a good state */ 923 if (ret) { 924 disable_irq(gmu->gmu_irq); 925 a6xx_rpmh_stop(gmu); 926 pm_runtime_put(gmu->dev); 927 } 928 929 return ret; 930 } 931 932 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 933 { 934 u32 reg; 935 936 if (!gmu->initialized) 937 return true; 938 939 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 940 941 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 942 return false; 943 944 return true; 945 } 946 947 #define GBIF_CLIENT_HALT_MASK BIT(0) 948 #define GBIF_ARB_HALT_MASK BIT(1) 949 950 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 951 { 952 struct msm_gpu *gpu = &adreno_gpu->base; 953 954 if (!a6xx_has_gbif(adreno_gpu)) { 955 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 956 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 957 0xf) == 0xf); 958 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 959 960 return; 961 } 962 963 /* Halt new client requests on GBIF */ 964 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 965 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 966 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 967 968 /* Halt all AXI requests on GBIF */ 969 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 970 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 971 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 972 973 /* The GBIF halt needs to be explicitly cleared */ 974 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 975 } 976 977 /* Gracefully try to shut down the GMU and by extension the GPU */ 978 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 979 { 980 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 981 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 982 u32 val; 983 984 /* 985 * The GMU may still be in slumber unless the GPU started so check and 986 * skip putting it back into slumber if so 987 */ 988 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 989 990 if (val != 0xf) { 991 int ret = a6xx_gmu_wait_for_idle(gmu); 992 993 /* If the GMU isn't responding assume it is hung */ 994 if (ret) { 995 a6xx_gmu_force_off(gmu); 996 return; 997 } 998 999 a6xx_bus_clear_pending_transactions(adreno_gpu); 1000 1001 /* tell the GMU we want to slumber */ 1002 a6xx_gmu_notify_slumber(gmu); 1003 1004 ret = gmu_poll_timeout(gmu, 1005 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1006 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1007 100, 10000); 1008 1009 /* 1010 * Let the user know we failed to slumber but don't worry too 1011 * much because we are powering down anyway 1012 */ 1013 1014 if (ret) 1015 DRM_DEV_ERROR(gmu->dev, 1016 "Unable to slumber GMU: status = 0%x/0%x\n", 1017 gmu_read(gmu, 1018 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1019 gmu_read(gmu, 1020 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1021 } 1022 1023 /* Turn off HFI */ 1024 a6xx_hfi_stop(gmu); 1025 1026 /* Stop the interrupts and mask the hardware */ 1027 a6xx_gmu_irq_disable(gmu); 1028 1029 /* Tell RPMh to power off the GPU */ 1030 a6xx_rpmh_stop(gmu); 1031 } 1032 1033 1034 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1035 { 1036 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1037 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1038 1039 if (!pm_runtime_active(gmu->dev)) 1040 return 0; 1041 1042 /* 1043 * Force the GMU off if we detected a hang, otherwise try to shut it 1044 * down gracefully 1045 */ 1046 if (gmu->hung) 1047 a6xx_gmu_force_off(gmu); 1048 else 1049 a6xx_gmu_shutdown(gmu); 1050 1051 /* Remove the bus vote */ 1052 icc_set_bw(gpu->icc_path, 0, 0); 1053 1054 /* 1055 * Make sure the GX domain is off before turning off the GMU (CX) 1056 * domain. Usually the GMU does this but only if the shutdown sequence 1057 * was successful 1058 */ 1059 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1060 pm_runtime_put_sync(gmu->gxpd); 1061 1062 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1063 1064 pm_runtime_put_sync(gmu->dev); 1065 1066 return 0; 1067 } 1068 1069 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1070 { 1071 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace, false); 1072 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace, false); 1073 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace, false); 1074 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace, false); 1075 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace, false); 1076 msm_gem_kernel_put(gmu->log.obj, gmu->aspace, false); 1077 1078 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1079 msm_gem_address_space_put(gmu->aspace); 1080 } 1081 1082 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1083 size_t size, u64 iova) 1084 { 1085 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1086 struct drm_device *dev = a6xx_gpu->base.base.dev; 1087 uint32_t flags = MSM_BO_WC; 1088 u64 range_start, range_end; 1089 int ret; 1090 1091 size = PAGE_ALIGN(size); 1092 if (!iova) { 1093 /* no fixed address - use GMU's uncached range */ 1094 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1095 range_end = 0x80000000; 1096 } else { 1097 /* range for fixed address */ 1098 range_start = iova; 1099 range_end = iova + size; 1100 /* use IOMMU_PRIV for icache/dcache */ 1101 flags |= MSM_BO_MAP_PRIV; 1102 } 1103 1104 bo->obj = msm_gem_new(dev, size, flags); 1105 if (IS_ERR(bo->obj)) 1106 return PTR_ERR(bo->obj); 1107 1108 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1109 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT); 1110 if (ret) { 1111 drm_gem_object_put(bo->obj); 1112 return ret; 1113 } 1114 1115 bo->virt = msm_gem_get_vaddr(bo->obj); 1116 bo->size = size; 1117 1118 return 0; 1119 } 1120 1121 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1122 { 1123 struct iommu_domain *domain; 1124 struct msm_mmu *mmu; 1125 1126 domain = iommu_domain_alloc(&platform_bus_type); 1127 if (!domain) 1128 return -ENODEV; 1129 1130 mmu = msm_iommu_new(gmu->dev, domain); 1131 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); 1132 if (IS_ERR(gmu->aspace)) { 1133 iommu_domain_free(domain); 1134 return PTR_ERR(gmu->aspace); 1135 } 1136 1137 return 0; 1138 } 1139 1140 /* Return the 'arc-level' for the given frequency */ 1141 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1142 unsigned long freq) 1143 { 1144 struct dev_pm_opp *opp; 1145 unsigned int val; 1146 1147 if (!freq) 1148 return 0; 1149 1150 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1151 if (IS_ERR(opp)) 1152 return 0; 1153 1154 val = dev_pm_opp_get_level(opp); 1155 1156 dev_pm_opp_put(opp); 1157 1158 return val; 1159 } 1160 1161 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1162 unsigned long *freqs, int freqs_count, const char *id) 1163 { 1164 int i, j; 1165 const u16 *pri, *sec; 1166 size_t pri_count, sec_count; 1167 1168 pri = cmd_db_read_aux_data(id, &pri_count); 1169 if (IS_ERR(pri)) 1170 return PTR_ERR(pri); 1171 /* 1172 * The data comes back as an array of unsigned shorts so adjust the 1173 * count accordingly 1174 */ 1175 pri_count >>= 1; 1176 if (!pri_count) 1177 return -EINVAL; 1178 1179 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1180 if (IS_ERR(sec)) 1181 return PTR_ERR(sec); 1182 1183 sec_count >>= 1; 1184 if (!sec_count) 1185 return -EINVAL; 1186 1187 /* Construct a vote for each frequency */ 1188 for (i = 0; i < freqs_count; i++) { 1189 u8 pindex = 0, sindex = 0; 1190 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1191 1192 /* Get the primary index that matches the arc level */ 1193 for (j = 0; j < pri_count; j++) { 1194 if (pri[j] >= level) { 1195 pindex = j; 1196 break; 1197 } 1198 } 1199 1200 if (j == pri_count) { 1201 DRM_DEV_ERROR(dev, 1202 "Level %u not found in the RPMh list\n", 1203 level); 1204 DRM_DEV_ERROR(dev, "Available levels:\n"); 1205 for (j = 0; j < pri_count; j++) 1206 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1207 1208 return -EINVAL; 1209 } 1210 1211 /* 1212 * Look for a level in in the secondary list that matches. If 1213 * nothing fits, use the maximum non zero vote 1214 */ 1215 1216 for (j = 0; j < sec_count; j++) { 1217 if (sec[j] >= level) { 1218 sindex = j; 1219 break; 1220 } else if (sec[j]) { 1221 sindex = j; 1222 } 1223 } 1224 1225 /* Construct the vote */ 1226 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1227 (sindex << 8) | pindex; 1228 } 1229 1230 return 0; 1231 } 1232 1233 /* 1234 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1235 * to construct the list of votes on the CPU and send it over. Query the RPMh 1236 * voltage levels and build the votes 1237 */ 1238 1239 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1240 { 1241 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1242 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1243 struct msm_gpu *gpu = &adreno_gpu->base; 1244 int ret; 1245 1246 /* Build the GX votes */ 1247 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1248 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1249 1250 /* Build the CX votes */ 1251 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1252 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1253 1254 return ret; 1255 } 1256 1257 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1258 u32 size) 1259 { 1260 int count = dev_pm_opp_get_opp_count(dev); 1261 struct dev_pm_opp *opp; 1262 int i, index = 0; 1263 unsigned long freq = 1; 1264 1265 /* 1266 * The OPP table doesn't contain the "off" frequency level so we need to 1267 * add 1 to the table size to account for it 1268 */ 1269 1270 if (WARN(count + 1 > size, 1271 "The GMU frequency table is being truncated\n")) 1272 count = size - 1; 1273 1274 /* Set the "off" frequency */ 1275 freqs[index++] = 0; 1276 1277 for (i = 0; i < count; i++) { 1278 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1279 if (IS_ERR(opp)) 1280 break; 1281 1282 dev_pm_opp_put(opp); 1283 freqs[index++] = freq++; 1284 } 1285 1286 return index; 1287 } 1288 1289 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1290 { 1291 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1292 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1293 struct msm_gpu *gpu = &adreno_gpu->base; 1294 1295 int ret = 0; 1296 1297 /* 1298 * The GMU handles its own frequency switching so build a list of 1299 * available frequencies to send during initialization 1300 */ 1301 ret = dev_pm_opp_of_add_table(gmu->dev); 1302 if (ret) { 1303 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1304 return ret; 1305 } 1306 1307 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1308 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1309 1310 /* 1311 * The GMU also handles GPU frequency switching so build a list 1312 * from the GPU OPP table 1313 */ 1314 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1315 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1316 1317 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1318 1319 /* Build the list of RPMh votes that we'll send to the GMU */ 1320 return a6xx_gmu_rpmh_votes_init(gmu); 1321 } 1322 1323 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1324 { 1325 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1326 1327 if (ret < 1) 1328 return ret; 1329 1330 gmu->nr_clocks = ret; 1331 1332 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1333 gmu->nr_clocks, "gmu"); 1334 1335 return 0; 1336 } 1337 1338 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1339 const char *name) 1340 { 1341 void __iomem *ret; 1342 struct resource *res = platform_get_resource_byname(pdev, 1343 IORESOURCE_MEM, name); 1344 1345 if (!res) { 1346 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1347 return ERR_PTR(-EINVAL); 1348 } 1349 1350 ret = ioremap(res->start, resource_size(res)); 1351 if (!ret) { 1352 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1353 return ERR_PTR(-EINVAL); 1354 } 1355 1356 return ret; 1357 } 1358 1359 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1360 const char *name, irq_handler_t handler) 1361 { 1362 int irq, ret; 1363 1364 irq = platform_get_irq_byname(pdev, name); 1365 1366 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1367 if (ret) { 1368 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1369 name, ret); 1370 return ret; 1371 } 1372 1373 disable_irq(irq); 1374 1375 return irq; 1376 } 1377 1378 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1379 { 1380 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1381 struct platform_device *pdev = to_platform_device(gmu->dev); 1382 1383 if (!gmu->initialized) 1384 return; 1385 1386 pm_runtime_force_suspend(gmu->dev); 1387 1388 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1389 pm_runtime_disable(gmu->gxpd); 1390 dev_pm_domain_detach(gmu->gxpd, false); 1391 } 1392 1393 iounmap(gmu->mmio); 1394 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1395 iounmap(gmu->rscc); 1396 gmu->mmio = NULL; 1397 gmu->rscc = NULL; 1398 1399 a6xx_gmu_memory_free(gmu); 1400 1401 free_irq(gmu->gmu_irq, gmu); 1402 free_irq(gmu->hfi_irq, gmu); 1403 1404 /* Drop reference taken in of_find_device_by_node */ 1405 put_device(gmu->dev); 1406 1407 gmu->initialized = false; 1408 } 1409 1410 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1411 { 1412 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1413 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1414 struct platform_device *pdev = of_find_device_by_node(node); 1415 int ret; 1416 1417 if (!pdev) 1418 return -ENODEV; 1419 1420 gmu->dev = &pdev->dev; 1421 1422 of_dma_configure(gmu->dev, node, true); 1423 1424 /* Fow now, don't do anything fancy until we get our feet under us */ 1425 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1426 1427 pm_runtime_enable(gmu->dev); 1428 1429 /* Get the list of clocks */ 1430 ret = a6xx_gmu_clocks_probe(gmu); 1431 if (ret) 1432 goto err_put_device; 1433 1434 ret = a6xx_gmu_memory_probe(gmu); 1435 if (ret) 1436 goto err_put_device; 1437 1438 /* Allocate memory for the GMU dummy page */ 1439 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); 1440 if (ret) 1441 goto err_memory; 1442 1443 if (adreno_is_a650(adreno_gpu)) { 1444 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1445 SZ_16M - SZ_16K, 0x04000); 1446 if (ret) 1447 goto err_memory; 1448 } else if (adreno_is_a640(adreno_gpu)) { 1449 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1450 SZ_256K - SZ_16K, 0x04000); 1451 if (ret) 1452 goto err_memory; 1453 1454 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1455 SZ_256K - SZ_16K, 0x44000); 1456 if (ret) 1457 goto err_memory; 1458 } else { 1459 /* HFI v1, has sptprac */ 1460 gmu->legacy = true; 1461 1462 /* Allocate memory for the GMU debug region */ 1463 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0); 1464 if (ret) 1465 goto err_memory; 1466 } 1467 1468 /* Allocate memory for for the HFI queues */ 1469 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0); 1470 if (ret) 1471 goto err_memory; 1472 1473 /* Allocate memory for the GMU log region */ 1474 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0); 1475 if (ret) 1476 goto err_memory; 1477 1478 /* Map the GMU registers */ 1479 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1480 if (IS_ERR(gmu->mmio)) { 1481 ret = PTR_ERR(gmu->mmio); 1482 goto err_memory; 1483 } 1484 1485 if (adreno_is_a650(adreno_gpu)) { 1486 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1487 if (IS_ERR(gmu->rscc)) 1488 goto err_mmio; 1489 } else { 1490 gmu->rscc = gmu->mmio + 0x23000; 1491 } 1492 1493 /* Get the HFI and GMU interrupts */ 1494 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1495 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1496 1497 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1498 goto err_mmio; 1499 1500 /* 1501 * Get a link to the GX power domain to reset the GPU in case of GMU 1502 * crash 1503 */ 1504 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1505 1506 /* Get the power levels for the GMU and GPU */ 1507 a6xx_gmu_pwrlevels_probe(gmu); 1508 1509 /* Set up the HFI queues */ 1510 a6xx_hfi_init(gmu); 1511 1512 gmu->initialized = true; 1513 1514 return 0; 1515 1516 err_mmio: 1517 iounmap(gmu->mmio); 1518 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1519 iounmap(gmu->rscc); 1520 free_irq(gmu->gmu_irq, gmu); 1521 free_irq(gmu->hfi_irq, gmu); 1522 1523 ret = -ENODEV; 1524 1525 err_memory: 1526 a6xx_gmu_memory_free(gmu); 1527 err_put_device: 1528 /* Drop reference taken in of_find_device_by_node */ 1529 put_device(gmu->dev); 1530 1531 return ret; 1532 } 1533