1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/dma-mapping.h> 6 #include <linux/interconnect.h> 7 #include <linux/pm_domain.h> 8 #include <linux/pm_opp.h> 9 #include <soc/qcom/cmd-db.h> 10 11 #include "a6xx_gpu.h" 12 #include "a6xx_gmu.xml.h" 13 14 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 15 { 16 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 17 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 18 struct msm_gpu *gpu = &adreno_gpu->base; 19 struct drm_device *dev = gpu->dev; 20 struct msm_drm_private *priv = dev->dev_private; 21 22 /* FIXME: add a banner here */ 23 gmu->hung = true; 24 25 /* Turn off the hangcheck timer while we are resetting */ 26 del_timer(&gpu->hangcheck_timer); 27 28 /* Queue the GPU handler because we need to treat this as a recovery */ 29 queue_work(priv->wq, &gpu->recover_work); 30 } 31 32 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 33 { 34 struct a6xx_gmu *gmu = data; 35 u32 status; 36 37 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 38 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 39 40 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 41 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 42 43 a6xx_gmu_fault(gmu); 44 } 45 46 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 47 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 48 49 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 50 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 51 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 52 53 return IRQ_HANDLED; 54 } 55 56 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 57 { 58 struct a6xx_gmu *gmu = data; 59 u32 status; 60 61 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 62 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 63 64 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 65 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 66 67 a6xx_gmu_fault(gmu); 68 } 69 70 return IRQ_HANDLED; 71 } 72 73 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 74 { 75 u32 val; 76 77 /* This can be called from gpu state code so make sure GMU is valid */ 78 if (!gmu->initialized) 79 return false; 80 81 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 82 83 return !(val & 84 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 85 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 86 } 87 88 /* Check to see if the GX rail is still powered */ 89 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 90 { 91 u32 val; 92 93 /* This can be called from gpu state code so make sure GMU is valid */ 94 if (!gmu->initialized) 95 return false; 96 97 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 98 99 return !(val & 100 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 101 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 102 } 103 104 static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) 105 { 106 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 107 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 108 struct msm_gpu *gpu = &adreno_gpu->base; 109 int ret; 110 111 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 112 113 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 114 ((3 & 0xf) << 28) | index); 115 116 /* 117 * Send an invalid index as a vote for the bus bandwidth and let the 118 * firmware decide on the right vote 119 */ 120 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 121 122 /* Set and clear the OOB for DCVS to trigger the GMU */ 123 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 124 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 125 126 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 127 if (ret) 128 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 129 130 gmu->freq = gmu->gpu_freqs[index]; 131 132 /* 133 * Eventually we will want to scale the path vote with the frequency but 134 * for now leave it at max so that the performance is nominal. 135 */ 136 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); 137 } 138 139 void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq) 140 { 141 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 142 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 143 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 144 u32 perf_index = 0; 145 146 if (freq == gmu->freq) 147 return; 148 149 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 150 if (freq == gmu->gpu_freqs[perf_index]) 151 break; 152 153 gmu->current_perf_index = perf_index; 154 155 __a6xx_gmu_set_freq(gmu, perf_index); 156 } 157 158 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 159 { 160 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 161 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 162 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 163 164 return gmu->freq; 165 } 166 167 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 168 { 169 u32 val; 170 int local = gmu->idle_level; 171 172 /* SPTP and IFPC both report as IFPC */ 173 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 174 local = GMU_IDLE_STATE_IFPC; 175 176 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 177 178 if (val == local) { 179 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 180 !a6xx_gmu_gx_is_on(gmu)) 181 return true; 182 } 183 184 return false; 185 } 186 187 /* Wait for the GMU to get to its most idle state */ 188 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 189 { 190 return spin_until(a6xx_gmu_check_idle_level(gmu)); 191 } 192 193 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 194 { 195 int ret; 196 u32 val; 197 198 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 199 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 200 201 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 202 val == 0xbabeface, 100, 10000); 203 204 if (ret) 205 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 206 207 return ret; 208 } 209 210 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 211 { 212 u32 val; 213 int ret; 214 215 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 216 217 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 218 val & 1, 100, 10000); 219 if (ret) 220 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 221 222 return ret; 223 } 224 225 /* Trigger a OOB (out of band) request to the GMU */ 226 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 227 { 228 int ret; 229 u32 val; 230 int request, ack; 231 const char *name; 232 233 switch (state) { 234 case GMU_OOB_GPU_SET: 235 request = GMU_OOB_GPU_SET_REQUEST; 236 ack = GMU_OOB_GPU_SET_ACK; 237 name = "GPU_SET"; 238 break; 239 case GMU_OOB_BOOT_SLUMBER: 240 request = GMU_OOB_BOOT_SLUMBER_REQUEST; 241 ack = GMU_OOB_BOOT_SLUMBER_ACK; 242 name = "BOOT_SLUMBER"; 243 break; 244 case GMU_OOB_DCVS_SET: 245 request = GMU_OOB_DCVS_REQUEST; 246 ack = GMU_OOB_DCVS_ACK; 247 name = "GPU_DCVS"; 248 break; 249 default: 250 return -EINVAL; 251 } 252 253 /* Trigger the equested OOB operation */ 254 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 255 256 /* Wait for the acknowledge interrupt */ 257 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 258 val & (1 << ack), 100, 10000); 259 260 if (ret) 261 DRM_DEV_ERROR(gmu->dev, 262 "Timeout waiting for GMU OOB set %s: 0x%x\n", 263 name, 264 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 265 266 /* Clear the acknowledge interrupt */ 267 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 268 269 return ret; 270 } 271 272 /* Clear a pending OOB state in the GMU */ 273 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 274 { 275 switch (state) { 276 case GMU_OOB_GPU_SET: 277 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 278 1 << GMU_OOB_GPU_SET_CLEAR); 279 break; 280 case GMU_OOB_BOOT_SLUMBER: 281 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 282 1 << GMU_OOB_BOOT_SLUMBER_CLEAR); 283 break; 284 case GMU_OOB_DCVS_SET: 285 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 286 1 << GMU_OOB_DCVS_CLEAR); 287 break; 288 } 289 } 290 291 /* Enable CPU control of SPTP power power collapse */ 292 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 293 { 294 int ret; 295 u32 val; 296 297 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 298 299 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 300 (val & 0x38) == 0x28, 1, 100); 301 302 if (ret) { 303 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 304 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 305 } 306 307 return 0; 308 } 309 310 /* Disable CPU control of SPTP power power collapse */ 311 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 312 { 313 u32 val; 314 int ret; 315 316 /* Make sure retention is on */ 317 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 318 319 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 320 321 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 322 (val & 0x04), 100, 10000); 323 324 if (ret) 325 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 326 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 327 } 328 329 /* Let the GMU know we are starting a boot sequence */ 330 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 331 { 332 u32 vote; 333 334 /* Let the GMU know we are getting ready for boot */ 335 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 336 337 /* Choose the "default" power level as the highest available */ 338 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 339 340 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 341 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 342 343 /* Let the GMU know the boot sequence has started */ 344 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 345 } 346 347 /* Let the GMU know that we are about to go into slumber */ 348 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 349 { 350 int ret; 351 352 /* Disable the power counter so the GMU isn't busy */ 353 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 354 355 /* Disable SPTP_PC if the CPU is responsible for it */ 356 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 357 a6xx_sptprac_disable(gmu); 358 359 /* Tell the GMU to get ready to slumber */ 360 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 361 362 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 363 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 364 365 if (!ret) { 366 /* Check to see if the GMU really did slumber */ 367 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 368 != 0x0f) { 369 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 370 ret = -ETIMEDOUT; 371 } 372 } 373 374 /* Put fence into allow mode */ 375 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 376 return ret; 377 } 378 379 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 380 { 381 int ret; 382 u32 val; 383 384 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 385 /* Wait for the register to finish posting */ 386 wmb(); 387 388 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 389 val & (1 << 1), 100, 10000); 390 if (ret) { 391 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 392 return ret; 393 } 394 395 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 396 !val, 100, 10000); 397 398 if (ret) { 399 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 400 return ret; 401 } 402 403 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 404 405 /* Set up CX GMU counter 0 to count busy ticks */ 406 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 407 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20); 408 409 /* Enable the power counter */ 410 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 411 return 0; 412 } 413 414 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 415 { 416 int ret; 417 u32 val; 418 419 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 420 421 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 422 val, val & (1 << 16), 100, 10000); 423 if (ret) 424 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 425 426 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 427 } 428 429 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 430 { 431 return msm_writel(value, ptr + (offset << 2)); 432 } 433 434 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 435 const char *name); 436 437 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 438 { 439 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 440 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 441 struct platform_device *pdev = to_platform_device(gmu->dev); 442 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 443 void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 444 445 if (!pdcptr || !seqptr) 446 goto err; 447 448 /* Disable SDE clock gating */ 449 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 450 451 /* Setup RSC PDC handshake for sleep and wakeup */ 452 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 453 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 454 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 455 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 456 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 457 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 458 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 459 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 460 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 461 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 462 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 463 464 /* Load RSC sequencer uCode for sleep and wakeup */ 465 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 466 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 467 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 468 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 469 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 470 471 /* Load PDC sequencer uCode for power up and power down sequence */ 472 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 473 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 474 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 475 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 476 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 477 478 /* Set TCS commands used by PDC sequence for low power modes */ 479 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 480 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 481 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 482 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 483 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 484 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 485 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 486 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 487 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 488 489 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 490 if (adreno_is_a618(adreno_gpu)) 491 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090); 492 else 493 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); 494 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 495 496 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 497 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 498 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 499 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 500 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 501 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 502 503 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 504 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 505 if (adreno_is_a618(adreno_gpu)) 506 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 507 else 508 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 509 510 511 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 512 if (adreno_is_a618(adreno_gpu)) 513 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090); 514 else 515 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); 516 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 517 518 /* Setup GPU PDC */ 519 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 520 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 521 522 /* ensure no writes happen before the uCode is fully written */ 523 wmb(); 524 525 err: 526 if (!IS_ERR_OR_NULL(pdcptr)) 527 iounmap(pdcptr); 528 if (!IS_ERR_OR_NULL(seqptr)) 529 iounmap(seqptr); 530 } 531 532 /* 533 * The lowest 16 bits of this value are the number of XO clock cycles for main 534 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 535 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 536 */ 537 538 #define GMU_PWR_COL_HYST 0x000a1680 539 540 /* Set up the idle state for the GMU */ 541 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 542 { 543 /* Disable GMU WB/RB buffer */ 544 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 545 546 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 547 548 switch (gmu->idle_level) { 549 case GMU_IDLE_STATE_IFPC: 550 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 551 GMU_PWR_COL_HYST); 552 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 553 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 554 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 555 /* Fall through */ 556 case GMU_IDLE_STATE_SPTP: 557 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 558 GMU_PWR_COL_HYST); 559 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 560 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 561 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 562 } 563 564 /* Enable RPMh GPU client */ 565 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 566 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 567 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 568 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 569 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 570 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 571 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 572 } 573 574 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 575 { 576 static bool rpmh_init; 577 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 578 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 579 int i, ret; 580 u32 chipid; 581 u32 *image; 582 583 if (state == GMU_WARM_BOOT) { 584 ret = a6xx_rpmh_start(gmu); 585 if (ret) 586 return ret; 587 } else { 588 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 589 "GMU firmware is not loaded\n")) 590 return -ENOENT; 591 592 /* Sanity check the size of the firmware that was loaded */ 593 if (adreno_gpu->fw[ADRENO_FW_GMU]->size > 0x8000) { 594 DRM_DEV_ERROR(gmu->dev, 595 "GMU firmware is bigger than the available region\n"); 596 return -EINVAL; 597 } 598 599 /* Turn on register retention */ 600 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 601 602 /* We only need to load the RPMh microcode once */ 603 if (!rpmh_init) { 604 a6xx_gmu_rpmh_init(gmu); 605 rpmh_init = true; 606 } else { 607 ret = a6xx_rpmh_start(gmu); 608 if (ret) 609 return ret; 610 } 611 612 image = (u32 *) adreno_gpu->fw[ADRENO_FW_GMU]->data; 613 614 for (i = 0; i < adreno_gpu->fw[ADRENO_FW_GMU]->size >> 2; i++) 615 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, 616 image[i]); 617 } 618 619 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 620 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 621 622 /* Write the iova of the HFI table */ 623 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova); 624 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 625 626 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 627 (1 << 31) | (0xa << 18) | (0xa0)); 628 629 chipid = adreno_gpu->rev.core << 24; 630 chipid |= adreno_gpu->rev.major << 16; 631 chipid |= adreno_gpu->rev.minor << 12; 632 chipid |= adreno_gpu->rev.patchid << 8; 633 634 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 635 636 /* Set up the lowest idle level on the GMU */ 637 a6xx_gmu_power_config(gmu); 638 639 ret = a6xx_gmu_start(gmu); 640 if (ret) 641 return ret; 642 643 ret = a6xx_gmu_gfx_rail_on(gmu); 644 if (ret) 645 return ret; 646 647 /* Enable SPTP_PC if the CPU is responsible for it */ 648 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 649 ret = a6xx_sptprac_enable(gmu); 650 if (ret) 651 return ret; 652 } 653 654 ret = a6xx_gmu_hfi_start(gmu); 655 if (ret) 656 return ret; 657 658 /* FIXME: Do we need this wmb() here? */ 659 wmb(); 660 661 return 0; 662 } 663 664 #define A6XX_HFI_IRQ_MASK \ 665 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 666 667 #define A6XX_GMU_IRQ_MASK \ 668 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 669 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 670 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 671 672 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 673 { 674 disable_irq(gmu->gmu_irq); 675 disable_irq(gmu->hfi_irq); 676 677 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 678 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 679 } 680 681 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 682 { 683 u32 val; 684 685 /* Make sure there are no outstanding RPMh votes */ 686 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 687 (val & 1), 100, 10000); 688 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 689 (val & 1), 100, 10000); 690 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 691 (val & 1), 100, 10000); 692 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 693 (val & 1), 100, 1000); 694 } 695 696 /* Force the GMU off in case it isn't responsive */ 697 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 698 { 699 /* Flush all the queues */ 700 a6xx_hfi_stop(gmu); 701 702 /* Stop the interrupts */ 703 a6xx_gmu_irq_disable(gmu); 704 705 /* Force off SPTP in case the GMU is managing it */ 706 a6xx_sptprac_disable(gmu); 707 708 /* Make sure there are no outstanding RPMh votes */ 709 a6xx_gmu_rpmh_off(gmu); 710 } 711 712 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 713 { 714 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 715 struct msm_gpu *gpu = &adreno_gpu->base; 716 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 717 int status, ret; 718 719 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 720 return 0; 721 722 gmu->hung = false; 723 724 /* Turn on the resources */ 725 pm_runtime_get_sync(gmu->dev); 726 727 /* Use a known rate to bring up the GMU */ 728 clk_set_rate(gmu->core_clk, 200000000); 729 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 730 if (ret) { 731 pm_runtime_put(gmu->dev); 732 return ret; 733 } 734 735 /* Set the bus quota to a reasonable value for boot */ 736 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); 737 738 /* Enable the GMU interrupt */ 739 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 740 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 741 enable_irq(gmu->gmu_irq); 742 743 /* Check to see if we are doing a cold or warm boot */ 744 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 745 GMU_WARM_BOOT : GMU_COLD_BOOT; 746 747 ret = a6xx_gmu_fw_start(gmu, status); 748 if (ret) 749 goto out; 750 751 ret = a6xx_hfi_start(gmu, status); 752 if (ret) 753 goto out; 754 755 /* 756 * Turn on the GMU firmware fault interrupt after we know the boot 757 * sequence is successful 758 */ 759 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 760 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 761 enable_irq(gmu->hfi_irq); 762 763 /* Set the GPU to the current freq */ 764 __a6xx_gmu_set_freq(gmu, gmu->current_perf_index); 765 766 /* 767 * "enable" the GX power domain which won't actually do anything but it 768 * will make sure that the refcounting is correct in case we need to 769 * bring down the GX after a GMU failure 770 */ 771 if (!IS_ERR_OR_NULL(gmu->gxpd)) 772 pm_runtime_get(gmu->gxpd); 773 774 out: 775 /* On failure, shut down the GMU to leave it in a good state */ 776 if (ret) { 777 disable_irq(gmu->gmu_irq); 778 a6xx_rpmh_stop(gmu); 779 pm_runtime_put(gmu->dev); 780 } 781 782 return ret; 783 } 784 785 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 786 { 787 u32 reg; 788 789 if (!gmu->initialized) 790 return true; 791 792 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 793 794 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 795 return false; 796 797 return true; 798 } 799 800 #define GBIF_CLIENT_HALT_MASK BIT(0) 801 #define GBIF_ARB_HALT_MASK BIT(1) 802 803 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) 804 { 805 struct msm_gpu *gpu = &adreno_gpu->base; 806 807 if (!a6xx_has_gbif(adreno_gpu)) { 808 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 809 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 810 0xf) == 0xf); 811 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 812 813 return; 814 } 815 816 /* Halt new client requests on GBIF */ 817 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 818 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 819 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 820 821 /* Halt all AXI requests on GBIF */ 822 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 823 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 824 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 825 826 /* The GBIF halt needs to be explicitly cleared */ 827 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 828 } 829 830 /* Gracefully try to shut down the GMU and by extension the GPU */ 831 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 832 { 833 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 834 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 835 u32 val; 836 837 /* 838 * The GMU may still be in slumber unless the GPU started so check and 839 * skip putting it back into slumber if so 840 */ 841 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 842 843 if (val != 0xf) { 844 int ret = a6xx_gmu_wait_for_idle(gmu); 845 846 /* If the GMU isn't responding assume it is hung */ 847 if (ret) { 848 a6xx_gmu_force_off(gmu); 849 return; 850 } 851 852 a6xx_bus_clear_pending_transactions(adreno_gpu); 853 854 /* tell the GMU we want to slumber */ 855 a6xx_gmu_notify_slumber(gmu); 856 857 ret = gmu_poll_timeout(gmu, 858 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 859 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 860 100, 10000); 861 862 /* 863 * Let the user know we failed to slumber but don't worry too 864 * much because we are powering down anyway 865 */ 866 867 if (ret) 868 DRM_DEV_ERROR(gmu->dev, 869 "Unable to slumber GMU: status = 0%x/0%x\n", 870 gmu_read(gmu, 871 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 872 gmu_read(gmu, 873 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 874 } 875 876 /* Turn off HFI */ 877 a6xx_hfi_stop(gmu); 878 879 /* Stop the interrupts and mask the hardware */ 880 a6xx_gmu_irq_disable(gmu); 881 882 /* Tell RPMh to power off the GPU */ 883 a6xx_rpmh_stop(gmu); 884 } 885 886 887 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 888 { 889 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 890 struct msm_gpu *gpu = &a6xx_gpu->base.base; 891 892 if (!pm_runtime_active(gmu->dev)) 893 return 0; 894 895 /* 896 * Force the GMU off if we detected a hang, otherwise try to shut it 897 * down gracefully 898 */ 899 if (gmu->hung) 900 a6xx_gmu_force_off(gmu); 901 else 902 a6xx_gmu_shutdown(gmu); 903 904 /* Remove the bus vote */ 905 icc_set_bw(gpu->icc_path, 0, 0); 906 907 /* 908 * Make sure the GX domain is off before turning off the GMU (CX) 909 * domain. Usually the GMU does this but only if the shutdown sequence 910 * was successful 911 */ 912 if (!IS_ERR_OR_NULL(gmu->gxpd)) 913 pm_runtime_put_sync(gmu->gxpd); 914 915 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 916 917 pm_runtime_put_sync(gmu->dev); 918 919 return 0; 920 } 921 922 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo) 923 { 924 if (IS_ERR_OR_NULL(bo)) 925 return; 926 927 dma_free_wc(gmu->dev, bo->size, bo->virt, bo->iova); 928 kfree(bo); 929 } 930 931 static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, 932 size_t size) 933 { 934 struct a6xx_gmu_bo *bo; 935 936 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 937 if (!bo) 938 return ERR_PTR(-ENOMEM); 939 940 bo->size = PAGE_ALIGN(size); 941 942 bo->virt = dma_alloc_wc(gmu->dev, bo->size, &bo->iova, GFP_KERNEL); 943 944 if (!bo->virt) { 945 kfree(bo); 946 return ERR_PTR(-ENOMEM); 947 } 948 949 return bo; 950 } 951 952 /* Return the 'arc-level' for the given frequency */ 953 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 954 unsigned long freq) 955 { 956 struct dev_pm_opp *opp; 957 unsigned int val; 958 959 if (!freq) 960 return 0; 961 962 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 963 if (IS_ERR(opp)) 964 return 0; 965 966 val = dev_pm_opp_get_level(opp); 967 968 dev_pm_opp_put(opp); 969 970 return val; 971 } 972 973 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 974 unsigned long *freqs, int freqs_count, const char *id) 975 { 976 int i, j; 977 const u16 *pri, *sec; 978 size_t pri_count, sec_count; 979 980 pri = cmd_db_read_aux_data(id, &pri_count); 981 if (IS_ERR(pri)) 982 return PTR_ERR(pri); 983 /* 984 * The data comes back as an array of unsigned shorts so adjust the 985 * count accordingly 986 */ 987 pri_count >>= 1; 988 if (!pri_count) 989 return -EINVAL; 990 991 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 992 if (IS_ERR(sec)) 993 return PTR_ERR(sec); 994 995 sec_count >>= 1; 996 if (!sec_count) 997 return -EINVAL; 998 999 /* Construct a vote for each frequency */ 1000 for (i = 0; i < freqs_count; i++) { 1001 u8 pindex = 0, sindex = 0; 1002 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1003 1004 /* Get the primary index that matches the arc level */ 1005 for (j = 0; j < pri_count; j++) { 1006 if (pri[j] >= level) { 1007 pindex = j; 1008 break; 1009 } 1010 } 1011 1012 if (j == pri_count) { 1013 DRM_DEV_ERROR(dev, 1014 "Level %u not found in the RPMh list\n", 1015 level); 1016 DRM_DEV_ERROR(dev, "Available levels:\n"); 1017 for (j = 0; j < pri_count; j++) 1018 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1019 1020 return -EINVAL; 1021 } 1022 1023 /* 1024 * Look for a level in in the secondary list that matches. If 1025 * nothing fits, use the maximum non zero vote 1026 */ 1027 1028 for (j = 0; j < sec_count; j++) { 1029 if (sec[j] >= level) { 1030 sindex = j; 1031 break; 1032 } else if (sec[j]) { 1033 sindex = j; 1034 } 1035 } 1036 1037 /* Construct the vote */ 1038 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1039 (sindex << 8) | pindex; 1040 } 1041 1042 return 0; 1043 } 1044 1045 /* 1046 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1047 * to construct the list of votes on the CPU and send it over. Query the RPMh 1048 * voltage levels and build the votes 1049 */ 1050 1051 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1052 { 1053 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1054 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1055 struct msm_gpu *gpu = &adreno_gpu->base; 1056 int ret; 1057 1058 /* Build the GX votes */ 1059 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1060 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1061 1062 /* Build the CX votes */ 1063 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1064 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1065 1066 return ret; 1067 } 1068 1069 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1070 u32 size) 1071 { 1072 int count = dev_pm_opp_get_opp_count(dev); 1073 struct dev_pm_opp *opp; 1074 int i, index = 0; 1075 unsigned long freq = 1; 1076 1077 /* 1078 * The OPP table doesn't contain the "off" frequency level so we need to 1079 * add 1 to the table size to account for it 1080 */ 1081 1082 if (WARN(count + 1 > size, 1083 "The GMU frequency table is being truncated\n")) 1084 count = size - 1; 1085 1086 /* Set the "off" frequency */ 1087 freqs[index++] = 0; 1088 1089 for (i = 0; i < count; i++) { 1090 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1091 if (IS_ERR(opp)) 1092 break; 1093 1094 dev_pm_opp_put(opp); 1095 freqs[index++] = freq++; 1096 } 1097 1098 return index; 1099 } 1100 1101 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1102 { 1103 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1104 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1105 struct msm_gpu *gpu = &adreno_gpu->base; 1106 1107 int ret = 0; 1108 1109 /* 1110 * The GMU handles its own frequency switching so build a list of 1111 * available frequencies to send during initialization 1112 */ 1113 ret = dev_pm_opp_of_add_table(gmu->dev); 1114 if (ret) { 1115 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1116 return ret; 1117 } 1118 1119 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1120 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1121 1122 /* 1123 * The GMU also handles GPU frequency switching so build a list 1124 * from the GPU OPP table 1125 */ 1126 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1127 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1128 1129 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1130 1131 /* Build the list of RPMh votes that we'll send to the GMU */ 1132 return a6xx_gmu_rpmh_votes_init(gmu); 1133 } 1134 1135 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1136 { 1137 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1138 1139 if (ret < 1) 1140 return ret; 1141 1142 gmu->nr_clocks = ret; 1143 1144 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1145 gmu->nr_clocks, "gmu"); 1146 1147 return 0; 1148 } 1149 1150 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1151 const char *name) 1152 { 1153 void __iomem *ret; 1154 struct resource *res = platform_get_resource_byname(pdev, 1155 IORESOURCE_MEM, name); 1156 1157 if (!res) { 1158 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1159 return ERR_PTR(-EINVAL); 1160 } 1161 1162 ret = ioremap(res->start, resource_size(res)); 1163 if (!ret) { 1164 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1165 return ERR_PTR(-EINVAL); 1166 } 1167 1168 return ret; 1169 } 1170 1171 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1172 const char *name, irq_handler_t handler) 1173 { 1174 int irq, ret; 1175 1176 irq = platform_get_irq_byname(pdev, name); 1177 1178 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1179 if (ret) { 1180 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1181 name, ret); 1182 return ret; 1183 } 1184 1185 disable_irq(irq); 1186 1187 return irq; 1188 } 1189 1190 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1191 { 1192 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1193 1194 if (!gmu->initialized) 1195 return; 1196 1197 pm_runtime_force_suspend(gmu->dev); 1198 1199 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1200 pm_runtime_disable(gmu->gxpd); 1201 dev_pm_domain_detach(gmu->gxpd, false); 1202 } 1203 1204 iounmap(gmu->mmio); 1205 gmu->mmio = NULL; 1206 1207 a6xx_gmu_memory_free(gmu, gmu->hfi); 1208 1209 free_irq(gmu->gmu_irq, gmu); 1210 free_irq(gmu->hfi_irq, gmu); 1211 1212 /* Drop reference taken in of_find_device_by_node */ 1213 put_device(gmu->dev); 1214 1215 gmu->initialized = false; 1216 } 1217 1218 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1219 { 1220 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1221 struct platform_device *pdev = of_find_device_by_node(node); 1222 int ret; 1223 1224 if (!pdev) 1225 return -ENODEV; 1226 1227 gmu->dev = &pdev->dev; 1228 1229 /* Pass force_dma false to require the DT to set the dma region */ 1230 ret = of_dma_configure(gmu->dev, node, false); 1231 if (ret) 1232 return ret; 1233 1234 /* Set the mask after the of_dma_configure() */ 1235 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(31)); 1236 if (ret) 1237 return ret; 1238 1239 /* Fow now, don't do anything fancy until we get our feet under us */ 1240 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1241 1242 pm_runtime_enable(gmu->dev); 1243 1244 /* Get the list of clocks */ 1245 ret = a6xx_gmu_clocks_probe(gmu); 1246 if (ret) 1247 goto err_put_device; 1248 1249 /* Allocate memory for for the HFI queues */ 1250 gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1251 if (IS_ERR(gmu->hfi)) 1252 goto err_memory; 1253 1254 /* Allocate memory for the GMU debug region */ 1255 gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); 1256 if (IS_ERR(gmu->debug)) 1257 goto err_memory; 1258 1259 /* Map the GMU registers */ 1260 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1261 if (IS_ERR(gmu->mmio)) 1262 goto err_memory; 1263 1264 /* Get the HFI and GMU interrupts */ 1265 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1266 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1267 1268 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) 1269 goto err_mmio; 1270 1271 /* 1272 * Get a link to the GX power domain to reset the GPU in case of GMU 1273 * crash 1274 */ 1275 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1276 1277 /* Get the power levels for the GMU and GPU */ 1278 a6xx_gmu_pwrlevels_probe(gmu); 1279 1280 /* Set up the HFI queues */ 1281 a6xx_hfi_init(gmu); 1282 1283 gmu->initialized = true; 1284 1285 return 0; 1286 1287 err_mmio: 1288 iounmap(gmu->mmio); 1289 free_irq(gmu->gmu_irq, gmu); 1290 free_irq(gmu->hfi_irq, gmu); 1291 err_memory: 1292 a6xx_gmu_memory_free(gmu, gmu->hfi); 1293 1294 ret = -ENODEV; 1295 1296 err_put_device: 1297 /* Drop reference taken in of_find_device_by_node */ 1298 put_device(gmu->dev); 1299 1300 return ret; 1301 } 1302