1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/clk.h> 5 #include <linux/interconnect.h> 6 #include <linux/of_platform.h> 7 #include <linux/platform_device.h> 8 #include <linux/pm_domain.h> 9 #include <linux/pm_opp.h> 10 #include <soc/qcom/cmd-db.h> 11 #include <drm/drm_gem.h> 12 13 #include "a6xx_gpu.h" 14 #include "a6xx_gmu.xml.h" 15 #include "msm_gem.h" 16 #include "msm_gpu_trace.h" 17 #include "msm_mmu.h" 18 19 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) 20 { 21 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 22 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 23 struct msm_gpu *gpu = &adreno_gpu->base; 24 25 /* FIXME: add a banner here */ 26 gmu->hung = true; 27 28 /* Turn off the hangcheck timer while we are resetting */ 29 del_timer(&gpu->hangcheck_timer); 30 31 /* Queue the GPU handler because we need to treat this as a recovery */ 32 kthread_queue_work(gpu->worker, &gpu->recover_work); 33 } 34 35 static irqreturn_t a6xx_gmu_irq(int irq, void *data) 36 { 37 struct a6xx_gmu *gmu = data; 38 u32 status; 39 40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); 41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); 42 43 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) { 44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); 45 46 a6xx_gmu_fault(gmu); 47 } 48 49 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR) 50 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); 51 52 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 53 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", 54 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); 55 56 return IRQ_HANDLED; 57 } 58 59 static irqreturn_t a6xx_hfi_irq(int irq, void *data) 60 { 61 struct a6xx_gmu *gmu = data; 62 u32 status; 63 64 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); 65 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); 66 67 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) { 68 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); 69 70 a6xx_gmu_fault(gmu); 71 } 72 73 return IRQ_HANDLED; 74 } 75 76 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu) 77 { 78 u32 val; 79 80 /* This can be called from gpu state code so make sure GMU is valid */ 81 if (!gmu->initialized) 82 return false; 83 84 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 85 86 return !(val & 87 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF | 88 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF)); 89 } 90 91 /* Check to see if the GX rail is still powered */ 92 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 93 { 94 u32 val; 95 96 /* This can be called from gpu state code so make sure GMU is valid */ 97 if (!gmu->initialized) 98 return false; 99 100 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 101 102 return !(val & 103 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 104 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 105 } 106 107 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 108 bool suspended) 109 { 110 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 111 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 112 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 113 u32 perf_index; 114 unsigned long gpu_freq; 115 int ret = 0; 116 117 gpu_freq = dev_pm_opp_get_freq(opp); 118 119 if (gpu_freq == gmu->freq) 120 return; 121 122 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++) 123 if (gpu_freq == gmu->gpu_freqs[perf_index]) 124 break; 125 126 gmu->current_perf_index = perf_index; 127 gmu->freq = gmu->gpu_freqs[perf_index]; 128 129 trace_msm_gmu_freq_change(gmu->freq, perf_index); 130 131 /* 132 * This can get called from devfreq while the hardware is idle. Don't 133 * bring up the power if it isn't already active. All we're doing here 134 * is updating the frequency so that when we come back online we're at 135 * the right rate. 136 */ 137 if (suspended) 138 return; 139 140 if (!gmu->legacy) { 141 a6xx_hfi_set_freq(gmu, perf_index); 142 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 143 return; 144 } 145 146 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); 147 148 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, 149 ((3 & 0xf) << 28) | perf_index); 150 151 /* 152 * Send an invalid index as a vote for the bus bandwidth and let the 153 * firmware decide on the right vote 154 */ 155 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); 156 157 /* Set and clear the OOB for DCVS to trigger the GMU */ 158 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); 159 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); 160 161 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); 162 if (ret) 163 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); 164 165 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 166 } 167 168 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu) 169 { 170 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 171 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 172 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 173 174 return gmu->freq; 175 } 176 177 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) 178 { 179 u32 val; 180 int local = gmu->idle_level; 181 182 /* SPTP and IFPC both report as IFPC */ 183 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) 184 local = GMU_IDLE_STATE_IFPC; 185 186 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 187 188 if (val == local) { 189 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 190 !a6xx_gmu_gx_is_on(gmu)) 191 return true; 192 } 193 194 return false; 195 } 196 197 /* Wait for the GMU to get to its most idle state */ 198 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu) 199 { 200 return spin_until(a6xx_gmu_check_idle_level(gmu)); 201 } 202 203 static int a6xx_gmu_start(struct a6xx_gmu *gmu) 204 { 205 int ret; 206 u32 val; 207 u32 mask, reset_val; 208 209 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8); 210 if (val <= 0x20010004) { 211 mask = 0xffffffff; 212 reset_val = 0xbabeface; 213 } else { 214 mask = 0x1ff; 215 reset_val = 0x100; 216 } 217 218 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 219 220 /* Set the log wptr index 221 * note: downstream saves the value in poweroff and restores it here 222 */ 223 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); 224 225 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); 226 227 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, 228 (val & mask) == reset_val, 100, 10000); 229 230 if (ret) 231 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n"); 232 233 return ret; 234 } 235 236 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) 237 { 238 u32 val; 239 int ret; 240 241 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); 242 243 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, 244 val & 1, 100, 10000); 245 if (ret) 246 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n"); 247 248 return ret; 249 } 250 251 struct a6xx_gmu_oob_bits { 252 int set, ack, set_new, ack_new, clear, clear_new; 253 const char *name; 254 }; 255 256 /* These are the interrupt / ack bits for each OOB request that are set 257 * in a6xx_gmu_set_oob and a6xx_clear_oob 258 */ 259 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = { 260 [GMU_OOB_GPU_SET] = { 261 .name = "GPU_SET", 262 .set = 16, 263 .ack = 24, 264 .set_new = 30, 265 .ack_new = 31, 266 .clear = 24, 267 .clear_new = 31, 268 }, 269 270 [GMU_OOB_PERFCOUNTER_SET] = { 271 .name = "PERFCOUNTER", 272 .set = 17, 273 .ack = 25, 274 .set_new = 28, 275 .ack_new = 30, 276 .clear = 25, 277 .clear_new = 29, 278 }, 279 280 [GMU_OOB_BOOT_SLUMBER] = { 281 .name = "BOOT_SLUMBER", 282 .set = 22, 283 .ack = 30, 284 .clear = 30, 285 }, 286 287 [GMU_OOB_DCVS_SET] = { 288 .name = "GPU_DCVS", 289 .set = 23, 290 .ack = 31, 291 .clear = 31, 292 }, 293 }; 294 295 /* Trigger a OOB (out of band) request to the GMU */ 296 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 297 { 298 int ret; 299 u32 val; 300 int request, ack; 301 302 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 303 304 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 305 return -EINVAL; 306 307 if (gmu->legacy) { 308 request = a6xx_gmu_oob_bits[state].set; 309 ack = a6xx_gmu_oob_bits[state].ack; 310 } else { 311 request = a6xx_gmu_oob_bits[state].set_new; 312 ack = a6xx_gmu_oob_bits[state].ack_new; 313 if (!request || !ack) { 314 DRM_DEV_ERROR(gmu->dev, 315 "Invalid non-legacy GMU request %s\n", 316 a6xx_gmu_oob_bits[state].name); 317 return -EINVAL; 318 } 319 } 320 321 /* Trigger the equested OOB operation */ 322 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); 323 324 /* Wait for the acknowledge interrupt */ 325 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, 326 val & (1 << ack), 100, 10000); 327 328 if (ret) 329 DRM_DEV_ERROR(gmu->dev, 330 "Timeout waiting for GMU OOB set %s: 0x%x\n", 331 a6xx_gmu_oob_bits[state].name, 332 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); 333 334 /* Clear the acknowledge interrupt */ 335 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); 336 337 return ret; 338 } 339 340 /* Clear a pending OOB state in the GMU */ 341 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) 342 { 343 int bit; 344 345 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock)); 346 347 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits)) 348 return; 349 350 if (gmu->legacy) 351 bit = a6xx_gmu_oob_bits[state].clear; 352 else 353 bit = a6xx_gmu_oob_bits[state].clear_new; 354 355 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); 356 } 357 358 /* Enable CPU control of SPTP power power collapse */ 359 int a6xx_sptprac_enable(struct a6xx_gmu *gmu) 360 { 361 int ret; 362 u32 val; 363 364 if (!gmu->legacy) 365 return 0; 366 367 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); 368 369 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 370 (val & 0x38) == 0x28, 1, 100); 371 372 if (ret) { 373 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", 374 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 375 } 376 377 return 0; 378 } 379 380 /* Disable CPU control of SPTP power power collapse */ 381 void a6xx_sptprac_disable(struct a6xx_gmu *gmu) 382 { 383 u32 val; 384 int ret; 385 386 if (!gmu->legacy) 387 return; 388 389 /* Make sure retention is on */ 390 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); 391 392 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); 393 394 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, 395 (val & 0x04), 100, 10000); 396 397 if (ret) 398 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", 399 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); 400 } 401 402 /* Let the GMU know we are starting a boot sequence */ 403 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) 404 { 405 u32 vote; 406 407 /* Let the GMU know we are getting ready for boot */ 408 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); 409 410 /* Choose the "default" power level as the highest available */ 411 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; 412 413 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); 414 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); 415 416 /* Let the GMU know the boot sequence has started */ 417 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 418 } 419 420 /* Let the GMU know that we are about to go into slumber */ 421 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 422 { 423 int ret; 424 425 /* Disable the power counter so the GMU isn't busy */ 426 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); 427 428 /* Disable SPTP_PC if the CPU is responsible for it */ 429 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) 430 a6xx_sptprac_disable(gmu); 431 432 if (!gmu->legacy) { 433 ret = a6xx_hfi_send_prep_slumber(gmu); 434 goto out; 435 } 436 437 /* Tell the GMU to get ready to slumber */ 438 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); 439 440 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); 441 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); 442 443 if (!ret) { 444 /* Check to see if the GMU really did slumber */ 445 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) 446 != 0x0f) { 447 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); 448 ret = -ETIMEDOUT; 449 } 450 } 451 452 out: 453 /* Put fence into allow mode */ 454 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); 455 return ret; 456 } 457 458 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) 459 { 460 int ret; 461 u32 val; 462 463 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); 464 /* Wait for the register to finish posting */ 465 wmb(); 466 467 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, 468 val & (1 << 1), 100, 10000); 469 if (ret) { 470 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n"); 471 return ret; 472 } 473 474 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, 475 !val, 100, 10000); 476 477 if (ret) { 478 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); 479 return ret; 480 } 481 482 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 483 484 return 0; 485 } 486 487 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) 488 { 489 int ret; 490 u32 val; 491 492 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); 493 494 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, 495 val, val & (1 << 16), 100, 10000); 496 if (ret) 497 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n"); 498 499 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); 500 } 501 502 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value) 503 { 504 msm_writel(value, ptr + (offset << 2)); 505 } 506 507 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 508 const char *name); 509 510 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 511 { 512 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 513 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 514 struct platform_device *pdev = to_platform_device(gmu->dev); 515 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); 516 void __iomem *seqptr = NULL; 517 uint32_t pdc_address_offset; 518 bool pdc_in_aop = false; 519 520 if (IS_ERR(pdcptr)) 521 goto err; 522 523 if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) 524 pdc_in_aop = true; 525 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu)) 526 pdc_address_offset = 0x30090; 527 else if (adreno_is_a619(adreno_gpu)) 528 pdc_address_offset = 0x300a0; 529 else 530 pdc_address_offset = 0x30080; 531 532 if (!pdc_in_aop) { 533 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); 534 if (IS_ERR(seqptr)) 535 goto err; 536 } 537 538 /* Disable SDE clock gating */ 539 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); 540 541 /* Setup RSC PDC handshake for sleep and wakeup */ 542 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); 543 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); 544 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); 545 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); 546 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); 547 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); 548 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); 549 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); 550 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); 551 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); 552 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); 553 554 /* Load RSC sequencer uCode for sleep and wakeup */ 555 if (adreno_is_a650_family(adreno_gpu)) { 556 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); 557 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); 558 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); 559 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); 560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); 561 } else { 562 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); 563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); 564 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); 565 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); 566 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); 567 } 568 569 if (pdc_in_aop) 570 goto setup_pdc; 571 572 /* Load PDC sequencer uCode for power up and power down sequence */ 573 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); 574 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); 575 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); 576 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); 577 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); 578 579 /* Set TCS commands used by PDC sequence for low power modes */ 580 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); 581 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); 582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); 583 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); 584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); 585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); 586 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); 587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); 588 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); 589 590 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); 591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset); 592 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); 593 594 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); 595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); 596 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); 597 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); 598 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); 599 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); 600 601 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); 602 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); 603 if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) || 604 adreno_is_a650_family(adreno_gpu)) 605 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); 606 else 607 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); 608 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); 609 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset); 610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); 611 612 /* Setup GPU PDC */ 613 setup_pdc: 614 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); 615 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); 616 617 /* ensure no writes happen before the uCode is fully written */ 618 wmb(); 619 620 a6xx_rpmh_stop(gmu); 621 622 err: 623 if (!IS_ERR_OR_NULL(pdcptr)) 624 iounmap(pdcptr); 625 if (!IS_ERR_OR_NULL(seqptr)) 626 iounmap(seqptr); 627 } 628 629 /* 630 * The lowest 16 bits of this value are the number of XO clock cycles for main 631 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are 632 * for the shorter hysteresis that happens after main - this is 0xa (.5 us) 633 */ 634 635 #define GMU_PWR_COL_HYST 0x000a1680 636 637 /* Set up the idle state for the GMU */ 638 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) 639 { 640 /* Disable GMU WB/RB buffer */ 641 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); 642 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1); 643 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1); 644 645 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); 646 647 switch (gmu->idle_level) { 648 case GMU_IDLE_STATE_IFPC: 649 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, 650 GMU_PWR_COL_HYST); 651 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 652 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 653 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE); 654 fallthrough; 655 case GMU_IDLE_STATE_SPTP: 656 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, 657 GMU_PWR_COL_HYST); 658 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, 659 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE | 660 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE); 661 } 662 663 /* Enable RPMh GPU client */ 664 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, 665 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE | 666 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE | 667 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE | 668 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE | 669 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE | 670 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE); 671 } 672 673 struct block_header { 674 u32 addr; 675 u32 size; 676 u32 type; 677 u32 value; 678 u32 data[]; 679 }; 680 681 /* this should be a general kernel helper */ 682 static int in_range(u32 addr, u32 start, u32 size) 683 { 684 return addr >= start && addr < start + size; 685 } 686 687 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk) 688 { 689 if (!in_range(blk->addr, bo->iova, bo->size)) 690 return false; 691 692 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size); 693 return true; 694 } 695 696 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) 697 { 698 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 699 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 700 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU]; 701 const struct block_header *blk; 702 u32 reg_offset; 703 704 u32 itcm_base = 0x00000000; 705 u32 dtcm_base = 0x00040000; 706 707 if (adreno_is_a650_family(adreno_gpu)) 708 dtcm_base = 0x10004000; 709 710 if (gmu->legacy) { 711 /* Sanity check the size of the firmware that was loaded */ 712 if (fw_image->size > 0x8000) { 713 DRM_DEV_ERROR(gmu->dev, 714 "GMU firmware is bigger than the available region\n"); 715 return -EINVAL; 716 } 717 718 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START, 719 (u32*) fw_image->data, fw_image->size); 720 return 0; 721 } 722 723 724 for (blk = (const struct block_header *) fw_image->data; 725 (const u8*) blk < fw_image->data + fw_image->size; 726 blk = (const struct block_header *) &blk->data[blk->size >> 2]) { 727 if (blk->size == 0) 728 continue; 729 730 if (in_range(blk->addr, itcm_base, SZ_16K)) { 731 reg_offset = (blk->addr - itcm_base) >> 2; 732 gmu_write_bulk(gmu, 733 REG_A6XX_GMU_CM3_ITCM_START + reg_offset, 734 blk->data, blk->size); 735 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) { 736 reg_offset = (blk->addr - dtcm_base) >> 2; 737 gmu_write_bulk(gmu, 738 REG_A6XX_GMU_CM3_DTCM_START + reg_offset, 739 blk->data, blk->size); 740 } else if (!fw_block_mem(&gmu->icache, blk) && 741 !fw_block_mem(&gmu->dcache, blk) && 742 !fw_block_mem(&gmu->dummy, blk)) { 743 DRM_DEV_ERROR(gmu->dev, 744 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n", 745 blk->addr, blk->size, blk->data[0]); 746 } 747 } 748 749 return 0; 750 } 751 752 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 753 { 754 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 755 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 756 int ret; 757 u32 chipid; 758 759 if (adreno_is_a650_family(adreno_gpu)) { 760 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); 761 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); 762 } 763 764 if (state == GMU_WARM_BOOT) { 765 ret = a6xx_rpmh_start(gmu); 766 if (ret) 767 return ret; 768 } else { 769 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU], 770 "GMU firmware is not loaded\n")) 771 return -ENOENT; 772 773 /* Turn on register retention */ 774 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); 775 776 ret = a6xx_rpmh_start(gmu); 777 if (ret) 778 return ret; 779 780 ret = a6xx_gmu_fw_load(gmu); 781 if (ret) 782 return ret; 783 } 784 785 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); 786 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); 787 788 /* Write the iova of the HFI table */ 789 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova); 790 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); 791 792 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, 793 (1 << 31) | (0xa << 18) | (0xa0)); 794 795 chipid = adreno_gpu->rev.core << 24; 796 chipid |= adreno_gpu->rev.major << 16; 797 chipid |= adreno_gpu->rev.minor << 12; 798 chipid |= adreno_gpu->rev.patchid << 8; 799 800 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); 801 802 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG, 803 gmu->log.iova | (gmu->log.size / SZ_4K - 1)); 804 805 /* Set up the lowest idle level on the GMU */ 806 a6xx_gmu_power_config(gmu); 807 808 ret = a6xx_gmu_start(gmu); 809 if (ret) 810 return ret; 811 812 if (gmu->legacy) { 813 ret = a6xx_gmu_gfx_rail_on(gmu); 814 if (ret) 815 return ret; 816 } 817 818 /* Enable SPTP_PC if the CPU is responsible for it */ 819 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { 820 ret = a6xx_sptprac_enable(gmu); 821 if (ret) 822 return ret; 823 } 824 825 ret = a6xx_gmu_hfi_start(gmu); 826 if (ret) 827 return ret; 828 829 /* FIXME: Do we need this wmb() here? */ 830 wmb(); 831 832 return 0; 833 } 834 835 #define A6XX_HFI_IRQ_MASK \ 836 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) 837 838 #define A6XX_GMU_IRQ_MASK \ 839 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \ 840 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \ 841 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR) 842 843 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) 844 { 845 disable_irq(gmu->gmu_irq); 846 disable_irq(gmu->hfi_irq); 847 848 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); 849 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); 850 } 851 852 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) 853 { 854 u32 val; 855 856 /* Make sure there are no outstanding RPMh votes */ 857 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, 858 (val & 1), 100, 10000); 859 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, 860 (val & 1), 100, 10000); 861 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, 862 (val & 1), 100, 10000); 863 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, 864 (val & 1), 100, 1000); 865 } 866 867 /* Force the GMU off in case it isn't responsive */ 868 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) 869 { 870 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 871 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 872 struct msm_gpu *gpu = &adreno_gpu->base; 873 874 /* 875 * Turn off keep alive that might have been enabled by the hang 876 * interrupt 877 */ 878 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 879 880 /* Flush all the queues */ 881 a6xx_hfi_stop(gmu); 882 883 /* Stop the interrupts */ 884 a6xx_gmu_irq_disable(gmu); 885 886 /* Force off SPTP in case the GMU is managing it */ 887 a6xx_sptprac_disable(gmu); 888 889 /* Make sure there are no outstanding RPMh votes */ 890 a6xx_gmu_rpmh_off(gmu); 891 892 /* Halt the gmu cm3 core */ 893 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); 894 895 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 896 897 /* Reset GPU core blocks */ 898 a6xx_gpu_sw_reset(gpu, true); 899 } 900 901 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 902 { 903 struct dev_pm_opp *gpu_opp; 904 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 905 906 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 907 if (IS_ERR(gpu_opp)) 908 return; 909 910 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */ 911 a6xx_gmu_set_freq(gpu, gpu_opp, false); 912 dev_pm_opp_put(gpu_opp); 913 } 914 915 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu) 916 { 917 struct dev_pm_opp *gpu_opp; 918 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index]; 919 920 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true); 921 if (IS_ERR(gpu_opp)) 922 return; 923 924 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp); 925 dev_pm_opp_put(gpu_opp); 926 } 927 928 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 929 { 930 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 931 struct msm_gpu *gpu = &adreno_gpu->base; 932 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 933 int status, ret; 934 935 if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) 936 return -EINVAL; 937 938 gmu->hung = false; 939 940 /* Turn on the resources */ 941 pm_runtime_get_sync(gmu->dev); 942 943 /* 944 * "enable" the GX power domain which won't actually do anything but it 945 * will make sure that the refcounting is correct in case we need to 946 * bring down the GX after a GMU failure 947 */ 948 if (!IS_ERR_OR_NULL(gmu->gxpd)) 949 pm_runtime_get_sync(gmu->gxpd); 950 951 /* Use a known rate to bring up the GMU */ 952 clk_set_rate(gmu->core_clk, 200000000); 953 clk_set_rate(gmu->hub_clk, 150000000); 954 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); 955 if (ret) { 956 pm_runtime_put(gmu->gxpd); 957 pm_runtime_put(gmu->dev); 958 return ret; 959 } 960 961 /* Set the bus quota to a reasonable value for boot */ 962 a6xx_gmu_set_initial_bw(gpu, gmu); 963 964 /* Enable the GMU interrupt */ 965 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); 966 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); 967 enable_irq(gmu->gmu_irq); 968 969 /* Check to see if we are doing a cold or warm boot */ 970 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? 971 GMU_WARM_BOOT : GMU_COLD_BOOT; 972 973 /* 974 * Warm boot path does not work on newer GPUs 975 * Presumably this is because icache/dcache regions must be restored 976 */ 977 if (!gmu->legacy) 978 status = GMU_COLD_BOOT; 979 980 ret = a6xx_gmu_fw_start(gmu, status); 981 if (ret) 982 goto out; 983 984 ret = a6xx_hfi_start(gmu, status); 985 if (ret) 986 goto out; 987 988 /* 989 * Turn on the GMU firmware fault interrupt after we know the boot 990 * sequence is successful 991 */ 992 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); 993 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); 994 enable_irq(gmu->hfi_irq); 995 996 /* Set the GPU to the current freq */ 997 a6xx_gmu_set_initial_freq(gpu, gmu); 998 999 out: 1000 /* On failure, shut down the GMU to leave it in a good state */ 1001 if (ret) { 1002 disable_irq(gmu->gmu_irq); 1003 a6xx_rpmh_stop(gmu); 1004 pm_runtime_put(gmu->gxpd); 1005 pm_runtime_put(gmu->dev); 1006 } 1007 1008 return ret; 1009 } 1010 1011 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) 1012 { 1013 u32 reg; 1014 1015 if (!gmu->initialized) 1016 return true; 1017 1018 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); 1019 1020 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB) 1021 return false; 1022 1023 return true; 1024 } 1025 1026 /* Gracefully try to shut down the GMU and by extension the GPU */ 1027 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) 1028 { 1029 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1030 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1031 u32 val; 1032 1033 /* 1034 * The GMU may still be in slumber unless the GPU started so check and 1035 * skip putting it back into slumber if so 1036 */ 1037 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); 1038 1039 if (val != 0xf) { 1040 int ret = a6xx_gmu_wait_for_idle(gmu); 1041 1042 /* If the GMU isn't responding assume it is hung */ 1043 if (ret) { 1044 a6xx_gmu_force_off(gmu); 1045 return; 1046 } 1047 1048 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung); 1049 1050 /* tell the GMU we want to slumber */ 1051 ret = a6xx_gmu_notify_slumber(gmu); 1052 if (ret) { 1053 a6xx_gmu_force_off(gmu); 1054 return; 1055 } 1056 1057 ret = gmu_poll_timeout(gmu, 1058 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val, 1059 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB), 1060 100, 10000); 1061 1062 /* 1063 * Let the user know we failed to slumber but don't worry too 1064 * much because we are powering down anyway 1065 */ 1066 1067 if (ret) 1068 DRM_DEV_ERROR(gmu->dev, 1069 "Unable to slumber GMU: status = 0%x/0%x\n", 1070 gmu_read(gmu, 1071 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS), 1072 gmu_read(gmu, 1073 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2)); 1074 } 1075 1076 /* Turn off HFI */ 1077 a6xx_hfi_stop(gmu); 1078 1079 /* Stop the interrupts and mask the hardware */ 1080 a6xx_gmu_irq_disable(gmu); 1081 1082 /* Tell RPMh to power off the GPU */ 1083 a6xx_rpmh_stop(gmu); 1084 } 1085 1086 1087 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) 1088 { 1089 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1090 struct msm_gpu *gpu = &a6xx_gpu->base.base; 1091 1092 if (!pm_runtime_active(gmu->dev)) 1093 return 0; 1094 1095 /* 1096 * Force the GMU off if we detected a hang, otherwise try to shut it 1097 * down gracefully 1098 */ 1099 if (gmu->hung) 1100 a6xx_gmu_force_off(gmu); 1101 else 1102 a6xx_gmu_shutdown(gmu); 1103 1104 /* Remove the bus vote */ 1105 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1106 1107 /* 1108 * Make sure the GX domain is off before turning off the GMU (CX) 1109 * domain. Usually the GMU does this but only if the shutdown sequence 1110 * was successful 1111 */ 1112 if (!IS_ERR_OR_NULL(gmu->gxpd)) 1113 pm_runtime_put_sync(gmu->gxpd); 1114 1115 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); 1116 1117 pm_runtime_put_sync(gmu->dev); 1118 1119 return 0; 1120 } 1121 1122 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu) 1123 { 1124 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace); 1125 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace); 1126 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace); 1127 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace); 1128 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace); 1129 msm_gem_kernel_put(gmu->log.obj, gmu->aspace); 1130 1131 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu); 1132 msm_gem_address_space_put(gmu->aspace); 1133 } 1134 1135 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, 1136 size_t size, u64 iova, const char *name) 1137 { 1138 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1139 struct drm_device *dev = a6xx_gpu->base.base.dev; 1140 uint32_t flags = MSM_BO_WC; 1141 u64 range_start, range_end; 1142 int ret; 1143 1144 size = PAGE_ALIGN(size); 1145 if (!iova) { 1146 /* no fixed address - use GMU's uncached range */ 1147 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */ 1148 range_end = 0x80000000; 1149 } else { 1150 /* range for fixed address */ 1151 range_start = iova; 1152 range_end = iova + size; 1153 /* use IOMMU_PRIV for icache/dcache */ 1154 flags |= MSM_BO_MAP_PRIV; 1155 } 1156 1157 bo->obj = msm_gem_new(dev, size, flags); 1158 if (IS_ERR(bo->obj)) 1159 return PTR_ERR(bo->obj); 1160 1161 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova, 1162 range_start, range_end); 1163 if (ret) { 1164 drm_gem_object_put(bo->obj); 1165 return ret; 1166 } 1167 1168 bo->virt = msm_gem_get_vaddr(bo->obj); 1169 bo->size = size; 1170 1171 msm_gem_object_set_name(bo->obj, name); 1172 1173 return 0; 1174 } 1175 1176 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) 1177 { 1178 struct msm_mmu *mmu; 1179 1180 mmu = msm_iommu_new(gmu->dev, 0); 1181 if (!mmu) 1182 return -ENODEV; 1183 if (IS_ERR(mmu)) 1184 return PTR_ERR(mmu); 1185 1186 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); 1187 if (IS_ERR(gmu->aspace)) 1188 return PTR_ERR(gmu->aspace); 1189 1190 return 0; 1191 } 1192 1193 /* Return the 'arc-level' for the given frequency */ 1194 static unsigned int a6xx_gmu_get_arc_level(struct device *dev, 1195 unsigned long freq) 1196 { 1197 struct dev_pm_opp *opp; 1198 unsigned int val; 1199 1200 if (!freq) 1201 return 0; 1202 1203 opp = dev_pm_opp_find_freq_exact(dev, freq, true); 1204 if (IS_ERR(opp)) 1205 return 0; 1206 1207 val = dev_pm_opp_get_level(opp); 1208 1209 dev_pm_opp_put(opp); 1210 1211 return val; 1212 } 1213 1214 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, 1215 unsigned long *freqs, int freqs_count, const char *id) 1216 { 1217 int i, j; 1218 const u16 *pri, *sec; 1219 size_t pri_count, sec_count; 1220 1221 pri = cmd_db_read_aux_data(id, &pri_count); 1222 if (IS_ERR(pri)) 1223 return PTR_ERR(pri); 1224 /* 1225 * The data comes back as an array of unsigned shorts so adjust the 1226 * count accordingly 1227 */ 1228 pri_count >>= 1; 1229 if (!pri_count) 1230 return -EINVAL; 1231 1232 sec = cmd_db_read_aux_data("mx.lvl", &sec_count); 1233 if (IS_ERR(sec)) 1234 return PTR_ERR(sec); 1235 1236 sec_count >>= 1; 1237 if (!sec_count) 1238 return -EINVAL; 1239 1240 /* Construct a vote for each frequency */ 1241 for (i = 0; i < freqs_count; i++) { 1242 u8 pindex = 0, sindex = 0; 1243 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); 1244 1245 /* Get the primary index that matches the arc level */ 1246 for (j = 0; j < pri_count; j++) { 1247 if (pri[j] >= level) { 1248 pindex = j; 1249 break; 1250 } 1251 } 1252 1253 if (j == pri_count) { 1254 DRM_DEV_ERROR(dev, 1255 "Level %u not found in the RPMh list\n", 1256 level); 1257 DRM_DEV_ERROR(dev, "Available levels:\n"); 1258 for (j = 0; j < pri_count; j++) 1259 DRM_DEV_ERROR(dev, " %u\n", pri[j]); 1260 1261 return -EINVAL; 1262 } 1263 1264 /* 1265 * Look for a level in in the secondary list that matches. If 1266 * nothing fits, use the maximum non zero vote 1267 */ 1268 1269 for (j = 0; j < sec_count; j++) { 1270 if (sec[j] >= level) { 1271 sindex = j; 1272 break; 1273 } else if (sec[j]) { 1274 sindex = j; 1275 } 1276 } 1277 1278 /* Construct the vote */ 1279 votes[i] = ((pri[pindex] & 0xffff) << 16) | 1280 (sindex << 8) | pindex; 1281 } 1282 1283 return 0; 1284 } 1285 1286 /* 1287 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need 1288 * to construct the list of votes on the CPU and send it over. Query the RPMh 1289 * voltage levels and build the votes 1290 */ 1291 1292 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) 1293 { 1294 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1295 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1296 struct msm_gpu *gpu = &adreno_gpu->base; 1297 int ret; 1298 1299 /* Build the GX votes */ 1300 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, 1301 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl"); 1302 1303 /* Build the CX votes */ 1304 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, 1305 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); 1306 1307 return ret; 1308 } 1309 1310 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, 1311 u32 size) 1312 { 1313 int count = dev_pm_opp_get_opp_count(dev); 1314 struct dev_pm_opp *opp; 1315 int i, index = 0; 1316 unsigned long freq = 1; 1317 1318 /* 1319 * The OPP table doesn't contain the "off" frequency level so we need to 1320 * add 1 to the table size to account for it 1321 */ 1322 1323 if (WARN(count + 1 > size, 1324 "The GMU frequency table is being truncated\n")) 1325 count = size - 1; 1326 1327 /* Set the "off" frequency */ 1328 freqs[index++] = 0; 1329 1330 for (i = 0; i < count; i++) { 1331 opp = dev_pm_opp_find_freq_ceil(dev, &freq); 1332 if (IS_ERR(opp)) 1333 break; 1334 1335 dev_pm_opp_put(opp); 1336 freqs[index++] = freq++; 1337 } 1338 1339 return index; 1340 } 1341 1342 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) 1343 { 1344 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 1345 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1346 struct msm_gpu *gpu = &adreno_gpu->base; 1347 1348 int ret = 0; 1349 1350 /* 1351 * The GMU handles its own frequency switching so build a list of 1352 * available frequencies to send during initialization 1353 */ 1354 ret = devm_pm_opp_of_add_table(gmu->dev); 1355 if (ret) { 1356 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); 1357 return ret; 1358 } 1359 1360 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, 1361 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); 1362 1363 /* 1364 * The GMU also handles GPU frequency switching so build a list 1365 * from the GPU OPP table 1366 */ 1367 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, 1368 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); 1369 1370 gmu->current_perf_index = gmu->nr_gpu_freqs - 1; 1371 1372 /* Build the list of RPMh votes that we'll send to the GMU */ 1373 return a6xx_gmu_rpmh_votes_init(gmu); 1374 } 1375 1376 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 1377 { 1378 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks); 1379 1380 if (ret < 1) 1381 return ret; 1382 1383 gmu->nr_clocks = ret; 1384 1385 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, 1386 gmu->nr_clocks, "gmu"); 1387 1388 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks, 1389 gmu->nr_clocks, "hub"); 1390 1391 return 0; 1392 } 1393 1394 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, 1395 const char *name) 1396 { 1397 void __iomem *ret; 1398 struct resource *res = platform_get_resource_byname(pdev, 1399 IORESOURCE_MEM, name); 1400 1401 if (!res) { 1402 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name); 1403 return ERR_PTR(-EINVAL); 1404 } 1405 1406 ret = ioremap(res->start, resource_size(res)); 1407 if (!ret) { 1408 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name); 1409 return ERR_PTR(-EINVAL); 1410 } 1411 1412 return ret; 1413 } 1414 1415 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, 1416 const char *name, irq_handler_t handler) 1417 { 1418 int irq, ret; 1419 1420 irq = platform_get_irq_byname(pdev, name); 1421 1422 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu); 1423 if (ret) { 1424 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n", 1425 name, ret); 1426 return ret; 1427 } 1428 1429 disable_irq(irq); 1430 1431 return irq; 1432 } 1433 1434 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) 1435 { 1436 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1437 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1438 struct platform_device *pdev = to_platform_device(gmu->dev); 1439 1440 if (!gmu->initialized) 1441 return; 1442 1443 pm_runtime_force_suspend(gmu->dev); 1444 1445 /* 1446 * Since cxpd is a virt device, the devlink with gmu-dev will be removed 1447 * automatically when we do detach 1448 */ 1449 dev_pm_domain_detach(gmu->cxpd, false); 1450 1451 if (!IS_ERR_OR_NULL(gmu->gxpd)) { 1452 pm_runtime_disable(gmu->gxpd); 1453 dev_pm_domain_detach(gmu->gxpd, false); 1454 } 1455 1456 iounmap(gmu->mmio); 1457 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1458 iounmap(gmu->rscc); 1459 gmu->mmio = NULL; 1460 gmu->rscc = NULL; 1461 1462 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1463 a6xx_gmu_memory_free(gmu); 1464 1465 free_irq(gmu->gmu_irq, gmu); 1466 free_irq(gmu->hfi_irq, gmu); 1467 } 1468 1469 /* Drop reference taken in of_find_device_by_node */ 1470 put_device(gmu->dev); 1471 1472 gmu->initialized = false; 1473 } 1474 1475 static int cxpd_notifier_cb(struct notifier_block *nb, 1476 unsigned long action, void *data) 1477 { 1478 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb); 1479 1480 if (action == GENPD_NOTIFY_OFF) 1481 complete_all(&gmu->pd_gate); 1482 1483 return 0; 1484 } 1485 1486 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1487 { 1488 struct platform_device *pdev = of_find_device_by_node(node); 1489 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1490 int ret; 1491 1492 if (!pdev) 1493 return -ENODEV; 1494 1495 gmu->dev = &pdev->dev; 1496 1497 of_dma_configure(gmu->dev, node, true); 1498 1499 pm_runtime_enable(gmu->dev); 1500 1501 /* Mark legacy for manual SPTPRAC control */ 1502 gmu->legacy = true; 1503 1504 /* Map the GMU registers */ 1505 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1506 if (IS_ERR(gmu->mmio)) { 1507 ret = PTR_ERR(gmu->mmio); 1508 goto err_mmio; 1509 } 1510 1511 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 1512 if (IS_ERR(gmu->cxpd)) { 1513 ret = PTR_ERR(gmu->cxpd); 1514 goto err_mmio; 1515 } 1516 1517 if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) { 1518 ret = -ENODEV; 1519 goto detach_cxpd; 1520 } 1521 1522 init_completion(&gmu->pd_gate); 1523 complete_all(&gmu->pd_gate); 1524 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 1525 1526 /* Get a link to the GX power domain to reset the GPU */ 1527 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1528 if (IS_ERR(gmu->gxpd)) { 1529 ret = PTR_ERR(gmu->gxpd); 1530 goto err_mmio; 1531 } 1532 1533 gmu->initialized = true; 1534 1535 return 0; 1536 1537 detach_cxpd: 1538 dev_pm_domain_detach(gmu->cxpd, false); 1539 1540 err_mmio: 1541 iounmap(gmu->mmio); 1542 1543 /* Drop reference taken in of_find_device_by_node */ 1544 put_device(gmu->dev); 1545 1546 return ret; 1547 } 1548 1549 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 1550 { 1551 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1552 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1553 struct platform_device *pdev = of_find_device_by_node(node); 1554 int ret; 1555 1556 if (!pdev) 1557 return -ENODEV; 1558 1559 gmu->dev = &pdev->dev; 1560 1561 of_dma_configure(gmu->dev, node, true); 1562 1563 /* Fow now, don't do anything fancy until we get our feet under us */ 1564 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; 1565 1566 pm_runtime_enable(gmu->dev); 1567 1568 /* Get the list of clocks */ 1569 ret = a6xx_gmu_clocks_probe(gmu); 1570 if (ret) 1571 goto err_put_device; 1572 1573 ret = a6xx_gmu_memory_probe(gmu); 1574 if (ret) 1575 goto err_put_device; 1576 1577 1578 /* A660 now requires handling "prealloc requests" in GMU firmware 1579 * For now just hardcode allocations based on the known firmware. 1580 * note: there is no indication that these correspond to "dummy" or 1581 * "debug" regions, but this "guess" allows reusing these BOs which 1582 * are otherwise unused by a660. 1583 */ 1584 gmu->dummy.size = SZ_4K; 1585 if (adreno_is_a660_family(adreno_gpu)) { 1586 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 1587 0x60400000, "debug"); 1588 if (ret) 1589 goto err_memory; 1590 1591 gmu->dummy.size = SZ_8K; 1592 } 1593 1594 /* Allocate memory for the GMU dummy page */ 1595 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 1596 0x60000000, "dummy"); 1597 if (ret) 1598 goto err_memory; 1599 1600 /* Note that a650 family also includes a660 family: */ 1601 if (adreno_is_a650_family(adreno_gpu)) { 1602 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1603 SZ_16M - SZ_16K, 0x04000, "icache"); 1604 if (ret) 1605 goto err_memory; 1606 /* 1607 * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition 1608 * to allocate icache/dcache here, as per downstream code flow, but it may not actually be 1609 * necessary. If you omit this step and you don't get random pagefaults, you are likely 1610 * good to go without this! 1611 */ 1612 } else if (adreno_is_a640_family(adreno_gpu)) { 1613 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, 1614 SZ_256K - SZ_16K, 0x04000, "icache"); 1615 if (ret) 1616 goto err_memory; 1617 1618 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache, 1619 SZ_256K - SZ_16K, 0x44000, "dcache"); 1620 if (ret) 1621 goto err_memory; 1622 } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) { 1623 /* HFI v1, has sptprac */ 1624 gmu->legacy = true; 1625 1626 /* Allocate memory for the GMU debug region */ 1627 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug"); 1628 if (ret) 1629 goto err_memory; 1630 } 1631 1632 /* Allocate memory for for the HFI queues */ 1633 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); 1634 if (ret) 1635 goto err_memory; 1636 1637 /* Allocate memory for the GMU log region */ 1638 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log"); 1639 if (ret) 1640 goto err_memory; 1641 1642 /* Map the GMU registers */ 1643 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); 1644 if (IS_ERR(gmu->mmio)) { 1645 ret = PTR_ERR(gmu->mmio); 1646 goto err_memory; 1647 } 1648 1649 if (adreno_is_a650_family(adreno_gpu)) { 1650 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); 1651 if (IS_ERR(gmu->rscc)) { 1652 ret = -ENODEV; 1653 goto err_mmio; 1654 } 1655 } else { 1656 gmu->rscc = gmu->mmio + 0x23000; 1657 } 1658 1659 /* Get the HFI and GMU interrupts */ 1660 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); 1661 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); 1662 1663 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) { 1664 ret = -ENODEV; 1665 goto err_mmio; 1666 } 1667 1668 gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx"); 1669 if (IS_ERR(gmu->cxpd)) { 1670 ret = PTR_ERR(gmu->cxpd); 1671 goto err_mmio; 1672 } 1673 1674 if (!device_link_add(gmu->dev, gmu->cxpd, 1675 DL_FLAG_PM_RUNTIME)) { 1676 ret = -ENODEV; 1677 goto detach_cxpd; 1678 } 1679 1680 init_completion(&gmu->pd_gate); 1681 complete_all(&gmu->pd_gate); 1682 gmu->pd_nb.notifier_call = cxpd_notifier_cb; 1683 1684 /* 1685 * Get a link to the GX power domain to reset the GPU in case of GMU 1686 * crash 1687 */ 1688 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); 1689 1690 /* Get the power levels for the GMU and GPU */ 1691 a6xx_gmu_pwrlevels_probe(gmu); 1692 1693 /* Set up the HFI queues */ 1694 a6xx_hfi_init(gmu); 1695 1696 /* Initialize RPMh */ 1697 a6xx_gmu_rpmh_init(gmu); 1698 1699 gmu->initialized = true; 1700 1701 return 0; 1702 1703 detach_cxpd: 1704 dev_pm_domain_detach(gmu->cxpd, false); 1705 1706 err_mmio: 1707 iounmap(gmu->mmio); 1708 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc")) 1709 iounmap(gmu->rscc); 1710 free_irq(gmu->gmu_irq, gmu); 1711 free_irq(gmu->hfi_irq, gmu); 1712 1713 err_memory: 1714 a6xx_gmu_memory_free(gmu); 1715 err_put_device: 1716 /* Drop reference taken in of_find_device_by_node */ 1717 put_device(gmu->dev); 1718 1719 return ret; 1720 } 1721