1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/hdmi.h> 11 #include <linux/i2c.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mutex.h> 16 #include <linux/of_platform.h> 17 #include <linux/of.h> 18 #include <linux/of_gpio.h> 19 #include <linux/of_graph.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 24 #include <sound/hdmi-codec.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_crtc.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_probe_helper.h> 32 33 #include "mtk_cec.h" 34 #include "mtk_hdmi.h" 35 #include "mtk_hdmi_regs.h" 36 37 #define NCTS_BYTES 7 38 39 enum mtk_hdmi_clk_id { 40 MTK_HDMI_CLK_HDMI_PIXEL, 41 MTK_HDMI_CLK_HDMI_PLL, 42 MTK_HDMI_CLK_AUD_BCLK, 43 MTK_HDMI_CLK_AUD_SPDIF, 44 MTK_HDMI_CLK_COUNT 45 }; 46 47 enum hdmi_aud_input_type { 48 HDMI_AUD_INPUT_I2S = 0, 49 HDMI_AUD_INPUT_SPDIF, 50 }; 51 52 enum hdmi_aud_i2s_fmt { 53 HDMI_I2S_MODE_RJT_24BIT = 0, 54 HDMI_I2S_MODE_RJT_16BIT, 55 HDMI_I2S_MODE_LJT_24BIT, 56 HDMI_I2S_MODE_LJT_16BIT, 57 HDMI_I2S_MODE_I2S_24BIT, 58 HDMI_I2S_MODE_I2S_16BIT 59 }; 60 61 enum hdmi_aud_mclk { 62 HDMI_AUD_MCLK_128FS, 63 HDMI_AUD_MCLK_192FS, 64 HDMI_AUD_MCLK_256FS, 65 HDMI_AUD_MCLK_384FS, 66 HDMI_AUD_MCLK_512FS, 67 HDMI_AUD_MCLK_768FS, 68 HDMI_AUD_MCLK_1152FS, 69 }; 70 71 enum hdmi_aud_channel_type { 72 HDMI_AUD_CHAN_TYPE_1_0 = 0, 73 HDMI_AUD_CHAN_TYPE_1_1, 74 HDMI_AUD_CHAN_TYPE_2_0, 75 HDMI_AUD_CHAN_TYPE_2_1, 76 HDMI_AUD_CHAN_TYPE_3_0, 77 HDMI_AUD_CHAN_TYPE_3_1, 78 HDMI_AUD_CHAN_TYPE_4_0, 79 HDMI_AUD_CHAN_TYPE_4_1, 80 HDMI_AUD_CHAN_TYPE_5_0, 81 HDMI_AUD_CHAN_TYPE_5_1, 82 HDMI_AUD_CHAN_TYPE_6_0, 83 HDMI_AUD_CHAN_TYPE_6_1, 84 HDMI_AUD_CHAN_TYPE_7_0, 85 HDMI_AUD_CHAN_TYPE_7_1, 86 HDMI_AUD_CHAN_TYPE_3_0_LRS, 87 HDMI_AUD_CHAN_TYPE_3_1_LRS, 88 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 89 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 90 HDMI_AUD_CHAN_TYPE_6_1_CS, 91 HDMI_AUD_CHAN_TYPE_6_1_CH, 92 HDMI_AUD_CHAN_TYPE_6_1_OH, 93 HDMI_AUD_CHAN_TYPE_6_1_CHR, 94 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 95 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 96 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 97 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 98 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 99 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 100 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 101 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 102 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 103 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 104 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 105 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 106 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 107 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 108 HDMI_AUD_CHAN_TYPE_6_0_CS, 109 HDMI_AUD_CHAN_TYPE_6_0_CH, 110 HDMI_AUD_CHAN_TYPE_6_0_OH, 111 HDMI_AUD_CHAN_TYPE_6_0_CHR, 112 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 113 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 114 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 115 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 116 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 117 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 118 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 119 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 120 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 121 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 122 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 123 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 124 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 125 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 126 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 127 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 128 }; 129 130 enum hdmi_aud_channel_swap_type { 131 HDMI_AUD_SWAP_LR, 132 HDMI_AUD_SWAP_LFE_CC, 133 HDMI_AUD_SWAP_LSRS, 134 HDMI_AUD_SWAP_RLS_RRS, 135 HDMI_AUD_SWAP_LR_STATUS, 136 }; 137 138 struct hdmi_audio_param { 139 enum hdmi_audio_coding_type aud_codec; 140 enum hdmi_audio_sample_size aud_sampe_size; 141 enum hdmi_aud_input_type aud_input_type; 142 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 143 enum hdmi_aud_mclk aud_mclk; 144 enum hdmi_aud_channel_type aud_input_chan_type; 145 struct hdmi_codec_params codec_params; 146 }; 147 148 struct mtk_hdmi { 149 struct drm_bridge bridge; 150 struct drm_bridge *next_bridge; 151 struct drm_connector conn; 152 struct device *dev; 153 struct phy *phy; 154 struct device *cec_dev; 155 struct i2c_adapter *ddc_adpt; 156 struct clk *clk[MTK_HDMI_CLK_COUNT]; 157 struct drm_display_mode mode; 158 bool dvi_mode; 159 u32 min_clock; 160 u32 max_clock; 161 u32 max_hdisplay; 162 u32 max_vdisplay; 163 u32 ibias; 164 u32 ibias_up; 165 struct regmap *sys_regmap; 166 unsigned int sys_offset; 167 void __iomem *regs; 168 enum hdmi_colorspace csp; 169 struct hdmi_audio_param aud_param; 170 bool audio_enable; 171 bool powered; 172 bool enabled; 173 hdmi_codec_plugged_cb plugged_cb; 174 struct device *codec_dev; 175 struct mutex update_plugged_status_lock; 176 }; 177 178 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 179 { 180 return container_of(b, struct mtk_hdmi, bridge); 181 } 182 183 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) 184 { 185 return container_of(c, struct mtk_hdmi, conn); 186 } 187 188 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 189 { 190 return readl(hdmi->regs + offset); 191 } 192 193 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 194 { 195 writel(val, hdmi->regs + offset); 196 } 197 198 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 199 { 200 void __iomem *reg = hdmi->regs + offset; 201 u32 tmp; 202 203 tmp = readl(reg); 204 tmp &= ~bits; 205 writel(tmp, reg); 206 } 207 208 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 209 { 210 void __iomem *reg = hdmi->regs + offset; 211 u32 tmp; 212 213 tmp = readl(reg); 214 tmp |= bits; 215 writel(tmp, reg); 216 } 217 218 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 219 { 220 void __iomem *reg = hdmi->regs + offset; 221 u32 tmp; 222 223 tmp = readl(reg); 224 tmp = (tmp & ~mask) | (val & mask); 225 writel(tmp, reg); 226 } 227 228 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 229 { 230 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 231 VIDEO_SOURCE_SEL); 232 } 233 234 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 235 { 236 struct arm_smccc_res res; 237 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy); 238 239 /* 240 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 241 * output. This bit can only be controlled in ARM supervisor mode. 242 * The ARM trusted firmware provides an API for the HDMI driver to set 243 * this control bit to enable HDMI output in supervisor mode. 244 */ 245 if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) 246 regmap_update_bits(hdmi->sys_regmap, 247 hdmi->sys_offset + HDMI_SYS_CFG20, 248 0x80008005, enable ? 0x80000005 : 0x8000); 249 else 250 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 251 0x80000000, 0, 0, 0, 0, 0, &res); 252 253 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 254 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 255 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 256 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 257 } 258 259 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 260 { 261 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 262 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 263 } 264 265 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 266 { 267 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 268 } 269 270 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 271 { 272 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 273 } 274 275 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 276 { 277 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 278 HDMI_RST, HDMI_RST); 279 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 280 HDMI_RST, 0); 281 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 282 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 283 ANLG_ON, ANLG_ON); 284 } 285 286 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 287 { 288 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 289 CFG2_NOTICE_EN); 290 } 291 292 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 293 { 294 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 295 } 296 297 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 298 { 299 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 300 } 301 302 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 303 u8 len) 304 { 305 u32 ctrl_reg = GRL_CTRL; 306 int i; 307 u8 *frame_data; 308 enum hdmi_infoframe_type frame_type; 309 u8 frame_ver; 310 u8 frame_len; 311 u8 checksum; 312 int ctrl_frame_en = 0; 313 314 frame_type = *buffer; 315 buffer += 1; 316 frame_ver = *buffer; 317 buffer += 1; 318 frame_len = *buffer; 319 buffer += 1; 320 checksum = *buffer; 321 buffer += 1; 322 frame_data = buffer; 323 324 dev_dbg(hdmi->dev, 325 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 326 frame_type, frame_ver, frame_len, checksum); 327 328 switch (frame_type) { 329 case HDMI_INFOFRAME_TYPE_AVI: 330 ctrl_frame_en = CTRL_AVI_EN; 331 ctrl_reg = GRL_CTRL; 332 break; 333 case HDMI_INFOFRAME_TYPE_SPD: 334 ctrl_frame_en = CTRL_SPD_EN; 335 ctrl_reg = GRL_CTRL; 336 break; 337 case HDMI_INFOFRAME_TYPE_AUDIO: 338 ctrl_frame_en = CTRL_AUDIO_EN; 339 ctrl_reg = GRL_CTRL; 340 break; 341 case HDMI_INFOFRAME_TYPE_VENDOR: 342 ctrl_frame_en = VS_EN; 343 ctrl_reg = GRL_ACP_ISRC_CTRL; 344 break; 345 default: 346 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 347 return; 348 } 349 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 350 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 351 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 352 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 353 354 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 355 for (i = 0; i < frame_len; i++) 356 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 357 358 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 359 } 360 361 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 362 { 363 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 364 AUDIO_PACKET_OFF); 365 } 366 367 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 368 { 369 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 370 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 371 usleep_range(2000, 4000); 372 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 373 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 374 } 375 376 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 377 { 378 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 379 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 380 COLOR_8BIT_MODE); 381 } 382 383 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 384 { 385 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 386 usleep_range(2000, 4000); 387 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 388 } 389 390 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 391 { 392 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 393 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 394 usleep_range(2000, 4000); 395 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 396 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 397 } 398 399 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 400 { 401 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 402 CTS_CTRL_SOFT); 403 } 404 405 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 406 bool enable) 407 { 408 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 409 NCTS_WRI_ANYTIME); 410 } 411 412 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 413 struct drm_display_mode *mode) 414 { 415 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 416 417 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 418 mode->clock == 74250 && 419 mode->vdisplay == 1080) 420 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 421 else 422 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 423 } 424 425 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 426 enum hdmi_aud_channel_swap_type swap) 427 { 428 u8 swap_bit; 429 430 switch (swap) { 431 case HDMI_AUD_SWAP_LR: 432 swap_bit = LR_SWAP; 433 break; 434 case HDMI_AUD_SWAP_LFE_CC: 435 swap_bit = LFE_CC_SWAP; 436 break; 437 case HDMI_AUD_SWAP_LSRS: 438 swap_bit = LSRS_SWAP; 439 break; 440 case HDMI_AUD_SWAP_RLS_RRS: 441 swap_bit = RLS_RRS_SWAP; 442 break; 443 case HDMI_AUD_SWAP_LR_STATUS: 444 swap_bit = LR_STATUS_SWAP; 445 break; 446 default: 447 swap_bit = LFE_CC_SWAP; 448 break; 449 } 450 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 451 } 452 453 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 454 enum hdmi_audio_sample_size bit_num) 455 { 456 u32 val; 457 458 switch (bit_num) { 459 case HDMI_AUDIO_SAMPLE_SIZE_16: 460 val = AOUT_16BIT; 461 break; 462 case HDMI_AUDIO_SAMPLE_SIZE_20: 463 val = AOUT_20BIT; 464 break; 465 case HDMI_AUDIO_SAMPLE_SIZE_24: 466 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 467 val = AOUT_24BIT; 468 break; 469 } 470 471 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 472 } 473 474 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 475 enum hdmi_aud_i2s_fmt i2s_fmt) 476 { 477 u32 val; 478 479 val = mtk_hdmi_read(hdmi, GRL_CFG0); 480 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 481 482 switch (i2s_fmt) { 483 case HDMI_I2S_MODE_RJT_24BIT: 484 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 485 break; 486 case HDMI_I2S_MODE_RJT_16BIT: 487 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 488 break; 489 case HDMI_I2S_MODE_LJT_24BIT: 490 default: 491 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 492 break; 493 case HDMI_I2S_MODE_LJT_16BIT: 494 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 495 break; 496 case HDMI_I2S_MODE_I2S_24BIT: 497 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 498 break; 499 case HDMI_I2S_MODE_I2S_16BIT: 500 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 501 break; 502 } 503 mtk_hdmi_write(hdmi, GRL_CFG0, val); 504 } 505 506 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 507 { 508 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 509 u8 val; 510 511 /* Disable high bitrate, set DST packet normal/double */ 512 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 513 514 if (dst) 515 val = DST_NORMAL_DOUBLE | SACD_DST; 516 else 517 val = 0; 518 519 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 520 } 521 522 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 523 enum hdmi_aud_channel_type channel_type, 524 u8 channel_count) 525 { 526 unsigned int ch_switch; 527 u8 i2s_uv; 528 529 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 530 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 531 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 532 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 533 534 if (channel_count == 2) { 535 i2s_uv = I2S_UV_CH_EN(0); 536 } else if (channel_count == 3 || channel_count == 4) { 537 if (channel_count == 4 && 538 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 539 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 540 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 541 else 542 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 543 } else if (channel_count == 6 || channel_count == 5) { 544 if (channel_count == 6 && 545 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 546 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 547 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 548 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 549 } else { 550 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 551 I2S_UV_CH_EN(0); 552 } 553 } else if (channel_count == 8 || channel_count == 7) { 554 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 555 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 556 } else { 557 i2s_uv = I2S_UV_CH_EN(0); 558 } 559 560 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 561 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 562 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 563 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 564 } 565 566 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 567 enum hdmi_aud_input_type input_type) 568 { 569 u32 val; 570 571 val = mtk_hdmi_read(hdmi, GRL_CFG1); 572 if (input_type == HDMI_AUD_INPUT_I2S && 573 (val & CFG1_SPDIF) == CFG1_SPDIF) { 574 val &= ~CFG1_SPDIF; 575 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 576 (val & CFG1_SPDIF) == 0) { 577 val |= CFG1_SPDIF; 578 } 579 mtk_hdmi_write(hdmi, GRL_CFG1, val); 580 } 581 582 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 583 u8 *channel_status) 584 { 585 int i; 586 587 for (i = 0; i < 5; i++) { 588 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 589 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 590 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 591 } 592 for (; i < 24; i++) { 593 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 594 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 595 } 596 } 597 598 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 599 { 600 u32 val; 601 602 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 603 if (val & MIX_CTRL_SRC_EN) { 604 val &= ~MIX_CTRL_SRC_EN; 605 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 606 usleep_range(255, 512); 607 val |= MIX_CTRL_SRC_EN; 608 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 609 } 610 } 611 612 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 613 { 614 u32 val; 615 616 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 617 val &= ~MIX_CTRL_SRC_EN; 618 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 619 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 620 } 621 622 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 623 enum hdmi_aud_mclk mclk) 624 { 625 u32 val; 626 627 val = mtk_hdmi_read(hdmi, GRL_CFG5); 628 val &= CFG5_CD_RATIO_MASK; 629 630 switch (mclk) { 631 case HDMI_AUD_MCLK_128FS: 632 val |= CFG5_FS128; 633 break; 634 case HDMI_AUD_MCLK_256FS: 635 val |= CFG5_FS256; 636 break; 637 case HDMI_AUD_MCLK_384FS: 638 val |= CFG5_FS384; 639 break; 640 case HDMI_AUD_MCLK_512FS: 641 val |= CFG5_FS512; 642 break; 643 case HDMI_AUD_MCLK_768FS: 644 val |= CFG5_FS768; 645 break; 646 default: 647 val |= CFG5_FS256; 648 break; 649 } 650 mtk_hdmi_write(hdmi, GRL_CFG5, val); 651 } 652 653 struct hdmi_acr_n { 654 unsigned int clock; 655 unsigned int n[3]; 656 }; 657 658 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 659 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 660 /* Clock, N: 32kHz 44.1kHz 48kHz */ 661 { 25175, { 4576, 7007, 6864 } }, 662 { 74176, { 11648, 17836, 11648 } }, 663 { 148352, { 11648, 8918, 5824 } }, 664 { 296703, { 5824, 4459, 5824 } }, 665 { 297000, { 3072, 4704, 5120 } }, 666 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 667 }; 668 669 /** 670 * hdmi_recommended_n() - Return N value recommended by HDMI specification 671 * @freq: audio sample rate in Hz 672 * @clock: rounded TMDS clock in kHz 673 */ 674 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 675 { 676 const struct hdmi_acr_n *recommended; 677 unsigned int i; 678 679 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 680 if (clock == hdmi_rec_n_table[i].clock) 681 break; 682 } 683 recommended = hdmi_rec_n_table + i; 684 685 switch (freq) { 686 case 32000: 687 return recommended->n[0]; 688 case 44100: 689 return recommended->n[1]; 690 case 48000: 691 return recommended->n[2]; 692 case 88200: 693 return recommended->n[1] * 2; 694 case 96000: 695 return recommended->n[2] * 2; 696 case 176400: 697 return recommended->n[1] * 4; 698 case 192000: 699 return recommended->n[2] * 4; 700 default: 701 return (128 * freq) / 1000; 702 } 703 } 704 705 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 706 { 707 switch (clock) { 708 case 25175: 709 return 25174825; /* 25.2/1.001 MHz */ 710 case 74176: 711 return 74175824; /* 74.25/1.001 MHz */ 712 case 148352: 713 return 148351648; /* 148.5/1.001 MHz */ 714 case 296703: 715 return 296703297; /* 297/1.001 MHz */ 716 default: 717 return clock * 1000; 718 } 719 } 720 721 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 722 unsigned int tmds_clock, unsigned int n) 723 { 724 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 725 128 * audio_sample_rate); 726 } 727 728 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 729 unsigned int cts) 730 { 731 unsigned char val[NCTS_BYTES]; 732 int i; 733 734 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 735 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 736 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 737 memset(val, 0, sizeof(val)); 738 739 val[0] = (cts >> 24) & 0xff; 740 val[1] = (cts >> 16) & 0xff; 741 val[2] = (cts >> 8) & 0xff; 742 val[3] = cts & 0xff; 743 744 val[4] = (n >> 16) & 0xff; 745 val[5] = (n >> 8) & 0xff; 746 val[6] = n & 0xff; 747 748 for (i = 0; i < NCTS_BYTES; i++) 749 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 750 } 751 752 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 753 unsigned int sample_rate, 754 unsigned int clock) 755 { 756 unsigned int n, cts; 757 758 n = hdmi_recommended_n(sample_rate, clock); 759 cts = hdmi_expected_cts(sample_rate, clock, n); 760 761 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 762 __func__, sample_rate, clock, n, cts); 763 764 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 765 AUDIO_I2S_NCTS_SEL); 766 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 767 } 768 769 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 770 { 771 switch (channel_type) { 772 case HDMI_AUD_CHAN_TYPE_1_0: 773 case HDMI_AUD_CHAN_TYPE_1_1: 774 case HDMI_AUD_CHAN_TYPE_2_0: 775 return 2; 776 case HDMI_AUD_CHAN_TYPE_2_1: 777 case HDMI_AUD_CHAN_TYPE_3_0: 778 return 3; 779 case HDMI_AUD_CHAN_TYPE_3_1: 780 case HDMI_AUD_CHAN_TYPE_4_0: 781 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 782 return 4; 783 case HDMI_AUD_CHAN_TYPE_4_1: 784 case HDMI_AUD_CHAN_TYPE_5_0: 785 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 786 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 787 return 5; 788 case HDMI_AUD_CHAN_TYPE_5_1: 789 case HDMI_AUD_CHAN_TYPE_6_0: 790 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 791 case HDMI_AUD_CHAN_TYPE_6_0_CS: 792 case HDMI_AUD_CHAN_TYPE_6_0_CH: 793 case HDMI_AUD_CHAN_TYPE_6_0_OH: 794 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 795 return 6; 796 case HDMI_AUD_CHAN_TYPE_6_1: 797 case HDMI_AUD_CHAN_TYPE_6_1_CS: 798 case HDMI_AUD_CHAN_TYPE_6_1_CH: 799 case HDMI_AUD_CHAN_TYPE_6_1_OH: 800 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 801 case HDMI_AUD_CHAN_TYPE_7_0: 802 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 803 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 804 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 805 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 806 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 807 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 808 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 809 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 810 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 811 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 812 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 813 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 814 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 815 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 816 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 817 return 7; 818 case HDMI_AUD_CHAN_TYPE_7_1: 819 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 820 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 821 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 822 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 823 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 824 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 825 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 826 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 827 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 828 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 829 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 830 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 831 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 832 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 833 return 8; 834 default: 835 return 2; 836 } 837 } 838 839 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 840 { 841 unsigned long rate; 842 int ret; 843 844 /* The DPI driver already should have set TVDPLL to the correct rate */ 845 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 846 if (ret) { 847 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 848 ret); 849 return ret; 850 } 851 852 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 853 854 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 855 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 856 rate); 857 else 858 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 859 860 mtk_hdmi_hw_config_sys(hdmi); 861 mtk_hdmi_hw_set_deep_color_mode(hdmi); 862 return 0; 863 } 864 865 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 866 struct drm_display_mode *mode) 867 { 868 mtk_hdmi_hw_reset(hdmi); 869 mtk_hdmi_hw_enable_notice(hdmi, true); 870 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 871 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 872 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 873 874 mtk_hdmi_hw_msic_setting(hdmi, mode); 875 } 876 877 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable) 878 { 879 mtk_hdmi_hw_send_aud_packet(hdmi, enable); 880 return 0; 881 } 882 883 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on) 884 { 885 mtk_hdmi_hw_ncts_enable(hdmi, on); 886 return 0; 887 } 888 889 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 890 { 891 enum hdmi_aud_channel_type chan_type; 892 u8 chan_count; 893 bool dst; 894 895 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 896 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 897 898 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 899 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 900 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 901 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 902 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 903 } 904 905 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 906 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 907 908 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 909 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 910 mtk_hdmi_hw_audio_config(hdmi, dst); 911 912 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 913 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 914 else 915 chan_type = hdmi->aud_param.aud_input_chan_type; 916 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 917 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 918 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 919 920 return 0; 921 } 922 923 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 924 struct drm_display_mode *display_mode) 925 { 926 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 927 928 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false); 929 mtk_hdmi_hw_aud_src_disable(hdmi); 930 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 931 932 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 933 switch (sample_rate) { 934 case 32000: 935 case 44100: 936 case 48000: 937 case 88200: 938 case 96000: 939 break; 940 default: 941 return -EINVAL; 942 } 943 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 944 } else { 945 switch (sample_rate) { 946 case 32000: 947 case 44100: 948 case 48000: 949 break; 950 default: 951 return -EINVAL; 952 } 953 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 954 } 955 956 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 957 958 mtk_hdmi_hw_aud_src_reenable(hdmi); 959 return 0; 960 } 961 962 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 963 struct drm_display_mode *display_mode) 964 { 965 mtk_hdmi_hw_aud_mute(hdmi); 966 mtk_hdmi_aud_enable_packet(hdmi, false); 967 968 mtk_hdmi_aud_set_input(hdmi); 969 mtk_hdmi_aud_set_src(hdmi, display_mode); 970 mtk_hdmi_hw_aud_set_channel_status(hdmi, 971 hdmi->aud_param.codec_params.iec.status); 972 973 usleep_range(50, 100); 974 975 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true); 976 mtk_hdmi_aud_enable_packet(hdmi, true); 977 mtk_hdmi_hw_aud_unmute(hdmi); 978 return 0; 979 } 980 981 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 982 struct drm_display_mode *mode) 983 { 984 struct hdmi_avi_infoframe frame; 985 u8 buffer[17]; 986 ssize_t err; 987 988 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 989 &hdmi->conn, mode); 990 if (err < 0) { 991 dev_err(hdmi->dev, 992 "Failed to get AVI infoframe from mode: %zd\n", err); 993 return err; 994 } 995 996 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 997 if (err < 0) { 998 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 999 return err; 1000 } 1001 1002 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1003 return 0; 1004 } 1005 1006 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 1007 const char *vendor, 1008 const char *product) 1009 { 1010 struct hdmi_spd_infoframe frame; 1011 u8 buffer[29]; 1012 ssize_t err; 1013 1014 err = hdmi_spd_infoframe_init(&frame, vendor, product); 1015 if (err < 0) { 1016 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 1017 err); 1018 return err; 1019 } 1020 1021 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 1022 if (err < 0) { 1023 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1024 return err; 1025 } 1026 1027 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1028 return 0; 1029 } 1030 1031 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1032 { 1033 struct hdmi_audio_infoframe frame; 1034 u8 buffer[14]; 1035 ssize_t err; 1036 1037 err = hdmi_audio_infoframe_init(&frame); 1038 if (err < 0) { 1039 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1040 err); 1041 return err; 1042 } 1043 1044 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1045 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1046 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1047 frame.channels = mtk_hdmi_aud_get_chnl_count( 1048 hdmi->aud_param.aud_input_chan_type); 1049 1050 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1051 if (err < 0) { 1052 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1053 err); 1054 return err; 1055 } 1056 1057 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1058 return 0; 1059 } 1060 1061 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1062 struct drm_display_mode *mode) 1063 { 1064 struct hdmi_vendor_infoframe frame; 1065 u8 buffer[10]; 1066 ssize_t err; 1067 1068 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1069 &hdmi->conn, mode); 1070 if (err) { 1071 dev_err(hdmi->dev, 1072 "Failed to get vendor infoframe from mode: %zd\n", err); 1073 return err; 1074 } 1075 1076 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1077 if (err < 0) { 1078 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1079 err); 1080 return err; 1081 } 1082 1083 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1084 return 0; 1085 } 1086 1087 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1088 { 1089 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1090 1091 hdmi->csp = HDMI_COLORSPACE_RGB; 1092 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1093 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1094 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1095 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1096 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1097 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1098 1099 return 0; 1100 } 1101 1102 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1103 { 1104 mtk_hdmi_aud_enable_packet(hdmi, true); 1105 hdmi->audio_enable = true; 1106 } 1107 1108 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1109 { 1110 mtk_hdmi_aud_enable_packet(hdmi, false); 1111 hdmi->audio_enable = false; 1112 } 1113 1114 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1115 struct hdmi_audio_param *param) 1116 { 1117 if (!hdmi->audio_enable) { 1118 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1119 return -EINVAL; 1120 } 1121 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1122 param->aud_codec, param->aud_input_type, 1123 param->aud_input_chan_type, param->codec_params.sample_rate); 1124 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1125 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1126 } 1127 1128 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1129 struct drm_display_mode *mode) 1130 { 1131 int ret; 1132 1133 mtk_hdmi_hw_vid_black(hdmi, true); 1134 mtk_hdmi_hw_aud_mute(hdmi); 1135 mtk_hdmi_hw_send_av_mute(hdmi); 1136 phy_power_off(hdmi->phy); 1137 1138 ret = mtk_hdmi_video_change_vpll(hdmi, 1139 mode->clock * 1000); 1140 if (ret) { 1141 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1142 return ret; 1143 } 1144 mtk_hdmi_video_set_display_mode(hdmi, mode); 1145 1146 phy_power_on(hdmi->phy); 1147 mtk_hdmi_aud_output_config(hdmi, mode); 1148 1149 mtk_hdmi_hw_vid_black(hdmi, false); 1150 mtk_hdmi_hw_aud_unmute(hdmi); 1151 mtk_hdmi_hw_send_av_unmute(hdmi); 1152 1153 return 0; 1154 } 1155 1156 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1157 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1158 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1159 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1160 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1161 }; 1162 1163 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1164 struct device_node *np) 1165 { 1166 int i; 1167 1168 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1169 hdmi->clk[i] = of_clk_get_by_name(np, 1170 mtk_hdmi_clk_names[i]); 1171 if (IS_ERR(hdmi->clk[i])) 1172 return PTR_ERR(hdmi->clk[i]); 1173 } 1174 return 0; 1175 } 1176 1177 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1178 { 1179 int ret; 1180 1181 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1182 if (ret) 1183 return ret; 1184 1185 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1186 if (ret) 1187 goto err; 1188 1189 return 0; 1190 err: 1191 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1192 return ret; 1193 } 1194 1195 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1196 { 1197 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1198 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1199 } 1200 1201 static enum drm_connector_status 1202 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) 1203 { 1204 bool connected; 1205 1206 mutex_lock(&hdmi->update_plugged_status_lock); 1207 connected = mtk_cec_hpd_high(hdmi->cec_dev); 1208 if (hdmi->plugged_cb && hdmi->codec_dev) 1209 hdmi->plugged_cb(hdmi->codec_dev, connected); 1210 mutex_unlock(&hdmi->update_plugged_status_lock); 1211 1212 return connected ? 1213 connector_status_connected : connector_status_disconnected; 1214 } 1215 1216 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, 1217 bool force) 1218 { 1219 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1220 return mtk_hdmi_update_plugged_status(hdmi); 1221 } 1222 1223 static void hdmi_conn_destroy(struct drm_connector *conn) 1224 { 1225 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1226 1227 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); 1228 1229 drm_connector_cleanup(conn); 1230 } 1231 1232 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) 1233 { 1234 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1235 struct edid *edid; 1236 int ret; 1237 1238 if (!hdmi->ddc_adpt) 1239 return -ENODEV; 1240 1241 edid = drm_get_edid(conn, hdmi->ddc_adpt); 1242 if (!edid) 1243 return -ENODEV; 1244 1245 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1246 1247 drm_connector_update_edid_property(conn, edid); 1248 1249 ret = drm_add_edid_modes(conn, edid); 1250 kfree(edid); 1251 return ret; 1252 } 1253 1254 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, 1255 struct drm_display_mode *mode) 1256 { 1257 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1258 struct drm_bridge *next_bridge; 1259 1260 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1261 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1262 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1263 1264 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge); 1265 if (next_bridge) { 1266 struct drm_display_mode adjusted_mode; 1267 1268 drm_mode_copy(&adjusted_mode, mode); 1269 if (!drm_bridge_chain_mode_fixup(next_bridge, mode, 1270 &adjusted_mode)) 1271 return MODE_BAD; 1272 } 1273 1274 if (mode->clock < 27000) 1275 return MODE_CLOCK_LOW; 1276 if (mode->clock > 297000) 1277 return MODE_CLOCK_HIGH; 1278 1279 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1280 } 1281 1282 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) 1283 { 1284 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1285 1286 return hdmi->bridge.encoder; 1287 } 1288 1289 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { 1290 .detect = hdmi_conn_detect, 1291 .fill_modes = drm_helper_probe_single_connector_modes, 1292 .destroy = hdmi_conn_destroy, 1293 .reset = drm_atomic_helper_connector_reset, 1294 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1295 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1296 }; 1297 1298 static const struct drm_connector_helper_funcs 1299 mtk_hdmi_connector_helper_funcs = { 1300 .get_modes = mtk_hdmi_conn_get_modes, 1301 .mode_valid = mtk_hdmi_conn_mode_valid, 1302 .best_encoder = mtk_hdmi_conn_best_enc, 1303 }; 1304 1305 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1306 { 1307 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1308 1309 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) 1310 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1311 } 1312 1313 /* 1314 * Bridge callbacks 1315 */ 1316 1317 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge) 1318 { 1319 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1320 int ret; 1321 1322 ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn, 1323 &mtk_hdmi_connector_funcs, 1324 DRM_MODE_CONNECTOR_HDMIA, 1325 hdmi->ddc_adpt); 1326 if (ret) { 1327 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); 1328 return ret; 1329 } 1330 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); 1331 1332 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; 1333 hdmi->conn.interlace_allowed = true; 1334 hdmi->conn.doublescan_allowed = false; 1335 1336 ret = drm_connector_attach_encoder(&hdmi->conn, 1337 bridge->encoder); 1338 if (ret) { 1339 dev_err(hdmi->dev, 1340 "Failed to attach connector to encoder: %d\n", ret); 1341 return ret; 1342 } 1343 1344 if (hdmi->next_bridge) { 1345 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1346 bridge); 1347 if (ret) { 1348 dev_err(hdmi->dev, 1349 "Failed to attach external bridge: %d\n", ret); 1350 return ret; 1351 } 1352 } 1353 1354 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1355 1356 return 0; 1357 } 1358 1359 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1360 const struct drm_display_mode *mode, 1361 struct drm_display_mode *adjusted_mode) 1362 { 1363 return true; 1364 } 1365 1366 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) 1367 { 1368 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1369 1370 if (!hdmi->enabled) 1371 return; 1372 1373 phy_power_off(hdmi->phy); 1374 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1375 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1376 1377 hdmi->enabled = false; 1378 } 1379 1380 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) 1381 { 1382 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1383 1384 if (!hdmi->powered) 1385 return; 1386 1387 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1388 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1389 1390 hdmi->powered = false; 1391 } 1392 1393 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1394 const struct drm_display_mode *mode, 1395 const struct drm_display_mode *adjusted_mode) 1396 { 1397 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1398 1399 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1400 adjusted_mode->name, adjusted_mode->hdisplay); 1401 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1402 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1403 adjusted_mode->htotal); 1404 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1405 adjusted_mode->hskew, adjusted_mode->vdisplay); 1406 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1407 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1408 adjusted_mode->vtotal); 1409 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1410 adjusted_mode->vscan, adjusted_mode->flags); 1411 1412 drm_mode_copy(&hdmi->mode, adjusted_mode); 1413 } 1414 1415 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 1416 { 1417 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1418 1419 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1420 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1421 1422 hdmi->powered = true; 1423 } 1424 1425 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1426 struct drm_display_mode *mode) 1427 { 1428 mtk_hdmi_setup_audio_infoframe(hdmi); 1429 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1430 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1431 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1432 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1433 } 1434 1435 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1436 { 1437 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1438 1439 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1440 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1441 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1442 phy_power_on(hdmi->phy); 1443 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1444 1445 hdmi->enabled = true; 1446 } 1447 1448 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1449 .attach = mtk_hdmi_bridge_attach, 1450 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1451 .disable = mtk_hdmi_bridge_disable, 1452 .post_disable = mtk_hdmi_bridge_post_disable, 1453 .mode_set = mtk_hdmi_bridge_mode_set, 1454 .pre_enable = mtk_hdmi_bridge_pre_enable, 1455 .enable = mtk_hdmi_bridge_enable, 1456 }; 1457 1458 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1459 struct platform_device *pdev) 1460 { 1461 struct device *dev = &pdev->dev; 1462 struct device_node *np = dev->of_node; 1463 struct device_node *cec_np, *remote, *i2c_np; 1464 struct platform_device *cec_pdev; 1465 struct regmap *regmap; 1466 struct resource *mem; 1467 int ret; 1468 1469 ret = mtk_hdmi_get_all_clk(hdmi, np); 1470 if (ret) { 1471 dev_err(dev, "Failed to get clocks: %d\n", ret); 1472 return ret; 1473 } 1474 1475 /* The CEC module handles HDMI hotplug detection */ 1476 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); 1477 if (!cec_np) { 1478 dev_err(dev, "Failed to find CEC node\n"); 1479 return -EINVAL; 1480 } 1481 1482 cec_pdev = of_find_device_by_node(cec_np); 1483 if (!cec_pdev) { 1484 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1485 cec_np); 1486 of_node_put(cec_np); 1487 return -EPROBE_DEFER; 1488 } 1489 of_node_put(cec_np); 1490 hdmi->cec_dev = &cec_pdev->dev; 1491 1492 /* 1493 * The mediatek,syscon-hdmi property contains a phandle link to the 1494 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1495 * registers it contains. 1496 */ 1497 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1498 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1499 &hdmi->sys_offset); 1500 if (IS_ERR(regmap)) 1501 ret = PTR_ERR(regmap); 1502 if (ret) { 1503 dev_err(dev, 1504 "Failed to get system configuration registers: %d\n", 1505 ret); 1506 return ret; 1507 } 1508 hdmi->sys_regmap = regmap; 1509 1510 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1511 hdmi->regs = devm_ioremap_resource(dev, mem); 1512 if (IS_ERR(hdmi->regs)) 1513 return PTR_ERR(hdmi->regs); 1514 1515 remote = of_graph_get_remote_node(np, 1, 0); 1516 if (!remote) 1517 return -EINVAL; 1518 1519 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1520 hdmi->next_bridge = of_drm_find_bridge(remote); 1521 if (!hdmi->next_bridge) { 1522 dev_err(dev, "Waiting for external bridge\n"); 1523 of_node_put(remote); 1524 return -EPROBE_DEFER; 1525 } 1526 } 1527 1528 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1529 if (!i2c_np) { 1530 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1531 remote); 1532 of_node_put(remote); 1533 return -EINVAL; 1534 } 1535 of_node_put(remote); 1536 1537 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1538 of_node_put(i2c_np); 1539 if (!hdmi->ddc_adpt) { 1540 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1541 return -EINVAL; 1542 } 1543 1544 return 0; 1545 } 1546 1547 /* 1548 * HDMI audio codec callbacks 1549 */ 1550 1551 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1552 struct hdmi_codec_daifmt *daifmt, 1553 struct hdmi_codec_params *params) 1554 { 1555 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1556 struct hdmi_audio_param hdmi_params; 1557 unsigned int chan = params->cea.channels; 1558 1559 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1560 params->sample_rate, params->sample_width, chan); 1561 1562 if (!hdmi->bridge.encoder) 1563 return -ENODEV; 1564 1565 switch (chan) { 1566 case 2: 1567 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1568 break; 1569 case 4: 1570 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1571 break; 1572 case 6: 1573 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1574 break; 1575 case 8: 1576 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1577 break; 1578 default: 1579 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1580 return -EINVAL; 1581 } 1582 1583 switch (params->sample_rate) { 1584 case 32000: 1585 case 44100: 1586 case 48000: 1587 case 88200: 1588 case 96000: 1589 case 176400: 1590 case 192000: 1591 break; 1592 default: 1593 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1594 params->sample_rate); 1595 return -EINVAL; 1596 } 1597 1598 switch (daifmt->fmt) { 1599 case HDMI_I2S: 1600 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1601 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1602 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1603 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1604 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1605 break; 1606 case HDMI_SPDIF: 1607 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1608 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1609 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1610 break; 1611 default: 1612 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1613 daifmt->fmt); 1614 return -EINVAL; 1615 } 1616 1617 memcpy(&hdmi_params.codec_params, params, 1618 sizeof(hdmi_params.codec_params)); 1619 1620 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1621 1622 return 0; 1623 } 1624 1625 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1626 { 1627 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1628 1629 dev_dbg(dev, "%s\n", __func__); 1630 1631 mtk_hdmi_audio_enable(hdmi); 1632 1633 return 0; 1634 } 1635 1636 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1637 { 1638 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1639 1640 dev_dbg(dev, "%s\n", __func__); 1641 1642 mtk_hdmi_audio_disable(hdmi); 1643 } 1644 1645 static int 1646 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) 1647 { 1648 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1649 1650 dev_dbg(dev, "%s(%d)\n", __func__, enable); 1651 1652 if (enable) 1653 mtk_hdmi_hw_aud_mute(hdmi); 1654 else 1655 mtk_hdmi_hw_aud_unmute(hdmi); 1656 1657 return 0; 1658 } 1659 1660 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1661 { 1662 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1663 1664 dev_dbg(dev, "%s\n", __func__); 1665 1666 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); 1667 1668 return 0; 1669 } 1670 1671 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, 1672 hdmi_codec_plugged_cb fn, 1673 struct device *codec_dev) 1674 { 1675 struct mtk_hdmi *hdmi = data; 1676 1677 mutex_lock(&hdmi->update_plugged_status_lock); 1678 hdmi->plugged_cb = fn; 1679 hdmi->codec_dev = codec_dev; 1680 mutex_unlock(&hdmi->update_plugged_status_lock); 1681 1682 mtk_hdmi_update_plugged_status(hdmi); 1683 1684 return 0; 1685 } 1686 1687 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1688 .hw_params = mtk_hdmi_audio_hw_params, 1689 .audio_startup = mtk_hdmi_audio_startup, 1690 .audio_shutdown = mtk_hdmi_audio_shutdown, 1691 .digital_mute = mtk_hdmi_audio_digital_mute, 1692 .get_eld = mtk_hdmi_audio_get_eld, 1693 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1694 }; 1695 1696 static int mtk_hdmi_register_audio_driver(struct device *dev) 1697 { 1698 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1699 struct hdmi_codec_pdata codec_data = { 1700 .ops = &mtk_hdmi_audio_codec_ops, 1701 .max_i2s_channels = 2, 1702 .i2s = 1, 1703 .data = hdmi, 1704 }; 1705 struct platform_device *pdev; 1706 1707 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1708 PLATFORM_DEVID_AUTO, &codec_data, 1709 sizeof(codec_data)); 1710 if (IS_ERR(pdev)) 1711 return PTR_ERR(pdev); 1712 1713 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1714 return 0; 1715 } 1716 1717 static int mtk_drm_hdmi_probe(struct platform_device *pdev) 1718 { 1719 struct mtk_hdmi *hdmi; 1720 struct device *dev = &pdev->dev; 1721 int ret; 1722 1723 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1724 if (!hdmi) 1725 return -ENOMEM; 1726 1727 hdmi->dev = dev; 1728 1729 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1730 if (ret) 1731 return ret; 1732 1733 hdmi->phy = devm_phy_get(dev, "hdmi"); 1734 if (IS_ERR(hdmi->phy)) { 1735 ret = PTR_ERR(hdmi->phy); 1736 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); 1737 return ret; 1738 } 1739 1740 mutex_init(&hdmi->update_plugged_status_lock); 1741 platform_set_drvdata(pdev, hdmi); 1742 1743 ret = mtk_hdmi_output_init(hdmi); 1744 if (ret) { 1745 dev_err(dev, "Failed to initialize hdmi output\n"); 1746 return ret; 1747 } 1748 1749 ret = mtk_hdmi_register_audio_driver(dev); 1750 if (ret) { 1751 dev_err(dev, "Failed to register audio driver: %d\n", ret); 1752 return ret; 1753 } 1754 1755 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1756 hdmi->bridge.of_node = pdev->dev.of_node; 1757 drm_bridge_add(&hdmi->bridge); 1758 1759 ret = mtk_hdmi_clk_enable_audio(hdmi); 1760 if (ret) { 1761 dev_err(dev, "Failed to enable audio clocks: %d\n", ret); 1762 goto err_bridge_remove; 1763 } 1764 1765 dev_dbg(dev, "mediatek hdmi probe success\n"); 1766 return 0; 1767 1768 err_bridge_remove: 1769 drm_bridge_remove(&hdmi->bridge); 1770 return ret; 1771 } 1772 1773 static int mtk_drm_hdmi_remove(struct platform_device *pdev) 1774 { 1775 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1776 1777 drm_bridge_remove(&hdmi->bridge); 1778 mtk_hdmi_clk_disable_audio(hdmi); 1779 return 0; 1780 } 1781 1782 #ifdef CONFIG_PM_SLEEP 1783 static int mtk_hdmi_suspend(struct device *dev) 1784 { 1785 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1786 1787 mtk_hdmi_clk_disable_audio(hdmi); 1788 dev_dbg(dev, "hdmi suspend success!\n"); 1789 return 0; 1790 } 1791 1792 static int mtk_hdmi_resume(struct device *dev) 1793 { 1794 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1795 int ret = 0; 1796 1797 ret = mtk_hdmi_clk_enable_audio(hdmi); 1798 if (ret) { 1799 dev_err(dev, "hdmi resume failed!\n"); 1800 return ret; 1801 } 1802 1803 dev_dbg(dev, "hdmi resume success!\n"); 1804 return 0; 1805 } 1806 #endif 1807 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1808 mtk_hdmi_suspend, mtk_hdmi_resume); 1809 1810 static const struct of_device_id mtk_drm_hdmi_of_ids[] = { 1811 { .compatible = "mediatek,mt8173-hdmi", }, 1812 {} 1813 }; 1814 1815 static struct platform_driver mtk_hdmi_driver = { 1816 .probe = mtk_drm_hdmi_probe, 1817 .remove = mtk_drm_hdmi_remove, 1818 .driver = { 1819 .name = "mediatek-drm-hdmi", 1820 .of_match_table = mtk_drm_hdmi_of_ids, 1821 .pm = &mtk_hdmi_pm_ops, 1822 }, 1823 }; 1824 1825 static struct platform_driver * const mtk_hdmi_drivers[] = { 1826 &mtk_hdmi_phy_driver, 1827 &mtk_hdmi_ddc_driver, 1828 &mtk_cec_driver, 1829 &mtk_hdmi_driver, 1830 }; 1831 1832 static int __init mtk_hdmitx_init(void) 1833 { 1834 return platform_register_drivers(mtk_hdmi_drivers, 1835 ARRAY_SIZE(mtk_hdmi_drivers)); 1836 } 1837 1838 static void __exit mtk_hdmitx_exit(void) 1839 { 1840 platform_unregister_drivers(mtk_hdmi_drivers, 1841 ARRAY_SIZE(mtk_hdmi_drivers)); 1842 } 1843 1844 module_init(mtk_hdmitx_init); 1845 module_exit(mtk_hdmitx_exit); 1846 1847 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1848 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1849 MODULE_LICENSE("GPL v2"); 1850