1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/hdmi.h> 11 #include <linux/i2c.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of_platform.h> 18 #include <linux/of.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_graph.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 25 #include <sound/hdmi-codec.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_bridge.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_edid.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include "mtk_cec.h" 35 #include "mtk_hdmi.h" 36 #include "mtk_hdmi_regs.h" 37 38 #define NCTS_BYTES 7 39 40 enum mtk_hdmi_clk_id { 41 MTK_HDMI_CLK_HDMI_PIXEL, 42 MTK_HDMI_CLK_HDMI_PLL, 43 MTK_HDMI_CLK_AUD_BCLK, 44 MTK_HDMI_CLK_AUD_SPDIF, 45 MTK_HDMI_CLK_COUNT 46 }; 47 48 enum hdmi_aud_input_type { 49 HDMI_AUD_INPUT_I2S = 0, 50 HDMI_AUD_INPUT_SPDIF, 51 }; 52 53 enum hdmi_aud_i2s_fmt { 54 HDMI_I2S_MODE_RJT_24BIT = 0, 55 HDMI_I2S_MODE_RJT_16BIT, 56 HDMI_I2S_MODE_LJT_24BIT, 57 HDMI_I2S_MODE_LJT_16BIT, 58 HDMI_I2S_MODE_I2S_24BIT, 59 HDMI_I2S_MODE_I2S_16BIT 60 }; 61 62 enum hdmi_aud_mclk { 63 HDMI_AUD_MCLK_128FS, 64 HDMI_AUD_MCLK_192FS, 65 HDMI_AUD_MCLK_256FS, 66 HDMI_AUD_MCLK_384FS, 67 HDMI_AUD_MCLK_512FS, 68 HDMI_AUD_MCLK_768FS, 69 HDMI_AUD_MCLK_1152FS, 70 }; 71 72 enum hdmi_aud_channel_type { 73 HDMI_AUD_CHAN_TYPE_1_0 = 0, 74 HDMI_AUD_CHAN_TYPE_1_1, 75 HDMI_AUD_CHAN_TYPE_2_0, 76 HDMI_AUD_CHAN_TYPE_2_1, 77 HDMI_AUD_CHAN_TYPE_3_0, 78 HDMI_AUD_CHAN_TYPE_3_1, 79 HDMI_AUD_CHAN_TYPE_4_0, 80 HDMI_AUD_CHAN_TYPE_4_1, 81 HDMI_AUD_CHAN_TYPE_5_0, 82 HDMI_AUD_CHAN_TYPE_5_1, 83 HDMI_AUD_CHAN_TYPE_6_0, 84 HDMI_AUD_CHAN_TYPE_6_1, 85 HDMI_AUD_CHAN_TYPE_7_0, 86 HDMI_AUD_CHAN_TYPE_7_1, 87 HDMI_AUD_CHAN_TYPE_3_0_LRS, 88 HDMI_AUD_CHAN_TYPE_3_1_LRS, 89 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 90 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 91 HDMI_AUD_CHAN_TYPE_6_1_CS, 92 HDMI_AUD_CHAN_TYPE_6_1_CH, 93 HDMI_AUD_CHAN_TYPE_6_1_OH, 94 HDMI_AUD_CHAN_TYPE_6_1_CHR, 95 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 96 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 97 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 98 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 99 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 100 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 101 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 102 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 103 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 104 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 105 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 106 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 107 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 108 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 109 HDMI_AUD_CHAN_TYPE_6_0_CS, 110 HDMI_AUD_CHAN_TYPE_6_0_CH, 111 HDMI_AUD_CHAN_TYPE_6_0_OH, 112 HDMI_AUD_CHAN_TYPE_6_0_CHR, 113 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 114 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 115 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 116 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 117 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 118 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 119 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 120 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 121 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 122 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 123 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 124 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 125 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 126 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 127 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 128 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 129 }; 130 131 enum hdmi_aud_channel_swap_type { 132 HDMI_AUD_SWAP_LR, 133 HDMI_AUD_SWAP_LFE_CC, 134 HDMI_AUD_SWAP_LSRS, 135 HDMI_AUD_SWAP_RLS_RRS, 136 HDMI_AUD_SWAP_LR_STATUS, 137 }; 138 139 struct hdmi_audio_param { 140 enum hdmi_audio_coding_type aud_codec; 141 enum hdmi_audio_sample_size aud_sampe_size; 142 enum hdmi_aud_input_type aud_input_type; 143 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 144 enum hdmi_aud_mclk aud_mclk; 145 enum hdmi_aud_channel_type aud_input_chan_type; 146 struct hdmi_codec_params codec_params; 147 }; 148 149 struct mtk_hdmi_conf { 150 bool tz_disabled; 151 }; 152 153 struct mtk_hdmi { 154 struct drm_bridge bridge; 155 struct drm_bridge *next_bridge; 156 struct drm_connector conn; 157 struct device *dev; 158 const struct mtk_hdmi_conf *conf; 159 struct phy *phy; 160 struct device *cec_dev; 161 struct i2c_adapter *ddc_adpt; 162 struct clk *clk[MTK_HDMI_CLK_COUNT]; 163 struct drm_display_mode mode; 164 bool dvi_mode; 165 u32 min_clock; 166 u32 max_clock; 167 u32 max_hdisplay; 168 u32 max_vdisplay; 169 u32 ibias; 170 u32 ibias_up; 171 struct regmap *sys_regmap; 172 unsigned int sys_offset; 173 void __iomem *regs; 174 enum hdmi_colorspace csp; 175 struct hdmi_audio_param aud_param; 176 bool audio_enable; 177 bool powered; 178 bool enabled; 179 hdmi_codec_plugged_cb plugged_cb; 180 struct device *codec_dev; 181 struct mutex update_plugged_status_lock; 182 }; 183 184 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 185 { 186 return container_of(b, struct mtk_hdmi, bridge); 187 } 188 189 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) 190 { 191 return container_of(c, struct mtk_hdmi, conn); 192 } 193 194 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 195 { 196 return readl(hdmi->regs + offset); 197 } 198 199 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 200 { 201 writel(val, hdmi->regs + offset); 202 } 203 204 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 205 { 206 void __iomem *reg = hdmi->regs + offset; 207 u32 tmp; 208 209 tmp = readl(reg); 210 tmp &= ~bits; 211 writel(tmp, reg); 212 } 213 214 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 215 { 216 void __iomem *reg = hdmi->regs + offset; 217 u32 tmp; 218 219 tmp = readl(reg); 220 tmp |= bits; 221 writel(tmp, reg); 222 } 223 224 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 225 { 226 void __iomem *reg = hdmi->regs + offset; 227 u32 tmp; 228 229 tmp = readl(reg); 230 tmp = (tmp & ~mask) | (val & mask); 231 writel(tmp, reg); 232 } 233 234 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 235 { 236 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 237 VIDEO_SOURCE_SEL); 238 } 239 240 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 241 { 242 struct arm_smccc_res res; 243 244 /* 245 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 246 * output. This bit can only be controlled in ARM supervisor mode. 247 * The ARM trusted firmware provides an API for the HDMI driver to set 248 * this control bit to enable HDMI output in supervisor mode. 249 */ 250 if (hdmi->conf && hdmi->conf->tz_disabled) 251 regmap_update_bits(hdmi->sys_regmap, 252 hdmi->sys_offset + HDMI_SYS_CFG20, 253 0x80008005, enable ? 0x80000005 : 0x8000); 254 else 255 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 256 0x80000000, 0, 0, 0, 0, 0, &res); 257 258 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 259 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 260 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 261 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 262 } 263 264 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 265 { 266 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 267 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 268 } 269 270 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 271 { 272 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 273 } 274 275 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 276 { 277 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 278 } 279 280 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 281 { 282 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 283 HDMI_RST, HDMI_RST); 284 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 285 HDMI_RST, 0); 286 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 287 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 288 ANLG_ON, ANLG_ON); 289 } 290 291 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 292 { 293 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 294 CFG2_NOTICE_EN); 295 } 296 297 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 298 { 299 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 300 } 301 302 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 303 { 304 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 305 } 306 307 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 308 u8 len) 309 { 310 u32 ctrl_reg = GRL_CTRL; 311 int i; 312 u8 *frame_data; 313 enum hdmi_infoframe_type frame_type; 314 u8 frame_ver; 315 u8 frame_len; 316 u8 checksum; 317 int ctrl_frame_en = 0; 318 319 frame_type = *buffer++; 320 frame_ver = *buffer++; 321 frame_len = *buffer++; 322 checksum = *buffer++; 323 frame_data = buffer; 324 325 dev_dbg(hdmi->dev, 326 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 327 frame_type, frame_ver, frame_len, checksum); 328 329 switch (frame_type) { 330 case HDMI_INFOFRAME_TYPE_AVI: 331 ctrl_frame_en = CTRL_AVI_EN; 332 ctrl_reg = GRL_CTRL; 333 break; 334 case HDMI_INFOFRAME_TYPE_SPD: 335 ctrl_frame_en = CTRL_SPD_EN; 336 ctrl_reg = GRL_CTRL; 337 break; 338 case HDMI_INFOFRAME_TYPE_AUDIO: 339 ctrl_frame_en = CTRL_AUDIO_EN; 340 ctrl_reg = GRL_CTRL; 341 break; 342 case HDMI_INFOFRAME_TYPE_VENDOR: 343 ctrl_frame_en = VS_EN; 344 ctrl_reg = GRL_ACP_ISRC_CTRL; 345 break; 346 default: 347 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 348 return; 349 } 350 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 351 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 352 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 353 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 354 355 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 356 for (i = 0; i < frame_len; i++) 357 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 358 359 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 360 } 361 362 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 363 { 364 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 365 AUDIO_PACKET_OFF); 366 } 367 368 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 369 { 370 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 371 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 372 usleep_range(2000, 4000); 373 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 374 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 375 } 376 377 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 378 { 379 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 380 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 381 COLOR_8BIT_MODE); 382 } 383 384 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 385 { 386 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 387 usleep_range(2000, 4000); 388 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 389 } 390 391 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 392 { 393 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 394 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 395 usleep_range(2000, 4000); 396 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 397 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 398 } 399 400 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 401 { 402 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 403 CTS_CTRL_SOFT); 404 } 405 406 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 407 bool enable) 408 { 409 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 410 NCTS_WRI_ANYTIME); 411 } 412 413 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 414 struct drm_display_mode *mode) 415 { 416 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 417 418 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 419 mode->clock == 74250 && 420 mode->vdisplay == 1080) 421 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 422 else 423 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 424 } 425 426 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 427 enum hdmi_aud_channel_swap_type swap) 428 { 429 u8 swap_bit; 430 431 switch (swap) { 432 case HDMI_AUD_SWAP_LR: 433 swap_bit = LR_SWAP; 434 break; 435 case HDMI_AUD_SWAP_LFE_CC: 436 swap_bit = LFE_CC_SWAP; 437 break; 438 case HDMI_AUD_SWAP_LSRS: 439 swap_bit = LSRS_SWAP; 440 break; 441 case HDMI_AUD_SWAP_RLS_RRS: 442 swap_bit = RLS_RRS_SWAP; 443 break; 444 case HDMI_AUD_SWAP_LR_STATUS: 445 swap_bit = LR_STATUS_SWAP; 446 break; 447 default: 448 swap_bit = LFE_CC_SWAP; 449 break; 450 } 451 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 452 } 453 454 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 455 enum hdmi_audio_sample_size bit_num) 456 { 457 u32 val; 458 459 switch (bit_num) { 460 case HDMI_AUDIO_SAMPLE_SIZE_16: 461 val = AOUT_16BIT; 462 break; 463 case HDMI_AUDIO_SAMPLE_SIZE_20: 464 val = AOUT_20BIT; 465 break; 466 case HDMI_AUDIO_SAMPLE_SIZE_24: 467 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 468 val = AOUT_24BIT; 469 break; 470 } 471 472 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 473 } 474 475 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 476 enum hdmi_aud_i2s_fmt i2s_fmt) 477 { 478 u32 val; 479 480 val = mtk_hdmi_read(hdmi, GRL_CFG0); 481 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 482 483 switch (i2s_fmt) { 484 case HDMI_I2S_MODE_RJT_24BIT: 485 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 486 break; 487 case HDMI_I2S_MODE_RJT_16BIT: 488 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 489 break; 490 case HDMI_I2S_MODE_LJT_24BIT: 491 default: 492 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 493 break; 494 case HDMI_I2S_MODE_LJT_16BIT: 495 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 496 break; 497 case HDMI_I2S_MODE_I2S_24BIT: 498 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 499 break; 500 case HDMI_I2S_MODE_I2S_16BIT: 501 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 502 break; 503 } 504 mtk_hdmi_write(hdmi, GRL_CFG0, val); 505 } 506 507 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 508 { 509 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 510 u8 val; 511 512 /* Disable high bitrate, set DST packet normal/double */ 513 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 514 515 if (dst) 516 val = DST_NORMAL_DOUBLE | SACD_DST; 517 else 518 val = 0; 519 520 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 521 } 522 523 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 524 enum hdmi_aud_channel_type channel_type, 525 u8 channel_count) 526 { 527 unsigned int ch_switch; 528 u8 i2s_uv; 529 530 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 531 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 532 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 533 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 534 535 if (channel_count == 2) { 536 i2s_uv = I2S_UV_CH_EN(0); 537 } else if (channel_count == 3 || channel_count == 4) { 538 if (channel_count == 4 && 539 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 540 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 541 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 542 else 543 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 544 } else if (channel_count == 6 || channel_count == 5) { 545 if (channel_count == 6 && 546 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 547 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 548 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 549 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 550 } else { 551 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 552 I2S_UV_CH_EN(0); 553 } 554 } else if (channel_count == 8 || channel_count == 7) { 555 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 556 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 557 } else { 558 i2s_uv = I2S_UV_CH_EN(0); 559 } 560 561 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 562 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 563 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 564 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 565 } 566 567 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 568 enum hdmi_aud_input_type input_type) 569 { 570 u32 val; 571 572 val = mtk_hdmi_read(hdmi, GRL_CFG1); 573 if (input_type == HDMI_AUD_INPUT_I2S && 574 (val & CFG1_SPDIF) == CFG1_SPDIF) { 575 val &= ~CFG1_SPDIF; 576 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 577 (val & CFG1_SPDIF) == 0) { 578 val |= CFG1_SPDIF; 579 } 580 mtk_hdmi_write(hdmi, GRL_CFG1, val); 581 } 582 583 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 584 u8 *channel_status) 585 { 586 int i; 587 588 for (i = 0; i < 5; i++) { 589 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 590 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 591 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 592 } 593 for (; i < 24; i++) { 594 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 595 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 596 } 597 } 598 599 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 600 { 601 u32 val; 602 603 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 604 if (val & MIX_CTRL_SRC_EN) { 605 val &= ~MIX_CTRL_SRC_EN; 606 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 607 usleep_range(255, 512); 608 val |= MIX_CTRL_SRC_EN; 609 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 610 } 611 } 612 613 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 614 { 615 u32 val; 616 617 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 618 val &= ~MIX_CTRL_SRC_EN; 619 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 620 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 621 } 622 623 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 624 enum hdmi_aud_mclk mclk) 625 { 626 u32 val; 627 628 val = mtk_hdmi_read(hdmi, GRL_CFG5); 629 val &= CFG5_CD_RATIO_MASK; 630 631 switch (mclk) { 632 case HDMI_AUD_MCLK_128FS: 633 val |= CFG5_FS128; 634 break; 635 case HDMI_AUD_MCLK_256FS: 636 val |= CFG5_FS256; 637 break; 638 case HDMI_AUD_MCLK_384FS: 639 val |= CFG5_FS384; 640 break; 641 case HDMI_AUD_MCLK_512FS: 642 val |= CFG5_FS512; 643 break; 644 case HDMI_AUD_MCLK_768FS: 645 val |= CFG5_FS768; 646 break; 647 default: 648 val |= CFG5_FS256; 649 break; 650 } 651 mtk_hdmi_write(hdmi, GRL_CFG5, val); 652 } 653 654 struct hdmi_acr_n { 655 unsigned int clock; 656 unsigned int n[3]; 657 }; 658 659 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 660 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 661 /* Clock, N: 32kHz 44.1kHz 48kHz */ 662 { 25175, { 4576, 7007, 6864 } }, 663 { 74176, { 11648, 17836, 11648 } }, 664 { 148352, { 11648, 8918, 5824 } }, 665 { 296703, { 5824, 4459, 5824 } }, 666 { 297000, { 3072, 4704, 5120 } }, 667 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 668 }; 669 670 /** 671 * hdmi_recommended_n() - Return N value recommended by HDMI specification 672 * @freq: audio sample rate in Hz 673 * @clock: rounded TMDS clock in kHz 674 */ 675 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 676 { 677 const struct hdmi_acr_n *recommended; 678 unsigned int i; 679 680 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 681 if (clock == hdmi_rec_n_table[i].clock) 682 break; 683 } 684 recommended = hdmi_rec_n_table + i; 685 686 switch (freq) { 687 case 32000: 688 return recommended->n[0]; 689 case 44100: 690 return recommended->n[1]; 691 case 48000: 692 return recommended->n[2]; 693 case 88200: 694 return recommended->n[1] * 2; 695 case 96000: 696 return recommended->n[2] * 2; 697 case 176400: 698 return recommended->n[1] * 4; 699 case 192000: 700 return recommended->n[2] * 4; 701 default: 702 return (128 * freq) / 1000; 703 } 704 } 705 706 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 707 { 708 switch (clock) { 709 case 25175: 710 return 25174825; /* 25.2/1.001 MHz */ 711 case 74176: 712 return 74175824; /* 74.25/1.001 MHz */ 713 case 148352: 714 return 148351648; /* 148.5/1.001 MHz */ 715 case 296703: 716 return 296703297; /* 297/1.001 MHz */ 717 default: 718 return clock * 1000; 719 } 720 } 721 722 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 723 unsigned int tmds_clock, unsigned int n) 724 { 725 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 726 128 * audio_sample_rate); 727 } 728 729 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 730 unsigned int cts) 731 { 732 unsigned char val[NCTS_BYTES]; 733 int i; 734 735 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 736 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 737 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 738 memset(val, 0, sizeof(val)); 739 740 val[0] = (cts >> 24) & 0xff; 741 val[1] = (cts >> 16) & 0xff; 742 val[2] = (cts >> 8) & 0xff; 743 val[3] = cts & 0xff; 744 745 val[4] = (n >> 16) & 0xff; 746 val[5] = (n >> 8) & 0xff; 747 val[6] = n & 0xff; 748 749 for (i = 0; i < NCTS_BYTES; i++) 750 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 751 } 752 753 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 754 unsigned int sample_rate, 755 unsigned int clock) 756 { 757 unsigned int n, cts; 758 759 n = hdmi_recommended_n(sample_rate, clock); 760 cts = hdmi_expected_cts(sample_rate, clock, n); 761 762 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 763 __func__, sample_rate, clock, n, cts); 764 765 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 766 AUDIO_I2S_NCTS_SEL); 767 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 768 } 769 770 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 771 { 772 switch (channel_type) { 773 case HDMI_AUD_CHAN_TYPE_1_0: 774 case HDMI_AUD_CHAN_TYPE_1_1: 775 case HDMI_AUD_CHAN_TYPE_2_0: 776 return 2; 777 case HDMI_AUD_CHAN_TYPE_2_1: 778 case HDMI_AUD_CHAN_TYPE_3_0: 779 return 3; 780 case HDMI_AUD_CHAN_TYPE_3_1: 781 case HDMI_AUD_CHAN_TYPE_4_0: 782 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 783 return 4; 784 case HDMI_AUD_CHAN_TYPE_4_1: 785 case HDMI_AUD_CHAN_TYPE_5_0: 786 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 787 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 788 return 5; 789 case HDMI_AUD_CHAN_TYPE_5_1: 790 case HDMI_AUD_CHAN_TYPE_6_0: 791 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 792 case HDMI_AUD_CHAN_TYPE_6_0_CS: 793 case HDMI_AUD_CHAN_TYPE_6_0_CH: 794 case HDMI_AUD_CHAN_TYPE_6_0_OH: 795 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 796 return 6; 797 case HDMI_AUD_CHAN_TYPE_6_1: 798 case HDMI_AUD_CHAN_TYPE_6_1_CS: 799 case HDMI_AUD_CHAN_TYPE_6_1_CH: 800 case HDMI_AUD_CHAN_TYPE_6_1_OH: 801 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 802 case HDMI_AUD_CHAN_TYPE_7_0: 803 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 804 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 805 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 806 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 807 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 808 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 809 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 810 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 811 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 812 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 813 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 814 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 815 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 816 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 817 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 818 return 7; 819 case HDMI_AUD_CHAN_TYPE_7_1: 820 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 821 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 822 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 823 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 824 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 825 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 826 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 827 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 828 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 829 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 830 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 831 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 832 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 833 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 834 return 8; 835 default: 836 return 2; 837 } 838 } 839 840 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 841 { 842 unsigned long rate; 843 int ret; 844 845 /* The DPI driver already should have set TVDPLL to the correct rate */ 846 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 847 if (ret) { 848 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 849 ret); 850 return ret; 851 } 852 853 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 854 855 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 856 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 857 rate); 858 else 859 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 860 861 mtk_hdmi_hw_config_sys(hdmi); 862 mtk_hdmi_hw_set_deep_color_mode(hdmi); 863 return 0; 864 } 865 866 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 867 struct drm_display_mode *mode) 868 { 869 mtk_hdmi_hw_reset(hdmi); 870 mtk_hdmi_hw_enable_notice(hdmi, true); 871 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 872 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 873 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 874 875 mtk_hdmi_hw_msic_setting(hdmi, mode); 876 } 877 878 879 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 880 { 881 enum hdmi_aud_channel_type chan_type; 882 u8 chan_count; 883 bool dst; 884 885 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 886 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 887 888 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 889 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 890 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 891 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 892 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 893 } 894 895 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 896 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 897 898 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 899 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 900 mtk_hdmi_hw_audio_config(hdmi, dst); 901 902 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 903 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 904 else 905 chan_type = hdmi->aud_param.aud_input_chan_type; 906 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 907 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 908 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 909 } 910 911 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 912 struct drm_display_mode *display_mode) 913 { 914 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 915 916 mtk_hdmi_hw_ncts_enable(hdmi, false); 917 mtk_hdmi_hw_aud_src_disable(hdmi); 918 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 919 920 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 921 switch (sample_rate) { 922 case 32000: 923 case 44100: 924 case 48000: 925 case 88200: 926 case 96000: 927 break; 928 default: 929 return -EINVAL; 930 } 931 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 932 } else { 933 switch (sample_rate) { 934 case 32000: 935 case 44100: 936 case 48000: 937 break; 938 default: 939 return -EINVAL; 940 } 941 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 942 } 943 944 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 945 946 mtk_hdmi_hw_aud_src_reenable(hdmi); 947 return 0; 948 } 949 950 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 951 struct drm_display_mode *display_mode) 952 { 953 mtk_hdmi_hw_aud_mute(hdmi); 954 mtk_hdmi_hw_send_aud_packet(hdmi, false); 955 956 mtk_hdmi_aud_set_input(hdmi); 957 mtk_hdmi_aud_set_src(hdmi, display_mode); 958 mtk_hdmi_hw_aud_set_channel_status(hdmi, 959 hdmi->aud_param.codec_params.iec.status); 960 961 usleep_range(50, 100); 962 963 mtk_hdmi_hw_ncts_enable(hdmi, true); 964 mtk_hdmi_hw_send_aud_packet(hdmi, true); 965 mtk_hdmi_hw_aud_unmute(hdmi); 966 return 0; 967 } 968 969 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 970 struct drm_display_mode *mode) 971 { 972 struct hdmi_avi_infoframe frame; 973 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 974 ssize_t err; 975 976 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 977 &hdmi->conn, mode); 978 if (err < 0) { 979 dev_err(hdmi->dev, 980 "Failed to get AVI infoframe from mode: %zd\n", err); 981 return err; 982 } 983 984 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 985 if (err < 0) { 986 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 987 return err; 988 } 989 990 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 991 return 0; 992 } 993 994 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 995 const char *vendor, 996 const char *product) 997 { 998 struct hdmi_spd_infoframe frame; 999 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; 1000 ssize_t err; 1001 1002 err = hdmi_spd_infoframe_init(&frame, vendor, product); 1003 if (err < 0) { 1004 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 1005 err); 1006 return err; 1007 } 1008 1009 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 1010 if (err < 0) { 1011 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1012 return err; 1013 } 1014 1015 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1016 return 0; 1017 } 1018 1019 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1020 { 1021 struct hdmi_audio_infoframe frame; 1022 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 1023 ssize_t err; 1024 1025 err = hdmi_audio_infoframe_init(&frame); 1026 if (err < 0) { 1027 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1028 err); 1029 return err; 1030 } 1031 1032 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1033 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1034 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1035 frame.channels = mtk_hdmi_aud_get_chnl_count( 1036 hdmi->aud_param.aud_input_chan_type); 1037 1038 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1039 if (err < 0) { 1040 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1041 err); 1042 return err; 1043 } 1044 1045 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1046 return 0; 1047 } 1048 1049 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1050 struct drm_display_mode *mode) 1051 { 1052 struct hdmi_vendor_infoframe frame; 1053 u8 buffer[10]; 1054 ssize_t err; 1055 1056 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1057 &hdmi->conn, mode); 1058 if (err) { 1059 dev_err(hdmi->dev, 1060 "Failed to get vendor infoframe from mode: %zd\n", err); 1061 return err; 1062 } 1063 1064 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1065 if (err < 0) { 1066 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1067 err); 1068 return err; 1069 } 1070 1071 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1072 return 0; 1073 } 1074 1075 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1076 { 1077 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1078 1079 hdmi->csp = HDMI_COLORSPACE_RGB; 1080 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1081 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1082 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1083 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1084 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1085 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1086 1087 return 0; 1088 } 1089 1090 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1091 { 1092 mtk_hdmi_hw_send_aud_packet(hdmi, true); 1093 hdmi->audio_enable = true; 1094 } 1095 1096 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1097 { 1098 mtk_hdmi_hw_send_aud_packet(hdmi, false); 1099 hdmi->audio_enable = false; 1100 } 1101 1102 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1103 struct hdmi_audio_param *param) 1104 { 1105 if (!hdmi->audio_enable) { 1106 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1107 return -EINVAL; 1108 } 1109 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1110 param->aud_codec, param->aud_input_type, 1111 param->aud_input_chan_type, param->codec_params.sample_rate); 1112 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1113 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1114 } 1115 1116 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1117 struct drm_display_mode *mode) 1118 { 1119 int ret; 1120 1121 mtk_hdmi_hw_vid_black(hdmi, true); 1122 mtk_hdmi_hw_aud_mute(hdmi); 1123 mtk_hdmi_hw_send_av_mute(hdmi); 1124 phy_power_off(hdmi->phy); 1125 1126 ret = mtk_hdmi_video_change_vpll(hdmi, 1127 mode->clock * 1000); 1128 if (ret) { 1129 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1130 return ret; 1131 } 1132 mtk_hdmi_video_set_display_mode(hdmi, mode); 1133 1134 phy_power_on(hdmi->phy); 1135 mtk_hdmi_aud_output_config(hdmi, mode); 1136 1137 mtk_hdmi_hw_vid_black(hdmi, false); 1138 mtk_hdmi_hw_aud_unmute(hdmi); 1139 mtk_hdmi_hw_send_av_unmute(hdmi); 1140 1141 return 0; 1142 } 1143 1144 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1145 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1146 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1147 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1148 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1149 }; 1150 1151 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1152 struct device_node *np) 1153 { 1154 int i; 1155 1156 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1157 hdmi->clk[i] = of_clk_get_by_name(np, 1158 mtk_hdmi_clk_names[i]); 1159 if (IS_ERR(hdmi->clk[i])) 1160 return PTR_ERR(hdmi->clk[i]); 1161 } 1162 return 0; 1163 } 1164 1165 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1166 { 1167 int ret; 1168 1169 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1170 if (ret) 1171 return ret; 1172 1173 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1174 if (ret) 1175 goto err; 1176 1177 return 0; 1178 err: 1179 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1180 return ret; 1181 } 1182 1183 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1184 { 1185 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1186 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1187 } 1188 1189 static enum drm_connector_status 1190 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) 1191 { 1192 bool connected; 1193 1194 mutex_lock(&hdmi->update_plugged_status_lock); 1195 connected = mtk_cec_hpd_high(hdmi->cec_dev); 1196 if (hdmi->plugged_cb && hdmi->codec_dev) 1197 hdmi->plugged_cb(hdmi->codec_dev, connected); 1198 mutex_unlock(&hdmi->update_plugged_status_lock); 1199 1200 return connected ? 1201 connector_status_connected : connector_status_disconnected; 1202 } 1203 1204 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, 1205 bool force) 1206 { 1207 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1208 return mtk_hdmi_update_plugged_status(hdmi); 1209 } 1210 1211 static void hdmi_conn_destroy(struct drm_connector *conn) 1212 { 1213 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1214 1215 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); 1216 1217 drm_connector_cleanup(conn); 1218 } 1219 1220 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) 1221 { 1222 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1223 struct edid *edid; 1224 int ret; 1225 1226 if (!hdmi->ddc_adpt) 1227 return -ENODEV; 1228 1229 edid = drm_get_edid(conn, hdmi->ddc_adpt); 1230 if (!edid) 1231 return -ENODEV; 1232 1233 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1234 1235 drm_connector_update_edid_property(conn, edid); 1236 1237 ret = drm_add_edid_modes(conn, edid); 1238 kfree(edid); 1239 return ret; 1240 } 1241 1242 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, 1243 struct drm_display_mode *mode) 1244 { 1245 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1246 struct drm_bridge *next_bridge; 1247 1248 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1249 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1250 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1251 1252 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge); 1253 if (next_bridge) { 1254 struct drm_display_mode adjusted_mode; 1255 1256 drm_mode_copy(&adjusted_mode, mode); 1257 if (!drm_bridge_chain_mode_fixup(next_bridge, mode, 1258 &adjusted_mode)) 1259 return MODE_BAD; 1260 } 1261 1262 if (mode->clock < 27000) 1263 return MODE_CLOCK_LOW; 1264 if (mode->clock > 297000) 1265 return MODE_CLOCK_HIGH; 1266 1267 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1268 } 1269 1270 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) 1271 { 1272 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1273 1274 return hdmi->bridge.encoder; 1275 } 1276 1277 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { 1278 .detect = hdmi_conn_detect, 1279 .fill_modes = drm_helper_probe_single_connector_modes, 1280 .destroy = hdmi_conn_destroy, 1281 .reset = drm_atomic_helper_connector_reset, 1282 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1283 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1284 }; 1285 1286 static const struct drm_connector_helper_funcs 1287 mtk_hdmi_connector_helper_funcs = { 1288 .get_modes = mtk_hdmi_conn_get_modes, 1289 .mode_valid = mtk_hdmi_conn_mode_valid, 1290 .best_encoder = mtk_hdmi_conn_best_enc, 1291 }; 1292 1293 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1294 { 1295 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1296 1297 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) 1298 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1299 } 1300 1301 /* 1302 * Bridge callbacks 1303 */ 1304 1305 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge, 1306 enum drm_bridge_attach_flags flags) 1307 { 1308 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1309 int ret; 1310 1311 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 1312 DRM_ERROR("Fix bridge driver to make connector optional!"); 1313 return -EINVAL; 1314 } 1315 1316 ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn, 1317 &mtk_hdmi_connector_funcs, 1318 DRM_MODE_CONNECTOR_HDMIA, 1319 hdmi->ddc_adpt); 1320 if (ret) { 1321 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); 1322 return ret; 1323 } 1324 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); 1325 1326 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; 1327 hdmi->conn.interlace_allowed = true; 1328 hdmi->conn.doublescan_allowed = false; 1329 1330 ret = drm_connector_attach_encoder(&hdmi->conn, 1331 bridge->encoder); 1332 if (ret) { 1333 dev_err(hdmi->dev, 1334 "Failed to attach connector to encoder: %d\n", ret); 1335 return ret; 1336 } 1337 1338 if (hdmi->next_bridge) { 1339 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1340 bridge, flags); 1341 if (ret) { 1342 dev_err(hdmi->dev, 1343 "Failed to attach external bridge: %d\n", ret); 1344 return ret; 1345 } 1346 } 1347 1348 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1349 1350 return 0; 1351 } 1352 1353 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1354 const struct drm_display_mode *mode, 1355 struct drm_display_mode *adjusted_mode) 1356 { 1357 return true; 1358 } 1359 1360 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) 1361 { 1362 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1363 1364 if (!hdmi->enabled) 1365 return; 1366 1367 phy_power_off(hdmi->phy); 1368 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1369 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1370 1371 hdmi->enabled = false; 1372 } 1373 1374 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) 1375 { 1376 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1377 1378 if (!hdmi->powered) 1379 return; 1380 1381 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1382 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1383 1384 hdmi->powered = false; 1385 } 1386 1387 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1388 const struct drm_display_mode *mode, 1389 const struct drm_display_mode *adjusted_mode) 1390 { 1391 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1392 1393 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1394 adjusted_mode->name, adjusted_mode->hdisplay); 1395 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1396 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1397 adjusted_mode->htotal); 1398 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1399 adjusted_mode->hskew, adjusted_mode->vdisplay); 1400 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1401 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1402 adjusted_mode->vtotal); 1403 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1404 adjusted_mode->vscan, adjusted_mode->flags); 1405 1406 drm_mode_copy(&hdmi->mode, adjusted_mode); 1407 } 1408 1409 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 1410 { 1411 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1412 1413 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1414 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1415 1416 hdmi->powered = true; 1417 } 1418 1419 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1420 struct drm_display_mode *mode) 1421 { 1422 mtk_hdmi_setup_audio_infoframe(hdmi); 1423 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1424 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1425 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1426 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1427 } 1428 1429 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1430 { 1431 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1432 1433 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1434 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1435 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1436 phy_power_on(hdmi->phy); 1437 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1438 1439 hdmi->enabled = true; 1440 } 1441 1442 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1443 .attach = mtk_hdmi_bridge_attach, 1444 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1445 .disable = mtk_hdmi_bridge_disable, 1446 .post_disable = mtk_hdmi_bridge_post_disable, 1447 .mode_set = mtk_hdmi_bridge_mode_set, 1448 .pre_enable = mtk_hdmi_bridge_pre_enable, 1449 .enable = mtk_hdmi_bridge_enable, 1450 }; 1451 1452 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1453 struct platform_device *pdev) 1454 { 1455 struct device *dev = &pdev->dev; 1456 struct device_node *np = dev->of_node; 1457 struct device_node *cec_np, *remote, *i2c_np; 1458 struct platform_device *cec_pdev; 1459 struct regmap *regmap; 1460 struct resource *mem; 1461 int ret; 1462 1463 ret = mtk_hdmi_get_all_clk(hdmi, np); 1464 if (ret) { 1465 if (ret != -EPROBE_DEFER) 1466 dev_err(dev, "Failed to get clocks: %d\n", ret); 1467 1468 return ret; 1469 } 1470 1471 /* The CEC module handles HDMI hotplug detection */ 1472 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); 1473 if (!cec_np) { 1474 dev_err(dev, "Failed to find CEC node\n"); 1475 return -EINVAL; 1476 } 1477 1478 cec_pdev = of_find_device_by_node(cec_np); 1479 if (!cec_pdev) { 1480 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1481 cec_np); 1482 of_node_put(cec_np); 1483 return -EPROBE_DEFER; 1484 } 1485 of_node_put(cec_np); 1486 hdmi->cec_dev = &cec_pdev->dev; 1487 1488 /* 1489 * The mediatek,syscon-hdmi property contains a phandle link to the 1490 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1491 * registers it contains. 1492 */ 1493 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1494 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1495 &hdmi->sys_offset); 1496 if (IS_ERR(regmap)) 1497 ret = PTR_ERR(regmap); 1498 if (ret) { 1499 dev_err(dev, 1500 "Failed to get system configuration registers: %d\n", 1501 ret); 1502 goto put_device; 1503 } 1504 hdmi->sys_regmap = regmap; 1505 1506 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1507 hdmi->regs = devm_ioremap_resource(dev, mem); 1508 if (IS_ERR(hdmi->regs)) { 1509 ret = PTR_ERR(hdmi->regs); 1510 goto put_device; 1511 } 1512 1513 remote = of_graph_get_remote_node(np, 1, 0); 1514 if (!remote) { 1515 ret = -EINVAL; 1516 goto put_device; 1517 } 1518 1519 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1520 hdmi->next_bridge = of_drm_find_bridge(remote); 1521 if (!hdmi->next_bridge) { 1522 dev_err(dev, "Waiting for external bridge\n"); 1523 of_node_put(remote); 1524 ret = -EPROBE_DEFER; 1525 goto put_device; 1526 } 1527 } 1528 1529 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1530 if (!i2c_np) { 1531 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1532 remote); 1533 of_node_put(remote); 1534 ret = -EINVAL; 1535 goto put_device; 1536 } 1537 of_node_put(remote); 1538 1539 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1540 of_node_put(i2c_np); 1541 if (!hdmi->ddc_adpt) { 1542 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1543 ret = -EINVAL; 1544 goto put_device; 1545 } 1546 1547 return 0; 1548 put_device: 1549 put_device(hdmi->cec_dev); 1550 return ret; 1551 } 1552 1553 /* 1554 * HDMI audio codec callbacks 1555 */ 1556 1557 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1558 struct hdmi_codec_daifmt *daifmt, 1559 struct hdmi_codec_params *params) 1560 { 1561 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1562 struct hdmi_audio_param hdmi_params; 1563 unsigned int chan = params->cea.channels; 1564 1565 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1566 params->sample_rate, params->sample_width, chan); 1567 1568 if (!hdmi->bridge.encoder) 1569 return -ENODEV; 1570 1571 switch (chan) { 1572 case 2: 1573 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1574 break; 1575 case 4: 1576 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1577 break; 1578 case 6: 1579 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1580 break; 1581 case 8: 1582 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1583 break; 1584 default: 1585 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1586 return -EINVAL; 1587 } 1588 1589 switch (params->sample_rate) { 1590 case 32000: 1591 case 44100: 1592 case 48000: 1593 case 88200: 1594 case 96000: 1595 case 176400: 1596 case 192000: 1597 break; 1598 default: 1599 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1600 params->sample_rate); 1601 return -EINVAL; 1602 } 1603 1604 switch (daifmt->fmt) { 1605 case HDMI_I2S: 1606 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1607 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1608 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1609 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1610 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1611 break; 1612 case HDMI_SPDIF: 1613 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1614 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1615 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1616 break; 1617 default: 1618 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1619 daifmt->fmt); 1620 return -EINVAL; 1621 } 1622 1623 memcpy(&hdmi_params.codec_params, params, 1624 sizeof(hdmi_params.codec_params)); 1625 1626 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1627 1628 return 0; 1629 } 1630 1631 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1632 { 1633 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1634 1635 mtk_hdmi_audio_enable(hdmi); 1636 1637 return 0; 1638 } 1639 1640 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1641 { 1642 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1643 1644 mtk_hdmi_audio_disable(hdmi); 1645 } 1646 1647 static int 1648 mtk_hdmi_audio_mute(struct device *dev, void *data, 1649 bool enable, int direction) 1650 { 1651 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1652 1653 if (enable) 1654 mtk_hdmi_hw_aud_mute(hdmi); 1655 else 1656 mtk_hdmi_hw_aud_unmute(hdmi); 1657 1658 return 0; 1659 } 1660 1661 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1662 { 1663 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1664 1665 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); 1666 1667 return 0; 1668 } 1669 1670 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, 1671 hdmi_codec_plugged_cb fn, 1672 struct device *codec_dev) 1673 { 1674 struct mtk_hdmi *hdmi = data; 1675 1676 mutex_lock(&hdmi->update_plugged_status_lock); 1677 hdmi->plugged_cb = fn; 1678 hdmi->codec_dev = codec_dev; 1679 mutex_unlock(&hdmi->update_plugged_status_lock); 1680 1681 mtk_hdmi_update_plugged_status(hdmi); 1682 1683 return 0; 1684 } 1685 1686 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1687 .hw_params = mtk_hdmi_audio_hw_params, 1688 .audio_startup = mtk_hdmi_audio_startup, 1689 .audio_shutdown = mtk_hdmi_audio_shutdown, 1690 .mute_stream = mtk_hdmi_audio_mute, 1691 .get_eld = mtk_hdmi_audio_get_eld, 1692 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1693 .no_capture_mute = 1, 1694 }; 1695 1696 static int mtk_hdmi_register_audio_driver(struct device *dev) 1697 { 1698 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1699 struct hdmi_codec_pdata codec_data = { 1700 .ops = &mtk_hdmi_audio_codec_ops, 1701 .max_i2s_channels = 2, 1702 .i2s = 1, 1703 .data = hdmi, 1704 }; 1705 struct platform_device *pdev; 1706 1707 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1708 PLATFORM_DEVID_AUTO, &codec_data, 1709 sizeof(codec_data)); 1710 if (IS_ERR(pdev)) 1711 return PTR_ERR(pdev); 1712 1713 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1714 return 0; 1715 } 1716 1717 static int mtk_drm_hdmi_probe(struct platform_device *pdev) 1718 { 1719 struct mtk_hdmi *hdmi; 1720 struct device *dev = &pdev->dev; 1721 int ret; 1722 1723 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1724 if (!hdmi) 1725 return -ENOMEM; 1726 1727 hdmi->dev = dev; 1728 hdmi->conf = of_device_get_match_data(dev); 1729 1730 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1731 if (ret) 1732 return ret; 1733 1734 hdmi->phy = devm_phy_get(dev, "hdmi"); 1735 if (IS_ERR(hdmi->phy)) { 1736 ret = PTR_ERR(hdmi->phy); 1737 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); 1738 return ret; 1739 } 1740 1741 mutex_init(&hdmi->update_plugged_status_lock); 1742 platform_set_drvdata(pdev, hdmi); 1743 1744 ret = mtk_hdmi_output_init(hdmi); 1745 if (ret) { 1746 dev_err(dev, "Failed to initialize hdmi output\n"); 1747 return ret; 1748 } 1749 1750 ret = mtk_hdmi_register_audio_driver(dev); 1751 if (ret) { 1752 dev_err(dev, "Failed to register audio driver: %d\n", ret); 1753 return ret; 1754 } 1755 1756 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1757 hdmi->bridge.of_node = pdev->dev.of_node; 1758 drm_bridge_add(&hdmi->bridge); 1759 1760 ret = mtk_hdmi_clk_enable_audio(hdmi); 1761 if (ret) { 1762 dev_err(dev, "Failed to enable audio clocks: %d\n", ret); 1763 goto err_bridge_remove; 1764 } 1765 1766 return 0; 1767 1768 err_bridge_remove: 1769 drm_bridge_remove(&hdmi->bridge); 1770 return ret; 1771 } 1772 1773 static int mtk_drm_hdmi_remove(struct platform_device *pdev) 1774 { 1775 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1776 1777 drm_bridge_remove(&hdmi->bridge); 1778 mtk_hdmi_clk_disable_audio(hdmi); 1779 return 0; 1780 } 1781 1782 #ifdef CONFIG_PM_SLEEP 1783 static int mtk_hdmi_suspend(struct device *dev) 1784 { 1785 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1786 1787 mtk_hdmi_clk_disable_audio(hdmi); 1788 1789 return 0; 1790 } 1791 1792 static int mtk_hdmi_resume(struct device *dev) 1793 { 1794 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1795 int ret = 0; 1796 1797 ret = mtk_hdmi_clk_enable_audio(hdmi); 1798 if (ret) { 1799 dev_err(dev, "hdmi resume failed!\n"); 1800 return ret; 1801 } 1802 1803 return 0; 1804 } 1805 #endif 1806 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1807 mtk_hdmi_suspend, mtk_hdmi_resume); 1808 1809 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = { 1810 .tz_disabled = true, 1811 }; 1812 1813 static const struct of_device_id mtk_drm_hdmi_of_ids[] = { 1814 { .compatible = "mediatek,mt2701-hdmi", 1815 .data = &mtk_hdmi_conf_mt2701, 1816 }, 1817 { .compatible = "mediatek,mt8173-hdmi", 1818 }, 1819 {} 1820 }; 1821 1822 static struct platform_driver mtk_hdmi_driver = { 1823 .probe = mtk_drm_hdmi_probe, 1824 .remove = mtk_drm_hdmi_remove, 1825 .driver = { 1826 .name = "mediatek-drm-hdmi", 1827 .of_match_table = mtk_drm_hdmi_of_ids, 1828 .pm = &mtk_hdmi_pm_ops, 1829 }, 1830 }; 1831 1832 static struct platform_driver * const mtk_hdmi_drivers[] = { 1833 &mtk_hdmi_ddc_driver, 1834 &mtk_cec_driver, 1835 &mtk_hdmi_driver, 1836 }; 1837 1838 static int __init mtk_hdmitx_init(void) 1839 { 1840 return platform_register_drivers(mtk_hdmi_drivers, 1841 ARRAY_SIZE(mtk_hdmi_drivers)); 1842 } 1843 1844 static void __exit mtk_hdmitx_exit(void) 1845 { 1846 platform_unregister_drivers(mtk_hdmi_drivers, 1847 ARRAY_SIZE(mtk_hdmi_drivers)); 1848 } 1849 1850 module_init(mtk_hdmitx_init); 1851 module_exit(mtk_hdmitx_exit); 1852 1853 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1854 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1855 MODULE_LICENSE("GPL v2"); 1856