1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Jie Qiu <jie.qiu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <drm/drmP.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_edid.h> 19 #include <linux/arm-smccc.h> 20 #include <linux/clk.h> 21 #include <linux/delay.h> 22 #include <linux/hdmi.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/of_platform.h> 28 #include <linux/of.h> 29 #include <linux/of_gpio.h> 30 #include <linux/of_graph.h> 31 #include <linux/phy/phy.h> 32 #include <linux/platform_device.h> 33 #include <linux/regmap.h> 34 #include <sound/hdmi-codec.h> 35 #include "mtk_cec.h" 36 #include "mtk_hdmi.h" 37 #include "mtk_hdmi_regs.h" 38 39 #define NCTS_BYTES 7 40 41 enum mtk_hdmi_clk_id { 42 MTK_HDMI_CLK_HDMI_PIXEL, 43 MTK_HDMI_CLK_HDMI_PLL, 44 MTK_HDMI_CLK_AUD_BCLK, 45 MTK_HDMI_CLK_AUD_SPDIF, 46 MTK_HDMI_CLK_COUNT 47 }; 48 49 enum hdmi_aud_input_type { 50 HDMI_AUD_INPUT_I2S = 0, 51 HDMI_AUD_INPUT_SPDIF, 52 }; 53 54 enum hdmi_aud_i2s_fmt { 55 HDMI_I2S_MODE_RJT_24BIT = 0, 56 HDMI_I2S_MODE_RJT_16BIT, 57 HDMI_I2S_MODE_LJT_24BIT, 58 HDMI_I2S_MODE_LJT_16BIT, 59 HDMI_I2S_MODE_I2S_24BIT, 60 HDMI_I2S_MODE_I2S_16BIT 61 }; 62 63 enum hdmi_aud_mclk { 64 HDMI_AUD_MCLK_128FS, 65 HDMI_AUD_MCLK_192FS, 66 HDMI_AUD_MCLK_256FS, 67 HDMI_AUD_MCLK_384FS, 68 HDMI_AUD_MCLK_512FS, 69 HDMI_AUD_MCLK_768FS, 70 HDMI_AUD_MCLK_1152FS, 71 }; 72 73 enum hdmi_aud_channel_type { 74 HDMI_AUD_CHAN_TYPE_1_0 = 0, 75 HDMI_AUD_CHAN_TYPE_1_1, 76 HDMI_AUD_CHAN_TYPE_2_0, 77 HDMI_AUD_CHAN_TYPE_2_1, 78 HDMI_AUD_CHAN_TYPE_3_0, 79 HDMI_AUD_CHAN_TYPE_3_1, 80 HDMI_AUD_CHAN_TYPE_4_0, 81 HDMI_AUD_CHAN_TYPE_4_1, 82 HDMI_AUD_CHAN_TYPE_5_0, 83 HDMI_AUD_CHAN_TYPE_5_1, 84 HDMI_AUD_CHAN_TYPE_6_0, 85 HDMI_AUD_CHAN_TYPE_6_1, 86 HDMI_AUD_CHAN_TYPE_7_0, 87 HDMI_AUD_CHAN_TYPE_7_1, 88 HDMI_AUD_CHAN_TYPE_3_0_LRS, 89 HDMI_AUD_CHAN_TYPE_3_1_LRS, 90 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 91 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 92 HDMI_AUD_CHAN_TYPE_6_1_CS, 93 HDMI_AUD_CHAN_TYPE_6_1_CH, 94 HDMI_AUD_CHAN_TYPE_6_1_OH, 95 HDMI_AUD_CHAN_TYPE_6_1_CHR, 96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 110 HDMI_AUD_CHAN_TYPE_6_0_CS, 111 HDMI_AUD_CHAN_TYPE_6_0_CH, 112 HDMI_AUD_CHAN_TYPE_6_0_OH, 113 HDMI_AUD_CHAN_TYPE_6_0_CHR, 114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 129 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 130 }; 131 132 enum hdmi_aud_channel_swap_type { 133 HDMI_AUD_SWAP_LR, 134 HDMI_AUD_SWAP_LFE_CC, 135 HDMI_AUD_SWAP_LSRS, 136 HDMI_AUD_SWAP_RLS_RRS, 137 HDMI_AUD_SWAP_LR_STATUS, 138 }; 139 140 struct hdmi_audio_param { 141 enum hdmi_audio_coding_type aud_codec; 142 enum hdmi_audio_sample_size aud_sampe_size; 143 enum hdmi_aud_input_type aud_input_type; 144 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 145 enum hdmi_aud_mclk aud_mclk; 146 enum hdmi_aud_channel_type aud_input_chan_type; 147 struct hdmi_codec_params codec_params; 148 }; 149 150 struct mtk_hdmi { 151 struct drm_bridge bridge; 152 struct drm_bridge *next_bridge; 153 struct drm_connector conn; 154 struct device *dev; 155 struct phy *phy; 156 struct device *cec_dev; 157 struct i2c_adapter *ddc_adpt; 158 struct clk *clk[MTK_HDMI_CLK_COUNT]; 159 struct drm_display_mode mode; 160 bool dvi_mode; 161 u32 min_clock; 162 u32 max_clock; 163 u32 max_hdisplay; 164 u32 max_vdisplay; 165 u32 ibias; 166 u32 ibias_up; 167 struct regmap *sys_regmap; 168 unsigned int sys_offset; 169 void __iomem *regs; 170 enum hdmi_colorspace csp; 171 struct hdmi_audio_param aud_param; 172 bool audio_enable; 173 bool powered; 174 bool enabled; 175 }; 176 177 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 178 { 179 return container_of(b, struct mtk_hdmi, bridge); 180 } 181 182 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) 183 { 184 return container_of(c, struct mtk_hdmi, conn); 185 } 186 187 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 188 { 189 return readl(hdmi->regs + offset); 190 } 191 192 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 193 { 194 writel(val, hdmi->regs + offset); 195 } 196 197 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 198 { 199 void __iomem *reg = hdmi->regs + offset; 200 u32 tmp; 201 202 tmp = readl(reg); 203 tmp &= ~bits; 204 writel(tmp, reg); 205 } 206 207 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 208 { 209 void __iomem *reg = hdmi->regs + offset; 210 u32 tmp; 211 212 tmp = readl(reg); 213 tmp |= bits; 214 writel(tmp, reg); 215 } 216 217 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 218 { 219 void __iomem *reg = hdmi->regs + offset; 220 u32 tmp; 221 222 tmp = readl(reg); 223 tmp = (tmp & ~mask) | (val & mask); 224 writel(tmp, reg); 225 } 226 227 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 228 { 229 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 230 VIDEO_SOURCE_SEL); 231 } 232 233 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 234 { 235 struct arm_smccc_res res; 236 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy); 237 238 /* 239 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 240 * output. This bit can only be controlled in ARM supervisor mode. 241 * The ARM trusted firmware provides an API for the HDMI driver to set 242 * this control bit to enable HDMI output in supervisor mode. 243 */ 244 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000, 245 0, 0, 0, 0, 0, &res); 246 247 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 248 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 249 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 250 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 251 } 252 253 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 254 { 255 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 256 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 257 } 258 259 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 260 { 261 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 262 } 263 264 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 265 { 266 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 267 } 268 269 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 270 { 271 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 272 HDMI_RST, HDMI_RST); 273 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 274 HDMI_RST, 0); 275 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 276 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 277 ANLG_ON, ANLG_ON); 278 } 279 280 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 281 { 282 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 283 CFG2_NOTICE_EN); 284 } 285 286 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 287 { 288 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 289 } 290 291 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 292 { 293 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 294 } 295 296 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 297 u8 len) 298 { 299 u32 ctrl_reg = GRL_CTRL; 300 int i; 301 u8 *frame_data; 302 enum hdmi_infoframe_type frame_type; 303 u8 frame_ver; 304 u8 frame_len; 305 u8 checksum; 306 int ctrl_frame_en = 0; 307 308 frame_type = *buffer; 309 buffer += 1; 310 frame_ver = *buffer; 311 buffer += 1; 312 frame_len = *buffer; 313 buffer += 1; 314 checksum = *buffer; 315 buffer += 1; 316 frame_data = buffer; 317 318 dev_dbg(hdmi->dev, 319 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 320 frame_type, frame_ver, frame_len, checksum); 321 322 switch (frame_type) { 323 case HDMI_INFOFRAME_TYPE_AVI: 324 ctrl_frame_en = CTRL_AVI_EN; 325 ctrl_reg = GRL_CTRL; 326 break; 327 case HDMI_INFOFRAME_TYPE_SPD: 328 ctrl_frame_en = CTRL_SPD_EN; 329 ctrl_reg = GRL_CTRL; 330 break; 331 case HDMI_INFOFRAME_TYPE_AUDIO: 332 ctrl_frame_en = CTRL_AUDIO_EN; 333 ctrl_reg = GRL_CTRL; 334 break; 335 case HDMI_INFOFRAME_TYPE_VENDOR: 336 ctrl_frame_en = VS_EN; 337 ctrl_reg = GRL_ACP_ISRC_CTRL; 338 break; 339 } 340 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 341 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 342 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 343 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 344 345 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 346 for (i = 0; i < frame_len; i++) 347 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 348 349 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 350 } 351 352 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 353 { 354 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 355 AUDIO_PACKET_OFF); 356 } 357 358 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 359 { 360 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 361 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 362 usleep_range(2000, 4000); 363 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 364 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 365 } 366 367 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 368 { 369 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 370 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 371 COLOR_8BIT_MODE); 372 } 373 374 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 375 { 376 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 377 usleep_range(2000, 4000); 378 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 379 } 380 381 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 382 { 383 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 384 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 385 usleep_range(2000, 4000); 386 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 387 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 388 } 389 390 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 391 { 392 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 393 CTS_CTRL_SOFT); 394 } 395 396 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 397 bool enable) 398 { 399 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 400 NCTS_WRI_ANYTIME); 401 } 402 403 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 404 struct drm_display_mode *mode) 405 { 406 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 407 408 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 409 mode->clock == 74250 && 410 mode->vdisplay == 1080) 411 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 412 else 413 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 414 } 415 416 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 417 enum hdmi_aud_channel_swap_type swap) 418 { 419 u8 swap_bit; 420 421 switch (swap) { 422 case HDMI_AUD_SWAP_LR: 423 swap_bit = LR_SWAP; 424 break; 425 case HDMI_AUD_SWAP_LFE_CC: 426 swap_bit = LFE_CC_SWAP; 427 break; 428 case HDMI_AUD_SWAP_LSRS: 429 swap_bit = LSRS_SWAP; 430 break; 431 case HDMI_AUD_SWAP_RLS_RRS: 432 swap_bit = RLS_RRS_SWAP; 433 break; 434 case HDMI_AUD_SWAP_LR_STATUS: 435 swap_bit = LR_STATUS_SWAP; 436 break; 437 default: 438 swap_bit = LFE_CC_SWAP; 439 break; 440 } 441 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 442 } 443 444 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 445 enum hdmi_audio_sample_size bit_num) 446 { 447 u32 val; 448 449 switch (bit_num) { 450 case HDMI_AUDIO_SAMPLE_SIZE_16: 451 val = AOUT_16BIT; 452 break; 453 case HDMI_AUDIO_SAMPLE_SIZE_20: 454 val = AOUT_20BIT; 455 break; 456 case HDMI_AUDIO_SAMPLE_SIZE_24: 457 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 458 val = AOUT_24BIT; 459 break; 460 } 461 462 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 463 } 464 465 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 466 enum hdmi_aud_i2s_fmt i2s_fmt) 467 { 468 u32 val; 469 470 val = mtk_hdmi_read(hdmi, GRL_CFG0); 471 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 472 473 switch (i2s_fmt) { 474 case HDMI_I2S_MODE_RJT_24BIT: 475 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 476 break; 477 case HDMI_I2S_MODE_RJT_16BIT: 478 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 479 break; 480 case HDMI_I2S_MODE_LJT_24BIT: 481 default: 482 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 483 break; 484 case HDMI_I2S_MODE_LJT_16BIT: 485 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 486 break; 487 case HDMI_I2S_MODE_I2S_24BIT: 488 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 489 break; 490 case HDMI_I2S_MODE_I2S_16BIT: 491 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 492 break; 493 } 494 mtk_hdmi_write(hdmi, GRL_CFG0, val); 495 } 496 497 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 498 { 499 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 500 u8 val; 501 502 /* Disable high bitrate, set DST packet normal/double */ 503 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 504 505 if (dst) 506 val = DST_NORMAL_DOUBLE | SACD_DST; 507 else 508 val = 0; 509 510 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 511 } 512 513 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 514 enum hdmi_aud_channel_type channel_type, 515 u8 channel_count) 516 { 517 unsigned int ch_switch; 518 u8 i2s_uv; 519 520 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 521 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 522 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 523 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 524 525 if (channel_count == 2) { 526 i2s_uv = I2S_UV_CH_EN(0); 527 } else if (channel_count == 3 || channel_count == 4) { 528 if (channel_count == 4 && 529 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 530 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 531 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 532 else 533 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 534 } else if (channel_count == 6 || channel_count == 5) { 535 if (channel_count == 6 && 536 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 537 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 538 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 539 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 540 } else { 541 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 542 I2S_UV_CH_EN(0); 543 } 544 } else if (channel_count == 8 || channel_count == 7) { 545 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 546 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 547 } else { 548 i2s_uv = I2S_UV_CH_EN(0); 549 } 550 551 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 552 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 553 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 554 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 555 } 556 557 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 558 enum hdmi_aud_input_type input_type) 559 { 560 u32 val; 561 562 val = mtk_hdmi_read(hdmi, GRL_CFG1); 563 if (input_type == HDMI_AUD_INPUT_I2S && 564 (val & CFG1_SPDIF) == CFG1_SPDIF) { 565 val &= ~CFG1_SPDIF; 566 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 567 (val & CFG1_SPDIF) == 0) { 568 val |= CFG1_SPDIF; 569 } 570 mtk_hdmi_write(hdmi, GRL_CFG1, val); 571 } 572 573 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 574 u8 *channel_status) 575 { 576 int i; 577 578 for (i = 0; i < 5; i++) { 579 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 580 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 581 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 582 } 583 for (; i < 24; i++) { 584 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 585 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 586 } 587 } 588 589 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 590 { 591 u32 val; 592 593 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 594 if (val & MIX_CTRL_SRC_EN) { 595 val &= ~MIX_CTRL_SRC_EN; 596 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 597 usleep_range(255, 512); 598 val |= MIX_CTRL_SRC_EN; 599 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 600 } 601 } 602 603 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 604 { 605 u32 val; 606 607 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 608 val &= ~MIX_CTRL_SRC_EN; 609 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 610 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 611 } 612 613 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 614 enum hdmi_aud_mclk mclk) 615 { 616 u32 val; 617 618 val = mtk_hdmi_read(hdmi, GRL_CFG5); 619 val &= CFG5_CD_RATIO_MASK; 620 621 switch (mclk) { 622 case HDMI_AUD_MCLK_128FS: 623 val |= CFG5_FS128; 624 break; 625 case HDMI_AUD_MCLK_256FS: 626 val |= CFG5_FS256; 627 break; 628 case HDMI_AUD_MCLK_384FS: 629 val |= CFG5_FS384; 630 break; 631 case HDMI_AUD_MCLK_512FS: 632 val |= CFG5_FS512; 633 break; 634 case HDMI_AUD_MCLK_768FS: 635 val |= CFG5_FS768; 636 break; 637 default: 638 val |= CFG5_FS256; 639 break; 640 } 641 mtk_hdmi_write(hdmi, GRL_CFG5, val); 642 } 643 644 struct hdmi_acr_n { 645 unsigned int clock; 646 unsigned int n[3]; 647 }; 648 649 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 650 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 651 /* Clock, N: 32kHz 44.1kHz 48kHz */ 652 { 25175, { 4576, 7007, 6864 } }, 653 { 74176, { 11648, 17836, 11648 } }, 654 { 148352, { 11648, 8918, 5824 } }, 655 { 296703, { 5824, 4459, 5824 } }, 656 { 297000, { 3072, 4704, 5120 } }, 657 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 658 }; 659 660 /** 661 * hdmi_recommended_n() - Return N value recommended by HDMI specification 662 * @freq: audio sample rate in Hz 663 * @clock: rounded TMDS clock in kHz 664 */ 665 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 666 { 667 const struct hdmi_acr_n *recommended; 668 unsigned int i; 669 670 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 671 if (clock == hdmi_rec_n_table[i].clock) 672 break; 673 } 674 recommended = hdmi_rec_n_table + i; 675 676 switch (freq) { 677 case 32000: 678 return recommended->n[0]; 679 case 44100: 680 return recommended->n[1]; 681 case 48000: 682 return recommended->n[2]; 683 case 88200: 684 return recommended->n[1] * 2; 685 case 96000: 686 return recommended->n[2] * 2; 687 case 176400: 688 return recommended->n[1] * 4; 689 case 192000: 690 return recommended->n[2] * 4; 691 default: 692 return (128 * freq) / 1000; 693 } 694 } 695 696 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 697 { 698 switch (clock) { 699 case 25175: 700 return 25174825; /* 25.2/1.001 MHz */ 701 case 74176: 702 return 74175824; /* 74.25/1.001 MHz */ 703 case 148352: 704 return 148351648; /* 148.5/1.001 MHz */ 705 case 296703: 706 return 296703297; /* 297/1.001 MHz */ 707 default: 708 return clock * 1000; 709 } 710 } 711 712 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 713 unsigned int tmds_clock, unsigned int n) 714 { 715 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 716 128 * audio_sample_rate); 717 } 718 719 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 720 unsigned int cts) 721 { 722 unsigned char val[NCTS_BYTES]; 723 int i; 724 725 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 726 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 727 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 728 memset(val, 0, sizeof(val)); 729 730 val[0] = (cts >> 24) & 0xff; 731 val[1] = (cts >> 16) & 0xff; 732 val[2] = (cts >> 8) & 0xff; 733 val[3] = cts & 0xff; 734 735 val[4] = (n >> 16) & 0xff; 736 val[5] = (n >> 8) & 0xff; 737 val[6] = n & 0xff; 738 739 for (i = 0; i < NCTS_BYTES; i++) 740 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 741 } 742 743 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 744 unsigned int sample_rate, 745 unsigned int clock) 746 { 747 unsigned int n, cts; 748 749 n = hdmi_recommended_n(sample_rate, clock); 750 cts = hdmi_expected_cts(sample_rate, clock, n); 751 752 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 753 __func__, sample_rate, clock, n, cts); 754 755 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 756 AUDIO_I2S_NCTS_SEL); 757 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 758 } 759 760 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 761 { 762 switch (channel_type) { 763 case HDMI_AUD_CHAN_TYPE_1_0: 764 case HDMI_AUD_CHAN_TYPE_1_1: 765 case HDMI_AUD_CHAN_TYPE_2_0: 766 return 2; 767 case HDMI_AUD_CHAN_TYPE_2_1: 768 case HDMI_AUD_CHAN_TYPE_3_0: 769 return 3; 770 case HDMI_AUD_CHAN_TYPE_3_1: 771 case HDMI_AUD_CHAN_TYPE_4_0: 772 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 773 return 4; 774 case HDMI_AUD_CHAN_TYPE_4_1: 775 case HDMI_AUD_CHAN_TYPE_5_0: 776 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 777 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 778 return 5; 779 case HDMI_AUD_CHAN_TYPE_5_1: 780 case HDMI_AUD_CHAN_TYPE_6_0: 781 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 782 case HDMI_AUD_CHAN_TYPE_6_0_CS: 783 case HDMI_AUD_CHAN_TYPE_6_0_CH: 784 case HDMI_AUD_CHAN_TYPE_6_0_OH: 785 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 786 return 6; 787 case HDMI_AUD_CHAN_TYPE_6_1: 788 case HDMI_AUD_CHAN_TYPE_6_1_CS: 789 case HDMI_AUD_CHAN_TYPE_6_1_CH: 790 case HDMI_AUD_CHAN_TYPE_6_1_OH: 791 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 792 case HDMI_AUD_CHAN_TYPE_7_0: 793 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 794 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 795 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 796 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 797 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 798 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 799 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 800 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 801 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 802 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 803 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 804 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 805 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 806 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 807 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 808 return 7; 809 case HDMI_AUD_CHAN_TYPE_7_1: 810 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 811 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 812 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 813 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 814 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 815 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 816 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 817 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 818 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 819 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 820 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 821 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 822 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 823 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 824 return 8; 825 default: 826 return 2; 827 } 828 } 829 830 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 831 { 832 unsigned long rate; 833 int ret; 834 835 /* The DPI driver already should have set TVDPLL to the correct rate */ 836 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 837 if (ret) { 838 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 839 ret); 840 return ret; 841 } 842 843 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 844 845 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 846 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 847 rate); 848 else 849 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 850 851 mtk_hdmi_hw_config_sys(hdmi); 852 mtk_hdmi_hw_set_deep_color_mode(hdmi); 853 return 0; 854 } 855 856 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 857 struct drm_display_mode *mode) 858 { 859 mtk_hdmi_hw_reset(hdmi); 860 mtk_hdmi_hw_enable_notice(hdmi, true); 861 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 862 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 863 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 864 865 mtk_hdmi_hw_msic_setting(hdmi, mode); 866 } 867 868 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable) 869 { 870 mtk_hdmi_hw_send_aud_packet(hdmi, enable); 871 return 0; 872 } 873 874 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on) 875 { 876 mtk_hdmi_hw_ncts_enable(hdmi, on); 877 return 0; 878 } 879 880 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 881 { 882 enum hdmi_aud_channel_type chan_type; 883 u8 chan_count; 884 bool dst; 885 886 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 887 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 888 889 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 890 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 891 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 892 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 893 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 894 } 895 896 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 897 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 898 899 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 900 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 901 mtk_hdmi_hw_audio_config(hdmi, dst); 902 903 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 904 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 905 else 906 chan_type = hdmi->aud_param.aud_input_chan_type; 907 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 908 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 909 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 910 911 return 0; 912 } 913 914 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 915 struct drm_display_mode *display_mode) 916 { 917 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 918 919 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false); 920 mtk_hdmi_hw_aud_src_disable(hdmi); 921 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 922 923 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 924 switch (sample_rate) { 925 case 32000: 926 case 44100: 927 case 48000: 928 case 88200: 929 case 96000: 930 break; 931 default: 932 return -EINVAL; 933 } 934 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 935 } else { 936 switch (sample_rate) { 937 case 32000: 938 case 44100: 939 case 48000: 940 break; 941 default: 942 return -EINVAL; 943 } 944 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 945 } 946 947 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 948 949 mtk_hdmi_hw_aud_src_reenable(hdmi); 950 return 0; 951 } 952 953 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 954 struct drm_display_mode *display_mode) 955 { 956 mtk_hdmi_hw_aud_mute(hdmi); 957 mtk_hdmi_aud_enable_packet(hdmi, false); 958 959 mtk_hdmi_aud_set_input(hdmi); 960 mtk_hdmi_aud_set_src(hdmi, display_mode); 961 mtk_hdmi_hw_aud_set_channel_status(hdmi, 962 hdmi->aud_param.codec_params.iec.status); 963 964 usleep_range(50, 100); 965 966 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true); 967 mtk_hdmi_aud_enable_packet(hdmi, true); 968 mtk_hdmi_hw_aud_unmute(hdmi); 969 return 0; 970 } 971 972 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 973 struct drm_display_mode *mode) 974 { 975 struct hdmi_avi_infoframe frame; 976 u8 buffer[17]; 977 ssize_t err; 978 979 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 980 if (err < 0) { 981 dev_err(hdmi->dev, 982 "Failed to get AVI infoframe from mode: %zd\n", err); 983 return err; 984 } 985 986 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 987 if (err < 0) { 988 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 989 return err; 990 } 991 992 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 993 return 0; 994 } 995 996 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 997 const char *vendor, 998 const char *product) 999 { 1000 struct hdmi_spd_infoframe frame; 1001 u8 buffer[29]; 1002 ssize_t err; 1003 1004 err = hdmi_spd_infoframe_init(&frame, vendor, product); 1005 if (err < 0) { 1006 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 1007 err); 1008 return err; 1009 } 1010 1011 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 1012 if (err < 0) { 1013 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1014 return err; 1015 } 1016 1017 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1018 return 0; 1019 } 1020 1021 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1022 { 1023 struct hdmi_audio_infoframe frame; 1024 u8 buffer[14]; 1025 ssize_t err; 1026 1027 err = hdmi_audio_infoframe_init(&frame); 1028 if (err < 0) { 1029 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1030 err); 1031 return err; 1032 } 1033 1034 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1035 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1036 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1037 frame.channels = mtk_hdmi_aud_get_chnl_count( 1038 hdmi->aud_param.aud_input_chan_type); 1039 1040 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1041 if (err < 0) { 1042 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1043 err); 1044 return err; 1045 } 1046 1047 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1048 return 0; 1049 } 1050 1051 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1052 struct drm_display_mode *mode) 1053 { 1054 struct hdmi_vendor_infoframe frame; 1055 u8 buffer[10]; 1056 ssize_t err; 1057 1058 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1059 &hdmi->conn, mode); 1060 if (err) { 1061 dev_err(hdmi->dev, 1062 "Failed to get vendor infoframe from mode: %zd\n", err); 1063 return err; 1064 } 1065 1066 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1067 if (err < 0) { 1068 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1069 err); 1070 return err; 1071 } 1072 1073 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1074 return 0; 1075 } 1076 1077 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1078 { 1079 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1080 1081 hdmi->csp = HDMI_COLORSPACE_RGB; 1082 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1083 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1084 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1085 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1086 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1087 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1088 1089 return 0; 1090 } 1091 1092 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1093 { 1094 mtk_hdmi_aud_enable_packet(hdmi, true); 1095 hdmi->audio_enable = true; 1096 } 1097 1098 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1099 { 1100 mtk_hdmi_aud_enable_packet(hdmi, false); 1101 hdmi->audio_enable = false; 1102 } 1103 1104 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1105 struct hdmi_audio_param *param) 1106 { 1107 if (!hdmi->audio_enable) { 1108 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1109 return -EINVAL; 1110 } 1111 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1112 param->aud_codec, param->aud_input_type, 1113 param->aud_input_chan_type, param->codec_params.sample_rate); 1114 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1115 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1116 } 1117 1118 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1119 struct drm_display_mode *mode) 1120 { 1121 int ret; 1122 1123 mtk_hdmi_hw_vid_black(hdmi, true); 1124 mtk_hdmi_hw_aud_mute(hdmi); 1125 mtk_hdmi_hw_send_av_mute(hdmi); 1126 phy_power_off(hdmi->phy); 1127 1128 ret = mtk_hdmi_video_change_vpll(hdmi, 1129 mode->clock * 1000); 1130 if (ret) { 1131 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1132 return ret; 1133 } 1134 mtk_hdmi_video_set_display_mode(hdmi, mode); 1135 1136 phy_power_on(hdmi->phy); 1137 mtk_hdmi_aud_output_config(hdmi, mode); 1138 1139 mtk_hdmi_hw_vid_black(hdmi, false); 1140 mtk_hdmi_hw_aud_unmute(hdmi); 1141 mtk_hdmi_hw_send_av_unmute(hdmi); 1142 1143 return 0; 1144 } 1145 1146 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1147 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1148 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1149 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1150 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1151 }; 1152 1153 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1154 struct device_node *np) 1155 { 1156 int i; 1157 1158 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1159 hdmi->clk[i] = of_clk_get_by_name(np, 1160 mtk_hdmi_clk_names[i]); 1161 if (IS_ERR(hdmi->clk[i])) 1162 return PTR_ERR(hdmi->clk[i]); 1163 } 1164 return 0; 1165 } 1166 1167 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1168 { 1169 int ret; 1170 1171 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1172 if (ret) 1173 return ret; 1174 1175 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1176 if (ret) 1177 goto err; 1178 1179 return 0; 1180 err: 1181 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1182 return ret; 1183 } 1184 1185 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1186 { 1187 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1188 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1189 } 1190 1191 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, 1192 bool force) 1193 { 1194 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1195 1196 return mtk_cec_hpd_high(hdmi->cec_dev) ? 1197 connector_status_connected : connector_status_disconnected; 1198 } 1199 1200 static void hdmi_conn_destroy(struct drm_connector *conn) 1201 { 1202 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1203 1204 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); 1205 1206 drm_connector_cleanup(conn); 1207 } 1208 1209 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) 1210 { 1211 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1212 struct edid *edid; 1213 int ret; 1214 1215 if (!hdmi->ddc_adpt) 1216 return -ENODEV; 1217 1218 edid = drm_get_edid(conn, hdmi->ddc_adpt); 1219 if (!edid) 1220 return -ENODEV; 1221 1222 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1223 1224 drm_connector_update_edid_property(conn, edid); 1225 1226 ret = drm_add_edid_modes(conn, edid); 1227 kfree(edid); 1228 return ret; 1229 } 1230 1231 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, 1232 struct drm_display_mode *mode) 1233 { 1234 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1235 1236 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1237 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1238 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1239 1240 if (hdmi->bridge.next) { 1241 struct drm_display_mode adjusted_mode; 1242 1243 drm_mode_copy(&adjusted_mode, mode); 1244 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode, 1245 &adjusted_mode)) 1246 return MODE_BAD; 1247 } 1248 1249 if (mode->clock < 27000) 1250 return MODE_CLOCK_LOW; 1251 if (mode->clock > 297000) 1252 return MODE_CLOCK_HIGH; 1253 1254 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1255 } 1256 1257 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) 1258 { 1259 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1260 1261 return hdmi->bridge.encoder; 1262 } 1263 1264 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { 1265 .detect = hdmi_conn_detect, 1266 .fill_modes = drm_helper_probe_single_connector_modes, 1267 .destroy = hdmi_conn_destroy, 1268 .reset = drm_atomic_helper_connector_reset, 1269 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1270 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1271 }; 1272 1273 static const struct drm_connector_helper_funcs 1274 mtk_hdmi_connector_helper_funcs = { 1275 .get_modes = mtk_hdmi_conn_get_modes, 1276 .mode_valid = mtk_hdmi_conn_mode_valid, 1277 .best_encoder = mtk_hdmi_conn_best_enc, 1278 }; 1279 1280 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1281 { 1282 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1283 1284 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) 1285 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1286 } 1287 1288 /* 1289 * Bridge callbacks 1290 */ 1291 1292 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge) 1293 { 1294 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1295 int ret; 1296 1297 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn, 1298 &mtk_hdmi_connector_funcs, 1299 DRM_MODE_CONNECTOR_HDMIA); 1300 if (ret) { 1301 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); 1302 return ret; 1303 } 1304 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); 1305 1306 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; 1307 hdmi->conn.interlace_allowed = true; 1308 hdmi->conn.doublescan_allowed = false; 1309 1310 ret = drm_connector_attach_encoder(&hdmi->conn, 1311 bridge->encoder); 1312 if (ret) { 1313 dev_err(hdmi->dev, 1314 "Failed to attach connector to encoder: %d\n", ret); 1315 return ret; 1316 } 1317 1318 if (hdmi->next_bridge) { 1319 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1320 bridge); 1321 if (ret) { 1322 dev_err(hdmi->dev, 1323 "Failed to attach external bridge: %d\n", ret); 1324 return ret; 1325 } 1326 } 1327 1328 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1329 1330 return 0; 1331 } 1332 1333 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1334 const struct drm_display_mode *mode, 1335 struct drm_display_mode *adjusted_mode) 1336 { 1337 return true; 1338 } 1339 1340 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) 1341 { 1342 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1343 1344 if (!hdmi->enabled) 1345 return; 1346 1347 phy_power_off(hdmi->phy); 1348 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1349 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1350 1351 hdmi->enabled = false; 1352 } 1353 1354 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) 1355 { 1356 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1357 1358 if (!hdmi->powered) 1359 return; 1360 1361 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1362 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1363 1364 hdmi->powered = false; 1365 } 1366 1367 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1368 struct drm_display_mode *mode, 1369 struct drm_display_mode *adjusted_mode) 1370 { 1371 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1372 1373 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1374 adjusted_mode->name, adjusted_mode->hdisplay); 1375 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1376 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1377 adjusted_mode->htotal); 1378 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1379 adjusted_mode->hskew, adjusted_mode->vdisplay); 1380 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1381 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1382 adjusted_mode->vtotal); 1383 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1384 adjusted_mode->vscan, adjusted_mode->flags); 1385 1386 drm_mode_copy(&hdmi->mode, adjusted_mode); 1387 } 1388 1389 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 1390 { 1391 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1392 1393 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1394 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1395 1396 hdmi->powered = true; 1397 } 1398 1399 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1400 struct drm_display_mode *mode) 1401 { 1402 mtk_hdmi_setup_audio_infoframe(hdmi); 1403 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1404 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1405 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1406 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1407 } 1408 1409 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1410 { 1411 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1412 1413 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1414 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1415 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1416 phy_power_on(hdmi->phy); 1417 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1418 1419 hdmi->enabled = true; 1420 } 1421 1422 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1423 .attach = mtk_hdmi_bridge_attach, 1424 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1425 .disable = mtk_hdmi_bridge_disable, 1426 .post_disable = mtk_hdmi_bridge_post_disable, 1427 .mode_set = mtk_hdmi_bridge_mode_set, 1428 .pre_enable = mtk_hdmi_bridge_pre_enable, 1429 .enable = mtk_hdmi_bridge_enable, 1430 }; 1431 1432 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1433 struct platform_device *pdev) 1434 { 1435 struct device *dev = &pdev->dev; 1436 struct device_node *np = dev->of_node; 1437 struct device_node *cec_np, *remote, *i2c_np; 1438 struct platform_device *cec_pdev; 1439 struct regmap *regmap; 1440 struct resource *mem; 1441 int ret; 1442 1443 ret = mtk_hdmi_get_all_clk(hdmi, np); 1444 if (ret) { 1445 dev_err(dev, "Failed to get clocks: %d\n", ret); 1446 return ret; 1447 } 1448 1449 /* The CEC module handles HDMI hotplug detection */ 1450 cec_np = of_find_compatible_node(np->parent, NULL, 1451 "mediatek,mt8173-cec"); 1452 if (!cec_np) { 1453 dev_err(dev, "Failed to find CEC node\n"); 1454 return -EINVAL; 1455 } 1456 1457 cec_pdev = of_find_device_by_node(cec_np); 1458 if (!cec_pdev) { 1459 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1460 cec_np); 1461 return -EPROBE_DEFER; 1462 } 1463 hdmi->cec_dev = &cec_pdev->dev; 1464 1465 /* 1466 * The mediatek,syscon-hdmi property contains a phandle link to the 1467 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1468 * registers it contains. 1469 */ 1470 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1471 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1472 &hdmi->sys_offset); 1473 if (IS_ERR(regmap)) 1474 ret = PTR_ERR(regmap); 1475 if (ret) { 1476 ret = PTR_ERR(regmap); 1477 dev_err(dev, 1478 "Failed to get system configuration registers: %d\n", 1479 ret); 1480 return ret; 1481 } 1482 hdmi->sys_regmap = regmap; 1483 1484 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1485 hdmi->regs = devm_ioremap_resource(dev, mem); 1486 if (IS_ERR(hdmi->regs)) 1487 return PTR_ERR(hdmi->regs); 1488 1489 remote = of_graph_get_remote_node(np, 1, 0); 1490 if (!remote) 1491 return -EINVAL; 1492 1493 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1494 hdmi->next_bridge = of_drm_find_bridge(remote); 1495 if (!hdmi->next_bridge) { 1496 dev_err(dev, "Waiting for external bridge\n"); 1497 of_node_put(remote); 1498 return -EPROBE_DEFER; 1499 } 1500 } 1501 1502 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1503 if (!i2c_np) { 1504 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1505 remote); 1506 of_node_put(remote); 1507 return -EINVAL; 1508 } 1509 of_node_put(remote); 1510 1511 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1512 if (!hdmi->ddc_adpt) { 1513 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1514 return -EINVAL; 1515 } 1516 1517 return 0; 1518 } 1519 1520 /* 1521 * HDMI audio codec callbacks 1522 */ 1523 1524 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1525 struct hdmi_codec_daifmt *daifmt, 1526 struct hdmi_codec_params *params) 1527 { 1528 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1529 struct hdmi_audio_param hdmi_params; 1530 unsigned int chan = params->cea.channels; 1531 1532 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1533 params->sample_rate, params->sample_width, chan); 1534 1535 if (!hdmi->bridge.encoder) 1536 return -ENODEV; 1537 1538 switch (chan) { 1539 case 2: 1540 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1541 break; 1542 case 4: 1543 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1544 break; 1545 case 6: 1546 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1547 break; 1548 case 8: 1549 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1550 break; 1551 default: 1552 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1553 return -EINVAL; 1554 } 1555 1556 switch (params->sample_rate) { 1557 case 32000: 1558 case 44100: 1559 case 48000: 1560 case 88200: 1561 case 96000: 1562 case 176400: 1563 case 192000: 1564 break; 1565 default: 1566 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1567 params->sample_rate); 1568 return -EINVAL; 1569 } 1570 1571 switch (daifmt->fmt) { 1572 case HDMI_I2S: 1573 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1574 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1575 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1576 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1577 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1578 break; 1579 default: 1580 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1581 daifmt->fmt); 1582 return -EINVAL; 1583 } 1584 1585 memcpy(&hdmi_params.codec_params, params, 1586 sizeof(hdmi_params.codec_params)); 1587 1588 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1589 1590 return 0; 1591 } 1592 1593 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1594 { 1595 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1596 1597 dev_dbg(dev, "%s\n", __func__); 1598 1599 mtk_hdmi_audio_enable(hdmi); 1600 1601 return 0; 1602 } 1603 1604 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1605 { 1606 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1607 1608 dev_dbg(dev, "%s\n", __func__); 1609 1610 mtk_hdmi_audio_disable(hdmi); 1611 } 1612 1613 static int 1614 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) 1615 { 1616 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1617 1618 dev_dbg(dev, "%s(%d)\n", __func__, enable); 1619 1620 if (enable) 1621 mtk_hdmi_hw_aud_mute(hdmi); 1622 else 1623 mtk_hdmi_hw_aud_unmute(hdmi); 1624 1625 return 0; 1626 } 1627 1628 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1629 { 1630 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1631 1632 dev_dbg(dev, "%s\n", __func__); 1633 1634 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); 1635 1636 return 0; 1637 } 1638 1639 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1640 .hw_params = mtk_hdmi_audio_hw_params, 1641 .audio_startup = mtk_hdmi_audio_startup, 1642 .audio_shutdown = mtk_hdmi_audio_shutdown, 1643 .digital_mute = mtk_hdmi_audio_digital_mute, 1644 .get_eld = mtk_hdmi_audio_get_eld, 1645 }; 1646 1647 static void mtk_hdmi_register_audio_driver(struct device *dev) 1648 { 1649 struct hdmi_codec_pdata codec_data = { 1650 .ops = &mtk_hdmi_audio_codec_ops, 1651 .max_i2s_channels = 2, 1652 .i2s = 1, 1653 }; 1654 struct platform_device *pdev; 1655 1656 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1657 PLATFORM_DEVID_AUTO, &codec_data, 1658 sizeof(codec_data)); 1659 if (IS_ERR(pdev)) 1660 return; 1661 1662 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1663 } 1664 1665 static int mtk_drm_hdmi_probe(struct platform_device *pdev) 1666 { 1667 struct mtk_hdmi *hdmi; 1668 struct device *dev = &pdev->dev; 1669 int ret; 1670 1671 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1672 if (!hdmi) 1673 return -ENOMEM; 1674 1675 hdmi->dev = dev; 1676 1677 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1678 if (ret) 1679 return ret; 1680 1681 hdmi->phy = devm_phy_get(dev, "hdmi"); 1682 if (IS_ERR(hdmi->phy)) { 1683 ret = PTR_ERR(hdmi->phy); 1684 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); 1685 return ret; 1686 } 1687 1688 platform_set_drvdata(pdev, hdmi); 1689 1690 ret = mtk_hdmi_output_init(hdmi); 1691 if (ret) { 1692 dev_err(dev, "Failed to initialize hdmi output\n"); 1693 return ret; 1694 } 1695 1696 mtk_hdmi_register_audio_driver(dev); 1697 1698 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1699 hdmi->bridge.of_node = pdev->dev.of_node; 1700 drm_bridge_add(&hdmi->bridge); 1701 1702 ret = mtk_hdmi_clk_enable_audio(hdmi); 1703 if (ret) { 1704 dev_err(dev, "Failed to enable audio clocks: %d\n", ret); 1705 goto err_bridge_remove; 1706 } 1707 1708 dev_dbg(dev, "mediatek hdmi probe success\n"); 1709 return 0; 1710 1711 err_bridge_remove: 1712 drm_bridge_remove(&hdmi->bridge); 1713 return ret; 1714 } 1715 1716 static int mtk_drm_hdmi_remove(struct platform_device *pdev) 1717 { 1718 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1719 1720 drm_bridge_remove(&hdmi->bridge); 1721 mtk_hdmi_clk_disable_audio(hdmi); 1722 return 0; 1723 } 1724 1725 #ifdef CONFIG_PM_SLEEP 1726 static int mtk_hdmi_suspend(struct device *dev) 1727 { 1728 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1729 1730 mtk_hdmi_clk_disable_audio(hdmi); 1731 dev_dbg(dev, "hdmi suspend success!\n"); 1732 return 0; 1733 } 1734 1735 static int mtk_hdmi_resume(struct device *dev) 1736 { 1737 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1738 int ret = 0; 1739 1740 ret = mtk_hdmi_clk_enable_audio(hdmi); 1741 if (ret) { 1742 dev_err(dev, "hdmi resume failed!\n"); 1743 return ret; 1744 } 1745 1746 dev_dbg(dev, "hdmi resume success!\n"); 1747 return 0; 1748 } 1749 #endif 1750 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1751 mtk_hdmi_suspend, mtk_hdmi_resume); 1752 1753 static const struct of_device_id mtk_drm_hdmi_of_ids[] = { 1754 { .compatible = "mediatek,mt8173-hdmi", }, 1755 {} 1756 }; 1757 1758 static struct platform_driver mtk_hdmi_driver = { 1759 .probe = mtk_drm_hdmi_probe, 1760 .remove = mtk_drm_hdmi_remove, 1761 .driver = { 1762 .name = "mediatek-drm-hdmi", 1763 .of_match_table = mtk_drm_hdmi_of_ids, 1764 .pm = &mtk_hdmi_pm_ops, 1765 }, 1766 }; 1767 1768 static struct platform_driver * const mtk_hdmi_drivers[] = { 1769 &mtk_hdmi_phy_driver, 1770 &mtk_hdmi_ddc_driver, 1771 &mtk_cec_driver, 1772 &mtk_hdmi_driver, 1773 }; 1774 1775 static int __init mtk_hdmitx_init(void) 1776 { 1777 return platform_register_drivers(mtk_hdmi_drivers, 1778 ARRAY_SIZE(mtk_hdmi_drivers)); 1779 } 1780 1781 static void __exit mtk_hdmitx_exit(void) 1782 { 1783 platform_unregister_drivers(mtk_hdmi_drivers, 1784 ARRAY_SIZE(mtk_hdmi_drivers)); 1785 } 1786 1787 module_init(mtk_hdmitx_init); 1788 module_exit(mtk_hdmitx_exit); 1789 1790 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1791 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1792 MODULE_LICENSE("GPL v2"); 1793