1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Jie Qiu <jie.qiu@mediatek.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/hdmi.h> 11 #include <linux/i2c.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/of_platform.h> 16 #include <linux/of.h> 17 #include <linux/of_gpio.h> 18 #include <linux/of_graph.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 23 #include <sound/hdmi-codec.h> 24 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_probe_helper.h> 31 32 #include "mtk_cec.h" 33 #include "mtk_hdmi.h" 34 #include "mtk_hdmi_regs.h" 35 36 #define NCTS_BYTES 7 37 38 enum mtk_hdmi_clk_id { 39 MTK_HDMI_CLK_HDMI_PIXEL, 40 MTK_HDMI_CLK_HDMI_PLL, 41 MTK_HDMI_CLK_AUD_BCLK, 42 MTK_HDMI_CLK_AUD_SPDIF, 43 MTK_HDMI_CLK_COUNT 44 }; 45 46 enum hdmi_aud_input_type { 47 HDMI_AUD_INPUT_I2S = 0, 48 HDMI_AUD_INPUT_SPDIF, 49 }; 50 51 enum hdmi_aud_i2s_fmt { 52 HDMI_I2S_MODE_RJT_24BIT = 0, 53 HDMI_I2S_MODE_RJT_16BIT, 54 HDMI_I2S_MODE_LJT_24BIT, 55 HDMI_I2S_MODE_LJT_16BIT, 56 HDMI_I2S_MODE_I2S_24BIT, 57 HDMI_I2S_MODE_I2S_16BIT 58 }; 59 60 enum hdmi_aud_mclk { 61 HDMI_AUD_MCLK_128FS, 62 HDMI_AUD_MCLK_192FS, 63 HDMI_AUD_MCLK_256FS, 64 HDMI_AUD_MCLK_384FS, 65 HDMI_AUD_MCLK_512FS, 66 HDMI_AUD_MCLK_768FS, 67 HDMI_AUD_MCLK_1152FS, 68 }; 69 70 enum hdmi_aud_channel_type { 71 HDMI_AUD_CHAN_TYPE_1_0 = 0, 72 HDMI_AUD_CHAN_TYPE_1_1, 73 HDMI_AUD_CHAN_TYPE_2_0, 74 HDMI_AUD_CHAN_TYPE_2_1, 75 HDMI_AUD_CHAN_TYPE_3_0, 76 HDMI_AUD_CHAN_TYPE_3_1, 77 HDMI_AUD_CHAN_TYPE_4_0, 78 HDMI_AUD_CHAN_TYPE_4_1, 79 HDMI_AUD_CHAN_TYPE_5_0, 80 HDMI_AUD_CHAN_TYPE_5_1, 81 HDMI_AUD_CHAN_TYPE_6_0, 82 HDMI_AUD_CHAN_TYPE_6_1, 83 HDMI_AUD_CHAN_TYPE_7_0, 84 HDMI_AUD_CHAN_TYPE_7_1, 85 HDMI_AUD_CHAN_TYPE_3_0_LRS, 86 HDMI_AUD_CHAN_TYPE_3_1_LRS, 87 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 88 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 89 HDMI_AUD_CHAN_TYPE_6_1_CS, 90 HDMI_AUD_CHAN_TYPE_6_1_CH, 91 HDMI_AUD_CHAN_TYPE_6_1_OH, 92 HDMI_AUD_CHAN_TYPE_6_1_CHR, 93 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 94 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 95 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 96 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 97 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 98 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 99 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 100 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 101 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 102 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 103 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 104 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 105 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 106 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 107 HDMI_AUD_CHAN_TYPE_6_0_CS, 108 HDMI_AUD_CHAN_TYPE_6_0_CH, 109 HDMI_AUD_CHAN_TYPE_6_0_OH, 110 HDMI_AUD_CHAN_TYPE_6_0_CHR, 111 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 112 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 113 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 114 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 115 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 116 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 117 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 118 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 119 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 120 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 121 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 122 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 123 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 124 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 125 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 126 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 127 }; 128 129 enum hdmi_aud_channel_swap_type { 130 HDMI_AUD_SWAP_LR, 131 HDMI_AUD_SWAP_LFE_CC, 132 HDMI_AUD_SWAP_LSRS, 133 HDMI_AUD_SWAP_RLS_RRS, 134 HDMI_AUD_SWAP_LR_STATUS, 135 }; 136 137 struct hdmi_audio_param { 138 enum hdmi_audio_coding_type aud_codec; 139 enum hdmi_audio_sample_size aud_sampe_size; 140 enum hdmi_aud_input_type aud_input_type; 141 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 142 enum hdmi_aud_mclk aud_mclk; 143 enum hdmi_aud_channel_type aud_input_chan_type; 144 struct hdmi_codec_params codec_params; 145 }; 146 147 struct mtk_hdmi { 148 struct drm_bridge bridge; 149 struct drm_bridge *next_bridge; 150 struct drm_connector conn; 151 struct device *dev; 152 struct phy *phy; 153 struct device *cec_dev; 154 struct i2c_adapter *ddc_adpt; 155 struct clk *clk[MTK_HDMI_CLK_COUNT]; 156 struct drm_display_mode mode; 157 bool dvi_mode; 158 u32 min_clock; 159 u32 max_clock; 160 u32 max_hdisplay; 161 u32 max_vdisplay; 162 u32 ibias; 163 u32 ibias_up; 164 struct regmap *sys_regmap; 165 unsigned int sys_offset; 166 void __iomem *regs; 167 enum hdmi_colorspace csp; 168 struct hdmi_audio_param aud_param; 169 bool audio_enable; 170 bool powered; 171 bool enabled; 172 hdmi_codec_plugged_cb plugged_cb; 173 struct device *codec_dev; 174 }; 175 176 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 177 { 178 return container_of(b, struct mtk_hdmi, bridge); 179 } 180 181 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) 182 { 183 return container_of(c, struct mtk_hdmi, conn); 184 } 185 186 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 187 { 188 return readl(hdmi->regs + offset); 189 } 190 191 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 192 { 193 writel(val, hdmi->regs + offset); 194 } 195 196 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 197 { 198 void __iomem *reg = hdmi->regs + offset; 199 u32 tmp; 200 201 tmp = readl(reg); 202 tmp &= ~bits; 203 writel(tmp, reg); 204 } 205 206 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 207 { 208 void __iomem *reg = hdmi->regs + offset; 209 u32 tmp; 210 211 tmp = readl(reg); 212 tmp |= bits; 213 writel(tmp, reg); 214 } 215 216 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 217 { 218 void __iomem *reg = hdmi->regs + offset; 219 u32 tmp; 220 221 tmp = readl(reg); 222 tmp = (tmp & ~mask) | (val & mask); 223 writel(tmp, reg); 224 } 225 226 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 227 { 228 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 229 VIDEO_SOURCE_SEL); 230 } 231 232 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 233 { 234 struct arm_smccc_res res; 235 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy); 236 237 /* 238 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 239 * output. This bit can only be controlled in ARM supervisor mode. 240 * The ARM trusted firmware provides an API for the HDMI driver to set 241 * this control bit to enable HDMI output in supervisor mode. 242 */ 243 if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) 244 regmap_update_bits(hdmi->sys_regmap, 245 hdmi->sys_offset + HDMI_SYS_CFG20, 246 0x80008005, enable ? 0x80000005 : 0x8000); 247 else 248 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 249 0x80000000, 0, 0, 0, 0, 0, &res); 250 251 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 252 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 253 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 254 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 255 } 256 257 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 258 { 259 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 260 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 261 } 262 263 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 264 { 265 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 266 } 267 268 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 269 { 270 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 271 } 272 273 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 274 { 275 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 276 HDMI_RST, HDMI_RST); 277 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 278 HDMI_RST, 0); 279 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 280 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 281 ANLG_ON, ANLG_ON); 282 } 283 284 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 285 { 286 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 287 CFG2_NOTICE_EN); 288 } 289 290 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 291 { 292 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 293 } 294 295 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 296 { 297 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 298 } 299 300 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 301 u8 len) 302 { 303 u32 ctrl_reg = GRL_CTRL; 304 int i; 305 u8 *frame_data; 306 enum hdmi_infoframe_type frame_type; 307 u8 frame_ver; 308 u8 frame_len; 309 u8 checksum; 310 int ctrl_frame_en = 0; 311 312 frame_type = *buffer; 313 buffer += 1; 314 frame_ver = *buffer; 315 buffer += 1; 316 frame_len = *buffer; 317 buffer += 1; 318 checksum = *buffer; 319 buffer += 1; 320 frame_data = buffer; 321 322 dev_dbg(hdmi->dev, 323 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 324 frame_type, frame_ver, frame_len, checksum); 325 326 switch (frame_type) { 327 case HDMI_INFOFRAME_TYPE_AVI: 328 ctrl_frame_en = CTRL_AVI_EN; 329 ctrl_reg = GRL_CTRL; 330 break; 331 case HDMI_INFOFRAME_TYPE_SPD: 332 ctrl_frame_en = CTRL_SPD_EN; 333 ctrl_reg = GRL_CTRL; 334 break; 335 case HDMI_INFOFRAME_TYPE_AUDIO: 336 ctrl_frame_en = CTRL_AUDIO_EN; 337 ctrl_reg = GRL_CTRL; 338 break; 339 case HDMI_INFOFRAME_TYPE_VENDOR: 340 ctrl_frame_en = VS_EN; 341 ctrl_reg = GRL_ACP_ISRC_CTRL; 342 break; 343 default: 344 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 345 return; 346 } 347 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 348 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 349 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 350 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 351 352 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 353 for (i = 0; i < frame_len; i++) 354 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 355 356 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 357 } 358 359 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 360 { 361 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 362 AUDIO_PACKET_OFF); 363 } 364 365 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 366 { 367 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 368 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 369 usleep_range(2000, 4000); 370 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 371 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 372 } 373 374 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 375 { 376 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 377 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 378 COLOR_8BIT_MODE); 379 } 380 381 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 382 { 383 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 384 usleep_range(2000, 4000); 385 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 386 } 387 388 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 389 { 390 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 391 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 392 usleep_range(2000, 4000); 393 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 394 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 395 } 396 397 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 398 { 399 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 400 CTS_CTRL_SOFT); 401 } 402 403 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 404 bool enable) 405 { 406 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 407 NCTS_WRI_ANYTIME); 408 } 409 410 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 411 struct drm_display_mode *mode) 412 { 413 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 414 415 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 416 mode->clock == 74250 && 417 mode->vdisplay == 1080) 418 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 419 else 420 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 421 } 422 423 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 424 enum hdmi_aud_channel_swap_type swap) 425 { 426 u8 swap_bit; 427 428 switch (swap) { 429 case HDMI_AUD_SWAP_LR: 430 swap_bit = LR_SWAP; 431 break; 432 case HDMI_AUD_SWAP_LFE_CC: 433 swap_bit = LFE_CC_SWAP; 434 break; 435 case HDMI_AUD_SWAP_LSRS: 436 swap_bit = LSRS_SWAP; 437 break; 438 case HDMI_AUD_SWAP_RLS_RRS: 439 swap_bit = RLS_RRS_SWAP; 440 break; 441 case HDMI_AUD_SWAP_LR_STATUS: 442 swap_bit = LR_STATUS_SWAP; 443 break; 444 default: 445 swap_bit = LFE_CC_SWAP; 446 break; 447 } 448 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 449 } 450 451 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 452 enum hdmi_audio_sample_size bit_num) 453 { 454 u32 val; 455 456 switch (bit_num) { 457 case HDMI_AUDIO_SAMPLE_SIZE_16: 458 val = AOUT_16BIT; 459 break; 460 case HDMI_AUDIO_SAMPLE_SIZE_20: 461 val = AOUT_20BIT; 462 break; 463 case HDMI_AUDIO_SAMPLE_SIZE_24: 464 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 465 val = AOUT_24BIT; 466 break; 467 } 468 469 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 470 } 471 472 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 473 enum hdmi_aud_i2s_fmt i2s_fmt) 474 { 475 u32 val; 476 477 val = mtk_hdmi_read(hdmi, GRL_CFG0); 478 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 479 480 switch (i2s_fmt) { 481 case HDMI_I2S_MODE_RJT_24BIT: 482 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 483 break; 484 case HDMI_I2S_MODE_RJT_16BIT: 485 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 486 break; 487 case HDMI_I2S_MODE_LJT_24BIT: 488 default: 489 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 490 break; 491 case HDMI_I2S_MODE_LJT_16BIT: 492 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 493 break; 494 case HDMI_I2S_MODE_I2S_24BIT: 495 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 496 break; 497 case HDMI_I2S_MODE_I2S_16BIT: 498 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 499 break; 500 } 501 mtk_hdmi_write(hdmi, GRL_CFG0, val); 502 } 503 504 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 505 { 506 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 507 u8 val; 508 509 /* Disable high bitrate, set DST packet normal/double */ 510 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 511 512 if (dst) 513 val = DST_NORMAL_DOUBLE | SACD_DST; 514 else 515 val = 0; 516 517 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 518 } 519 520 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 521 enum hdmi_aud_channel_type channel_type, 522 u8 channel_count) 523 { 524 unsigned int ch_switch; 525 u8 i2s_uv; 526 527 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 528 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 529 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 530 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 531 532 if (channel_count == 2) { 533 i2s_uv = I2S_UV_CH_EN(0); 534 } else if (channel_count == 3 || channel_count == 4) { 535 if (channel_count == 4 && 536 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 537 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 538 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 539 else 540 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 541 } else if (channel_count == 6 || channel_count == 5) { 542 if (channel_count == 6 && 543 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 544 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 545 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 546 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 547 } else { 548 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 549 I2S_UV_CH_EN(0); 550 } 551 } else if (channel_count == 8 || channel_count == 7) { 552 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 553 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 554 } else { 555 i2s_uv = I2S_UV_CH_EN(0); 556 } 557 558 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 559 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 560 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 561 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 562 } 563 564 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 565 enum hdmi_aud_input_type input_type) 566 { 567 u32 val; 568 569 val = mtk_hdmi_read(hdmi, GRL_CFG1); 570 if (input_type == HDMI_AUD_INPUT_I2S && 571 (val & CFG1_SPDIF) == CFG1_SPDIF) { 572 val &= ~CFG1_SPDIF; 573 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 574 (val & CFG1_SPDIF) == 0) { 575 val |= CFG1_SPDIF; 576 } 577 mtk_hdmi_write(hdmi, GRL_CFG1, val); 578 } 579 580 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 581 u8 *channel_status) 582 { 583 int i; 584 585 for (i = 0; i < 5; i++) { 586 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 587 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 588 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 589 } 590 for (; i < 24; i++) { 591 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 592 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 593 } 594 } 595 596 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 597 { 598 u32 val; 599 600 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 601 if (val & MIX_CTRL_SRC_EN) { 602 val &= ~MIX_CTRL_SRC_EN; 603 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 604 usleep_range(255, 512); 605 val |= MIX_CTRL_SRC_EN; 606 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 607 } 608 } 609 610 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 611 { 612 u32 val; 613 614 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 615 val &= ~MIX_CTRL_SRC_EN; 616 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 617 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 618 } 619 620 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 621 enum hdmi_aud_mclk mclk) 622 { 623 u32 val; 624 625 val = mtk_hdmi_read(hdmi, GRL_CFG5); 626 val &= CFG5_CD_RATIO_MASK; 627 628 switch (mclk) { 629 case HDMI_AUD_MCLK_128FS: 630 val |= CFG5_FS128; 631 break; 632 case HDMI_AUD_MCLK_256FS: 633 val |= CFG5_FS256; 634 break; 635 case HDMI_AUD_MCLK_384FS: 636 val |= CFG5_FS384; 637 break; 638 case HDMI_AUD_MCLK_512FS: 639 val |= CFG5_FS512; 640 break; 641 case HDMI_AUD_MCLK_768FS: 642 val |= CFG5_FS768; 643 break; 644 default: 645 val |= CFG5_FS256; 646 break; 647 } 648 mtk_hdmi_write(hdmi, GRL_CFG5, val); 649 } 650 651 struct hdmi_acr_n { 652 unsigned int clock; 653 unsigned int n[3]; 654 }; 655 656 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 657 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 658 /* Clock, N: 32kHz 44.1kHz 48kHz */ 659 { 25175, { 4576, 7007, 6864 } }, 660 { 74176, { 11648, 17836, 11648 } }, 661 { 148352, { 11648, 8918, 5824 } }, 662 { 296703, { 5824, 4459, 5824 } }, 663 { 297000, { 3072, 4704, 5120 } }, 664 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 665 }; 666 667 /** 668 * hdmi_recommended_n() - Return N value recommended by HDMI specification 669 * @freq: audio sample rate in Hz 670 * @clock: rounded TMDS clock in kHz 671 */ 672 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 673 { 674 const struct hdmi_acr_n *recommended; 675 unsigned int i; 676 677 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 678 if (clock == hdmi_rec_n_table[i].clock) 679 break; 680 } 681 recommended = hdmi_rec_n_table + i; 682 683 switch (freq) { 684 case 32000: 685 return recommended->n[0]; 686 case 44100: 687 return recommended->n[1]; 688 case 48000: 689 return recommended->n[2]; 690 case 88200: 691 return recommended->n[1] * 2; 692 case 96000: 693 return recommended->n[2] * 2; 694 case 176400: 695 return recommended->n[1] * 4; 696 case 192000: 697 return recommended->n[2] * 4; 698 default: 699 return (128 * freq) / 1000; 700 } 701 } 702 703 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 704 { 705 switch (clock) { 706 case 25175: 707 return 25174825; /* 25.2/1.001 MHz */ 708 case 74176: 709 return 74175824; /* 74.25/1.001 MHz */ 710 case 148352: 711 return 148351648; /* 148.5/1.001 MHz */ 712 case 296703: 713 return 296703297; /* 297/1.001 MHz */ 714 default: 715 return clock * 1000; 716 } 717 } 718 719 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 720 unsigned int tmds_clock, unsigned int n) 721 { 722 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 723 128 * audio_sample_rate); 724 } 725 726 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 727 unsigned int cts) 728 { 729 unsigned char val[NCTS_BYTES]; 730 int i; 731 732 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 733 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 734 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 735 memset(val, 0, sizeof(val)); 736 737 val[0] = (cts >> 24) & 0xff; 738 val[1] = (cts >> 16) & 0xff; 739 val[2] = (cts >> 8) & 0xff; 740 val[3] = cts & 0xff; 741 742 val[4] = (n >> 16) & 0xff; 743 val[5] = (n >> 8) & 0xff; 744 val[6] = n & 0xff; 745 746 for (i = 0; i < NCTS_BYTES; i++) 747 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 748 } 749 750 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 751 unsigned int sample_rate, 752 unsigned int clock) 753 { 754 unsigned int n, cts; 755 756 n = hdmi_recommended_n(sample_rate, clock); 757 cts = hdmi_expected_cts(sample_rate, clock, n); 758 759 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 760 __func__, sample_rate, clock, n, cts); 761 762 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 763 AUDIO_I2S_NCTS_SEL); 764 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 765 } 766 767 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 768 { 769 switch (channel_type) { 770 case HDMI_AUD_CHAN_TYPE_1_0: 771 case HDMI_AUD_CHAN_TYPE_1_1: 772 case HDMI_AUD_CHAN_TYPE_2_0: 773 return 2; 774 case HDMI_AUD_CHAN_TYPE_2_1: 775 case HDMI_AUD_CHAN_TYPE_3_0: 776 return 3; 777 case HDMI_AUD_CHAN_TYPE_3_1: 778 case HDMI_AUD_CHAN_TYPE_4_0: 779 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 780 return 4; 781 case HDMI_AUD_CHAN_TYPE_4_1: 782 case HDMI_AUD_CHAN_TYPE_5_0: 783 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 784 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 785 return 5; 786 case HDMI_AUD_CHAN_TYPE_5_1: 787 case HDMI_AUD_CHAN_TYPE_6_0: 788 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 789 case HDMI_AUD_CHAN_TYPE_6_0_CS: 790 case HDMI_AUD_CHAN_TYPE_6_0_CH: 791 case HDMI_AUD_CHAN_TYPE_6_0_OH: 792 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 793 return 6; 794 case HDMI_AUD_CHAN_TYPE_6_1: 795 case HDMI_AUD_CHAN_TYPE_6_1_CS: 796 case HDMI_AUD_CHAN_TYPE_6_1_CH: 797 case HDMI_AUD_CHAN_TYPE_6_1_OH: 798 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 799 case HDMI_AUD_CHAN_TYPE_7_0: 800 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 801 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 802 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 803 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 804 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 805 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 806 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 807 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 808 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 809 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 810 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 811 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 812 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 813 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 814 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 815 return 7; 816 case HDMI_AUD_CHAN_TYPE_7_1: 817 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 818 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 819 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 820 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 821 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 822 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 823 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 824 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 825 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 826 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 827 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 828 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 829 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 830 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 831 return 8; 832 default: 833 return 2; 834 } 835 } 836 837 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 838 { 839 unsigned long rate; 840 int ret; 841 842 /* The DPI driver already should have set TVDPLL to the correct rate */ 843 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 844 if (ret) { 845 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 846 ret); 847 return ret; 848 } 849 850 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 851 852 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 853 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 854 rate); 855 else 856 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 857 858 mtk_hdmi_hw_config_sys(hdmi); 859 mtk_hdmi_hw_set_deep_color_mode(hdmi); 860 return 0; 861 } 862 863 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 864 struct drm_display_mode *mode) 865 { 866 mtk_hdmi_hw_reset(hdmi); 867 mtk_hdmi_hw_enable_notice(hdmi, true); 868 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 869 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 870 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 871 872 mtk_hdmi_hw_msic_setting(hdmi, mode); 873 } 874 875 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable) 876 { 877 mtk_hdmi_hw_send_aud_packet(hdmi, enable); 878 return 0; 879 } 880 881 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on) 882 { 883 mtk_hdmi_hw_ncts_enable(hdmi, on); 884 return 0; 885 } 886 887 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 888 { 889 enum hdmi_aud_channel_type chan_type; 890 u8 chan_count; 891 bool dst; 892 893 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 894 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 895 896 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 897 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 898 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 899 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 900 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 901 } 902 903 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 904 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 905 906 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 907 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 908 mtk_hdmi_hw_audio_config(hdmi, dst); 909 910 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 911 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 912 else 913 chan_type = hdmi->aud_param.aud_input_chan_type; 914 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 915 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 916 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 917 918 return 0; 919 } 920 921 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 922 struct drm_display_mode *display_mode) 923 { 924 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 925 926 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false); 927 mtk_hdmi_hw_aud_src_disable(hdmi); 928 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 929 930 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 931 switch (sample_rate) { 932 case 32000: 933 case 44100: 934 case 48000: 935 case 88200: 936 case 96000: 937 break; 938 default: 939 return -EINVAL; 940 } 941 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 942 } else { 943 switch (sample_rate) { 944 case 32000: 945 case 44100: 946 case 48000: 947 break; 948 default: 949 return -EINVAL; 950 } 951 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 952 } 953 954 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 955 956 mtk_hdmi_hw_aud_src_reenable(hdmi); 957 return 0; 958 } 959 960 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 961 struct drm_display_mode *display_mode) 962 { 963 mtk_hdmi_hw_aud_mute(hdmi); 964 mtk_hdmi_aud_enable_packet(hdmi, false); 965 966 mtk_hdmi_aud_set_input(hdmi); 967 mtk_hdmi_aud_set_src(hdmi, display_mode); 968 mtk_hdmi_hw_aud_set_channel_status(hdmi, 969 hdmi->aud_param.codec_params.iec.status); 970 971 usleep_range(50, 100); 972 973 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true); 974 mtk_hdmi_aud_enable_packet(hdmi, true); 975 mtk_hdmi_hw_aud_unmute(hdmi); 976 return 0; 977 } 978 979 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 980 struct drm_display_mode *mode) 981 { 982 struct hdmi_avi_infoframe frame; 983 u8 buffer[17]; 984 ssize_t err; 985 986 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 987 &hdmi->conn, mode); 988 if (err < 0) { 989 dev_err(hdmi->dev, 990 "Failed to get AVI infoframe from mode: %zd\n", err); 991 return err; 992 } 993 994 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 995 if (err < 0) { 996 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 997 return err; 998 } 999 1000 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1001 return 0; 1002 } 1003 1004 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 1005 const char *vendor, 1006 const char *product) 1007 { 1008 struct hdmi_spd_infoframe frame; 1009 u8 buffer[29]; 1010 ssize_t err; 1011 1012 err = hdmi_spd_infoframe_init(&frame, vendor, product); 1013 if (err < 0) { 1014 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 1015 err); 1016 return err; 1017 } 1018 1019 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 1020 if (err < 0) { 1021 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1022 return err; 1023 } 1024 1025 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1026 return 0; 1027 } 1028 1029 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1030 { 1031 struct hdmi_audio_infoframe frame; 1032 u8 buffer[14]; 1033 ssize_t err; 1034 1035 err = hdmi_audio_infoframe_init(&frame); 1036 if (err < 0) { 1037 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1038 err); 1039 return err; 1040 } 1041 1042 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1043 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1044 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1045 frame.channels = mtk_hdmi_aud_get_chnl_count( 1046 hdmi->aud_param.aud_input_chan_type); 1047 1048 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1049 if (err < 0) { 1050 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1051 err); 1052 return err; 1053 } 1054 1055 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1056 return 0; 1057 } 1058 1059 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1060 struct drm_display_mode *mode) 1061 { 1062 struct hdmi_vendor_infoframe frame; 1063 u8 buffer[10]; 1064 ssize_t err; 1065 1066 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1067 &hdmi->conn, mode); 1068 if (err) { 1069 dev_err(hdmi->dev, 1070 "Failed to get vendor infoframe from mode: %zd\n", err); 1071 return err; 1072 } 1073 1074 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1075 if (err < 0) { 1076 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1077 err); 1078 return err; 1079 } 1080 1081 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1082 return 0; 1083 } 1084 1085 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1086 { 1087 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1088 1089 hdmi->csp = HDMI_COLORSPACE_RGB; 1090 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1091 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1092 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1093 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1094 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1095 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1096 1097 return 0; 1098 } 1099 1100 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1101 { 1102 mtk_hdmi_aud_enable_packet(hdmi, true); 1103 hdmi->audio_enable = true; 1104 } 1105 1106 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1107 { 1108 mtk_hdmi_aud_enable_packet(hdmi, false); 1109 hdmi->audio_enable = false; 1110 } 1111 1112 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1113 struct hdmi_audio_param *param) 1114 { 1115 if (!hdmi->audio_enable) { 1116 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1117 return -EINVAL; 1118 } 1119 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1120 param->aud_codec, param->aud_input_type, 1121 param->aud_input_chan_type, param->codec_params.sample_rate); 1122 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1123 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1124 } 1125 1126 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1127 struct drm_display_mode *mode) 1128 { 1129 int ret; 1130 1131 mtk_hdmi_hw_vid_black(hdmi, true); 1132 mtk_hdmi_hw_aud_mute(hdmi); 1133 mtk_hdmi_hw_send_av_mute(hdmi); 1134 phy_power_off(hdmi->phy); 1135 1136 ret = mtk_hdmi_video_change_vpll(hdmi, 1137 mode->clock * 1000); 1138 if (ret) { 1139 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1140 return ret; 1141 } 1142 mtk_hdmi_video_set_display_mode(hdmi, mode); 1143 1144 phy_power_on(hdmi->phy); 1145 mtk_hdmi_aud_output_config(hdmi, mode); 1146 1147 mtk_hdmi_hw_vid_black(hdmi, false); 1148 mtk_hdmi_hw_aud_unmute(hdmi); 1149 mtk_hdmi_hw_send_av_unmute(hdmi); 1150 1151 return 0; 1152 } 1153 1154 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1155 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1156 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1157 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1158 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1159 }; 1160 1161 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1162 struct device_node *np) 1163 { 1164 int i; 1165 1166 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1167 hdmi->clk[i] = of_clk_get_by_name(np, 1168 mtk_hdmi_clk_names[i]); 1169 if (IS_ERR(hdmi->clk[i])) 1170 return PTR_ERR(hdmi->clk[i]); 1171 } 1172 return 0; 1173 } 1174 1175 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1176 { 1177 int ret; 1178 1179 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1180 if (ret) 1181 return ret; 1182 1183 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1184 if (ret) 1185 goto err; 1186 1187 return 0; 1188 err: 1189 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1190 return ret; 1191 } 1192 1193 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1194 { 1195 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1196 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1197 } 1198 1199 static enum drm_connector_status 1200 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) 1201 { 1202 bool connected = mtk_cec_hpd_high(hdmi->cec_dev); 1203 1204 if (hdmi->plugged_cb && hdmi->codec_dev) 1205 hdmi->plugged_cb(hdmi->codec_dev, connected); 1206 1207 return connected ? 1208 connector_status_connected : connector_status_disconnected; 1209 } 1210 1211 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, 1212 bool force) 1213 { 1214 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1215 return mtk_hdmi_update_plugged_status(hdmi); 1216 } 1217 1218 static void hdmi_conn_destroy(struct drm_connector *conn) 1219 { 1220 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1221 1222 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); 1223 1224 drm_connector_cleanup(conn); 1225 } 1226 1227 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) 1228 { 1229 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1230 struct edid *edid; 1231 int ret; 1232 1233 if (!hdmi->ddc_adpt) 1234 return -ENODEV; 1235 1236 edid = drm_get_edid(conn, hdmi->ddc_adpt); 1237 if (!edid) 1238 return -ENODEV; 1239 1240 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1241 1242 drm_connector_update_edid_property(conn, edid); 1243 1244 ret = drm_add_edid_modes(conn, edid); 1245 kfree(edid); 1246 return ret; 1247 } 1248 1249 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, 1250 struct drm_display_mode *mode) 1251 { 1252 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1253 struct drm_bridge *next_bridge; 1254 1255 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1256 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1257 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1258 1259 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge); 1260 if (next_bridge) { 1261 struct drm_display_mode adjusted_mode; 1262 1263 drm_mode_copy(&adjusted_mode, mode); 1264 if (!drm_bridge_chain_mode_fixup(next_bridge, mode, 1265 &adjusted_mode)) 1266 return MODE_BAD; 1267 } 1268 1269 if (mode->clock < 27000) 1270 return MODE_CLOCK_LOW; 1271 if (mode->clock > 297000) 1272 return MODE_CLOCK_HIGH; 1273 1274 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1275 } 1276 1277 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) 1278 { 1279 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1280 1281 return hdmi->bridge.encoder; 1282 } 1283 1284 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { 1285 .detect = hdmi_conn_detect, 1286 .fill_modes = drm_helper_probe_single_connector_modes, 1287 .destroy = hdmi_conn_destroy, 1288 .reset = drm_atomic_helper_connector_reset, 1289 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1290 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1291 }; 1292 1293 static const struct drm_connector_helper_funcs 1294 mtk_hdmi_connector_helper_funcs = { 1295 .get_modes = mtk_hdmi_conn_get_modes, 1296 .mode_valid = mtk_hdmi_conn_mode_valid, 1297 .best_encoder = mtk_hdmi_conn_best_enc, 1298 }; 1299 1300 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1301 { 1302 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1303 1304 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) 1305 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1306 } 1307 1308 /* 1309 * Bridge callbacks 1310 */ 1311 1312 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge) 1313 { 1314 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1315 int ret; 1316 1317 ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn, 1318 &mtk_hdmi_connector_funcs, 1319 DRM_MODE_CONNECTOR_HDMIA, 1320 hdmi->ddc_adpt); 1321 if (ret) { 1322 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); 1323 return ret; 1324 } 1325 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); 1326 1327 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; 1328 hdmi->conn.interlace_allowed = true; 1329 hdmi->conn.doublescan_allowed = false; 1330 1331 ret = drm_connector_attach_encoder(&hdmi->conn, 1332 bridge->encoder); 1333 if (ret) { 1334 dev_err(hdmi->dev, 1335 "Failed to attach connector to encoder: %d\n", ret); 1336 return ret; 1337 } 1338 1339 if (hdmi->next_bridge) { 1340 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1341 bridge); 1342 if (ret) { 1343 dev_err(hdmi->dev, 1344 "Failed to attach external bridge: %d\n", ret); 1345 return ret; 1346 } 1347 } 1348 1349 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1350 1351 return 0; 1352 } 1353 1354 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1355 const struct drm_display_mode *mode, 1356 struct drm_display_mode *adjusted_mode) 1357 { 1358 return true; 1359 } 1360 1361 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) 1362 { 1363 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1364 1365 if (!hdmi->enabled) 1366 return; 1367 1368 phy_power_off(hdmi->phy); 1369 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1370 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1371 1372 hdmi->enabled = false; 1373 } 1374 1375 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) 1376 { 1377 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1378 1379 if (!hdmi->powered) 1380 return; 1381 1382 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1383 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1384 1385 hdmi->powered = false; 1386 } 1387 1388 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1389 const struct drm_display_mode *mode, 1390 const struct drm_display_mode *adjusted_mode) 1391 { 1392 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1393 1394 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1395 adjusted_mode->name, adjusted_mode->hdisplay); 1396 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1397 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1398 adjusted_mode->htotal); 1399 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1400 adjusted_mode->hskew, adjusted_mode->vdisplay); 1401 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1402 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1403 adjusted_mode->vtotal); 1404 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1405 adjusted_mode->vscan, adjusted_mode->flags); 1406 1407 drm_mode_copy(&hdmi->mode, adjusted_mode); 1408 } 1409 1410 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 1411 { 1412 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1413 1414 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1415 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1416 1417 hdmi->powered = true; 1418 } 1419 1420 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1421 struct drm_display_mode *mode) 1422 { 1423 mtk_hdmi_setup_audio_infoframe(hdmi); 1424 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1425 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1426 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1427 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1428 } 1429 1430 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1431 { 1432 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1433 1434 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1435 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1436 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1437 phy_power_on(hdmi->phy); 1438 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1439 1440 hdmi->enabled = true; 1441 } 1442 1443 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1444 .attach = mtk_hdmi_bridge_attach, 1445 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1446 .disable = mtk_hdmi_bridge_disable, 1447 .post_disable = mtk_hdmi_bridge_post_disable, 1448 .mode_set = mtk_hdmi_bridge_mode_set, 1449 .pre_enable = mtk_hdmi_bridge_pre_enable, 1450 .enable = mtk_hdmi_bridge_enable, 1451 }; 1452 1453 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1454 struct platform_device *pdev) 1455 { 1456 struct device *dev = &pdev->dev; 1457 struct device_node *np = dev->of_node; 1458 struct device_node *cec_np, *remote, *i2c_np; 1459 struct platform_device *cec_pdev; 1460 struct regmap *regmap; 1461 struct resource *mem; 1462 int ret; 1463 1464 ret = mtk_hdmi_get_all_clk(hdmi, np); 1465 if (ret) { 1466 dev_err(dev, "Failed to get clocks: %d\n", ret); 1467 return ret; 1468 } 1469 1470 /* The CEC module handles HDMI hotplug detection */ 1471 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); 1472 if (!cec_np) { 1473 dev_err(dev, "Failed to find CEC node\n"); 1474 return -EINVAL; 1475 } 1476 1477 cec_pdev = of_find_device_by_node(cec_np); 1478 if (!cec_pdev) { 1479 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1480 cec_np); 1481 of_node_put(cec_np); 1482 return -EPROBE_DEFER; 1483 } 1484 of_node_put(cec_np); 1485 hdmi->cec_dev = &cec_pdev->dev; 1486 1487 /* 1488 * The mediatek,syscon-hdmi property contains a phandle link to the 1489 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1490 * registers it contains. 1491 */ 1492 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1493 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1494 &hdmi->sys_offset); 1495 if (IS_ERR(regmap)) 1496 ret = PTR_ERR(regmap); 1497 if (ret) { 1498 dev_err(dev, 1499 "Failed to get system configuration registers: %d\n", 1500 ret); 1501 return ret; 1502 } 1503 hdmi->sys_regmap = regmap; 1504 1505 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1506 hdmi->regs = devm_ioremap_resource(dev, mem); 1507 if (IS_ERR(hdmi->regs)) 1508 return PTR_ERR(hdmi->regs); 1509 1510 remote = of_graph_get_remote_node(np, 1, 0); 1511 if (!remote) 1512 return -EINVAL; 1513 1514 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1515 hdmi->next_bridge = of_drm_find_bridge(remote); 1516 if (!hdmi->next_bridge) { 1517 dev_err(dev, "Waiting for external bridge\n"); 1518 of_node_put(remote); 1519 return -EPROBE_DEFER; 1520 } 1521 } 1522 1523 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1524 if (!i2c_np) { 1525 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1526 remote); 1527 of_node_put(remote); 1528 return -EINVAL; 1529 } 1530 of_node_put(remote); 1531 1532 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1533 of_node_put(i2c_np); 1534 if (!hdmi->ddc_adpt) { 1535 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1536 return -EINVAL; 1537 } 1538 1539 return 0; 1540 } 1541 1542 /* 1543 * HDMI audio codec callbacks 1544 */ 1545 1546 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1547 struct hdmi_codec_daifmt *daifmt, 1548 struct hdmi_codec_params *params) 1549 { 1550 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1551 struct hdmi_audio_param hdmi_params; 1552 unsigned int chan = params->cea.channels; 1553 1554 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1555 params->sample_rate, params->sample_width, chan); 1556 1557 if (!hdmi->bridge.encoder) 1558 return -ENODEV; 1559 1560 switch (chan) { 1561 case 2: 1562 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1563 break; 1564 case 4: 1565 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1566 break; 1567 case 6: 1568 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1569 break; 1570 case 8: 1571 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1572 break; 1573 default: 1574 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1575 return -EINVAL; 1576 } 1577 1578 switch (params->sample_rate) { 1579 case 32000: 1580 case 44100: 1581 case 48000: 1582 case 88200: 1583 case 96000: 1584 case 176400: 1585 case 192000: 1586 break; 1587 default: 1588 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1589 params->sample_rate); 1590 return -EINVAL; 1591 } 1592 1593 switch (daifmt->fmt) { 1594 case HDMI_I2S: 1595 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1596 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1597 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1598 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1599 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1600 break; 1601 case HDMI_SPDIF: 1602 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1603 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1604 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1605 break; 1606 default: 1607 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1608 daifmt->fmt); 1609 return -EINVAL; 1610 } 1611 1612 memcpy(&hdmi_params.codec_params, params, 1613 sizeof(hdmi_params.codec_params)); 1614 1615 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1616 1617 return 0; 1618 } 1619 1620 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1621 { 1622 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1623 1624 dev_dbg(dev, "%s\n", __func__); 1625 1626 mtk_hdmi_audio_enable(hdmi); 1627 1628 return 0; 1629 } 1630 1631 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1632 { 1633 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1634 1635 dev_dbg(dev, "%s\n", __func__); 1636 1637 mtk_hdmi_audio_disable(hdmi); 1638 } 1639 1640 static int 1641 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) 1642 { 1643 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1644 1645 dev_dbg(dev, "%s(%d)\n", __func__, enable); 1646 1647 if (enable) 1648 mtk_hdmi_hw_aud_mute(hdmi); 1649 else 1650 mtk_hdmi_hw_aud_unmute(hdmi); 1651 1652 return 0; 1653 } 1654 1655 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1656 { 1657 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1658 1659 dev_dbg(dev, "%s\n", __func__); 1660 1661 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); 1662 1663 return 0; 1664 } 1665 1666 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, 1667 hdmi_codec_plugged_cb fn, 1668 struct device *codec_dev) 1669 { 1670 struct mtk_hdmi *hdmi = data; 1671 1672 hdmi->plugged_cb = fn; 1673 hdmi->codec_dev = codec_dev; 1674 mtk_hdmi_update_plugged_status(hdmi); 1675 1676 return 0; 1677 } 1678 1679 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1680 .hw_params = mtk_hdmi_audio_hw_params, 1681 .audio_startup = mtk_hdmi_audio_startup, 1682 .audio_shutdown = mtk_hdmi_audio_shutdown, 1683 .digital_mute = mtk_hdmi_audio_digital_mute, 1684 .get_eld = mtk_hdmi_audio_get_eld, 1685 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, 1686 }; 1687 1688 static int mtk_hdmi_register_audio_driver(struct device *dev) 1689 { 1690 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1691 struct hdmi_codec_pdata codec_data = { 1692 .ops = &mtk_hdmi_audio_codec_ops, 1693 .max_i2s_channels = 2, 1694 .i2s = 1, 1695 .data = hdmi, 1696 }; 1697 struct platform_device *pdev; 1698 1699 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1700 PLATFORM_DEVID_AUTO, &codec_data, 1701 sizeof(codec_data)); 1702 if (IS_ERR(pdev)) 1703 return PTR_ERR(pdev); 1704 1705 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1706 return 0; 1707 } 1708 1709 static int mtk_drm_hdmi_probe(struct platform_device *pdev) 1710 { 1711 struct mtk_hdmi *hdmi; 1712 struct device *dev = &pdev->dev; 1713 int ret; 1714 1715 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1716 if (!hdmi) 1717 return -ENOMEM; 1718 1719 hdmi->dev = dev; 1720 1721 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1722 if (ret) 1723 return ret; 1724 1725 hdmi->phy = devm_phy_get(dev, "hdmi"); 1726 if (IS_ERR(hdmi->phy)) { 1727 ret = PTR_ERR(hdmi->phy); 1728 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); 1729 return ret; 1730 } 1731 1732 platform_set_drvdata(pdev, hdmi); 1733 1734 ret = mtk_hdmi_output_init(hdmi); 1735 if (ret) { 1736 dev_err(dev, "Failed to initialize hdmi output\n"); 1737 return ret; 1738 } 1739 1740 ret = mtk_hdmi_register_audio_driver(dev); 1741 if (ret) { 1742 dev_err(dev, "Failed to register audio driver: %d\n", ret); 1743 return ret; 1744 } 1745 1746 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1747 hdmi->bridge.of_node = pdev->dev.of_node; 1748 drm_bridge_add(&hdmi->bridge); 1749 1750 ret = mtk_hdmi_clk_enable_audio(hdmi); 1751 if (ret) { 1752 dev_err(dev, "Failed to enable audio clocks: %d\n", ret); 1753 goto err_bridge_remove; 1754 } 1755 1756 dev_dbg(dev, "mediatek hdmi probe success\n"); 1757 return 0; 1758 1759 err_bridge_remove: 1760 drm_bridge_remove(&hdmi->bridge); 1761 return ret; 1762 } 1763 1764 static int mtk_drm_hdmi_remove(struct platform_device *pdev) 1765 { 1766 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1767 1768 drm_bridge_remove(&hdmi->bridge); 1769 mtk_hdmi_clk_disable_audio(hdmi); 1770 return 0; 1771 } 1772 1773 #ifdef CONFIG_PM_SLEEP 1774 static int mtk_hdmi_suspend(struct device *dev) 1775 { 1776 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1777 1778 mtk_hdmi_clk_disable_audio(hdmi); 1779 dev_dbg(dev, "hdmi suspend success!\n"); 1780 return 0; 1781 } 1782 1783 static int mtk_hdmi_resume(struct device *dev) 1784 { 1785 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1786 int ret = 0; 1787 1788 ret = mtk_hdmi_clk_enable_audio(hdmi); 1789 if (ret) { 1790 dev_err(dev, "hdmi resume failed!\n"); 1791 return ret; 1792 } 1793 1794 dev_dbg(dev, "hdmi resume success!\n"); 1795 return 0; 1796 } 1797 #endif 1798 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1799 mtk_hdmi_suspend, mtk_hdmi_resume); 1800 1801 static const struct of_device_id mtk_drm_hdmi_of_ids[] = { 1802 { .compatible = "mediatek,mt8173-hdmi", }, 1803 {} 1804 }; 1805 1806 static struct platform_driver mtk_hdmi_driver = { 1807 .probe = mtk_drm_hdmi_probe, 1808 .remove = mtk_drm_hdmi_remove, 1809 .driver = { 1810 .name = "mediatek-drm-hdmi", 1811 .of_match_table = mtk_drm_hdmi_of_ids, 1812 .pm = &mtk_hdmi_pm_ops, 1813 }, 1814 }; 1815 1816 static struct platform_driver * const mtk_hdmi_drivers[] = { 1817 &mtk_hdmi_phy_driver, 1818 &mtk_hdmi_ddc_driver, 1819 &mtk_cec_driver, 1820 &mtk_hdmi_driver, 1821 }; 1822 1823 static int __init mtk_hdmitx_init(void) 1824 { 1825 return platform_register_drivers(mtk_hdmi_drivers, 1826 ARRAY_SIZE(mtk_hdmi_drivers)); 1827 } 1828 1829 static void __exit mtk_hdmitx_exit(void) 1830 { 1831 platform_unregister_drivers(mtk_hdmi_drivers, 1832 ARRAY_SIZE(mtk_hdmi_drivers)); 1833 } 1834 1835 module_init(mtk_hdmitx_init); 1836 module_exit(mtk_hdmitx_exit); 1837 1838 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1839 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1840 MODULE_LICENSE("GPL v2"); 1841