1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Jie Qiu <jie.qiu@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <drm/drmP.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_probe_helper.h> 18 #include <drm/drm_edid.h> 19 #include <linux/arm-smccc.h> 20 #include <linux/clk.h> 21 #include <linux/delay.h> 22 #include <linux/hdmi.h> 23 #include <linux/i2c.h> 24 #include <linux/io.h> 25 #include <linux/kernel.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/of_platform.h> 28 #include <linux/of.h> 29 #include <linux/of_gpio.h> 30 #include <linux/of_graph.h> 31 #include <linux/phy/phy.h> 32 #include <linux/platform_device.h> 33 #include <linux/regmap.h> 34 #include <sound/hdmi-codec.h> 35 #include "mtk_cec.h" 36 #include "mtk_hdmi.h" 37 #include "mtk_hdmi_regs.h" 38 39 #define NCTS_BYTES 7 40 41 enum mtk_hdmi_clk_id { 42 MTK_HDMI_CLK_HDMI_PIXEL, 43 MTK_HDMI_CLK_HDMI_PLL, 44 MTK_HDMI_CLK_AUD_BCLK, 45 MTK_HDMI_CLK_AUD_SPDIF, 46 MTK_HDMI_CLK_COUNT 47 }; 48 49 enum hdmi_aud_input_type { 50 HDMI_AUD_INPUT_I2S = 0, 51 HDMI_AUD_INPUT_SPDIF, 52 }; 53 54 enum hdmi_aud_i2s_fmt { 55 HDMI_I2S_MODE_RJT_24BIT = 0, 56 HDMI_I2S_MODE_RJT_16BIT, 57 HDMI_I2S_MODE_LJT_24BIT, 58 HDMI_I2S_MODE_LJT_16BIT, 59 HDMI_I2S_MODE_I2S_24BIT, 60 HDMI_I2S_MODE_I2S_16BIT 61 }; 62 63 enum hdmi_aud_mclk { 64 HDMI_AUD_MCLK_128FS, 65 HDMI_AUD_MCLK_192FS, 66 HDMI_AUD_MCLK_256FS, 67 HDMI_AUD_MCLK_384FS, 68 HDMI_AUD_MCLK_512FS, 69 HDMI_AUD_MCLK_768FS, 70 HDMI_AUD_MCLK_1152FS, 71 }; 72 73 enum hdmi_aud_channel_type { 74 HDMI_AUD_CHAN_TYPE_1_0 = 0, 75 HDMI_AUD_CHAN_TYPE_1_1, 76 HDMI_AUD_CHAN_TYPE_2_0, 77 HDMI_AUD_CHAN_TYPE_2_1, 78 HDMI_AUD_CHAN_TYPE_3_0, 79 HDMI_AUD_CHAN_TYPE_3_1, 80 HDMI_AUD_CHAN_TYPE_4_0, 81 HDMI_AUD_CHAN_TYPE_4_1, 82 HDMI_AUD_CHAN_TYPE_5_0, 83 HDMI_AUD_CHAN_TYPE_5_1, 84 HDMI_AUD_CHAN_TYPE_6_0, 85 HDMI_AUD_CHAN_TYPE_6_1, 86 HDMI_AUD_CHAN_TYPE_7_0, 87 HDMI_AUD_CHAN_TYPE_7_1, 88 HDMI_AUD_CHAN_TYPE_3_0_LRS, 89 HDMI_AUD_CHAN_TYPE_3_1_LRS, 90 HDMI_AUD_CHAN_TYPE_4_0_CLRS, 91 HDMI_AUD_CHAN_TYPE_4_1_CLRS, 92 HDMI_AUD_CHAN_TYPE_6_1_CS, 93 HDMI_AUD_CHAN_TYPE_6_1_CH, 94 HDMI_AUD_CHAN_TYPE_6_1_OH, 95 HDMI_AUD_CHAN_TYPE_6_1_CHR, 96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH, 97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, 98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC, 99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW, 100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, 101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, 102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, 103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH, 104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH, 105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, 106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH, 107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, 108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, 109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, 110 HDMI_AUD_CHAN_TYPE_6_0_CS, 111 HDMI_AUD_CHAN_TYPE_6_0_CH, 112 HDMI_AUD_CHAN_TYPE_6_0_OH, 113 HDMI_AUD_CHAN_TYPE_6_0_CHR, 114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH, 115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, 116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC, 117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW, 118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, 119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, 120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, 121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH, 122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH, 123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, 124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH, 125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, 126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, 127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, 128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, 129 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF 130 }; 131 132 enum hdmi_aud_channel_swap_type { 133 HDMI_AUD_SWAP_LR, 134 HDMI_AUD_SWAP_LFE_CC, 135 HDMI_AUD_SWAP_LSRS, 136 HDMI_AUD_SWAP_RLS_RRS, 137 HDMI_AUD_SWAP_LR_STATUS, 138 }; 139 140 struct hdmi_audio_param { 141 enum hdmi_audio_coding_type aud_codec; 142 enum hdmi_audio_sample_size aud_sampe_size; 143 enum hdmi_aud_input_type aud_input_type; 144 enum hdmi_aud_i2s_fmt aud_i2s_fmt; 145 enum hdmi_aud_mclk aud_mclk; 146 enum hdmi_aud_channel_type aud_input_chan_type; 147 struct hdmi_codec_params codec_params; 148 }; 149 150 struct mtk_hdmi { 151 struct drm_bridge bridge; 152 struct drm_bridge *next_bridge; 153 struct drm_connector conn; 154 struct device *dev; 155 struct phy *phy; 156 struct device *cec_dev; 157 struct i2c_adapter *ddc_adpt; 158 struct clk *clk[MTK_HDMI_CLK_COUNT]; 159 struct drm_display_mode mode; 160 bool dvi_mode; 161 u32 min_clock; 162 u32 max_clock; 163 u32 max_hdisplay; 164 u32 max_vdisplay; 165 u32 ibias; 166 u32 ibias_up; 167 struct regmap *sys_regmap; 168 unsigned int sys_offset; 169 void __iomem *regs; 170 enum hdmi_colorspace csp; 171 struct hdmi_audio_param aud_param; 172 bool audio_enable; 173 bool powered; 174 bool enabled; 175 }; 176 177 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) 178 { 179 return container_of(b, struct mtk_hdmi, bridge); 180 } 181 182 static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) 183 { 184 return container_of(c, struct mtk_hdmi, conn); 185 } 186 187 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) 188 { 189 return readl(hdmi->regs + offset); 190 } 191 192 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) 193 { 194 writel(val, hdmi->regs + offset); 195 } 196 197 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 198 { 199 void __iomem *reg = hdmi->regs + offset; 200 u32 tmp; 201 202 tmp = readl(reg); 203 tmp &= ~bits; 204 writel(tmp, reg); 205 } 206 207 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) 208 { 209 void __iomem *reg = hdmi->regs + offset; 210 u32 tmp; 211 212 tmp = readl(reg); 213 tmp |= bits; 214 writel(tmp, reg); 215 } 216 217 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) 218 { 219 void __iomem *reg = hdmi->regs + offset; 220 u32 tmp; 221 222 tmp = readl(reg); 223 tmp = (tmp & ~mask) | (val & mask); 224 writel(tmp, reg); 225 } 226 227 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) 228 { 229 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, 230 VIDEO_SOURCE_SEL); 231 } 232 233 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) 234 { 235 struct arm_smccc_res res; 236 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy); 237 238 /* 239 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI 240 * output. This bit can only be controlled in ARM supervisor mode. 241 * The ARM trusted firmware provides an API for the HDMI driver to set 242 * this control bit to enable HDMI output in supervisor mode. 243 */ 244 if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) 245 regmap_update_bits(hdmi->sys_regmap, 246 hdmi->sys_offset + HDMI_SYS_CFG20, 247 0x80008005, enable ? 0x80000005 : 0x8000); 248 else 249 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 250 0x80000000, 0, 0, 0, 0, 0, &res); 251 252 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 253 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); 254 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 255 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); 256 } 257 258 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) 259 { 260 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 261 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); 262 } 263 264 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) 265 { 266 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 267 } 268 269 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) 270 { 271 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); 272 } 273 274 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) 275 { 276 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 277 HDMI_RST, HDMI_RST); 278 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 279 HDMI_RST, 0); 280 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); 281 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, 282 ANLG_ON, ANLG_ON); 283 } 284 285 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) 286 { 287 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, 288 CFG2_NOTICE_EN); 289 } 290 291 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) 292 { 293 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); 294 } 295 296 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) 297 { 298 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); 299 } 300 301 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, 302 u8 len) 303 { 304 u32 ctrl_reg = GRL_CTRL; 305 int i; 306 u8 *frame_data; 307 enum hdmi_infoframe_type frame_type; 308 u8 frame_ver; 309 u8 frame_len; 310 u8 checksum; 311 int ctrl_frame_en = 0; 312 313 frame_type = *buffer; 314 buffer += 1; 315 frame_ver = *buffer; 316 buffer += 1; 317 frame_len = *buffer; 318 buffer += 1; 319 checksum = *buffer; 320 buffer += 1; 321 frame_data = buffer; 322 323 dev_dbg(hdmi->dev, 324 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", 325 frame_type, frame_ver, frame_len, checksum); 326 327 switch (frame_type) { 328 case HDMI_INFOFRAME_TYPE_AVI: 329 ctrl_frame_en = CTRL_AVI_EN; 330 ctrl_reg = GRL_CTRL; 331 break; 332 case HDMI_INFOFRAME_TYPE_SPD: 333 ctrl_frame_en = CTRL_SPD_EN; 334 ctrl_reg = GRL_CTRL; 335 break; 336 case HDMI_INFOFRAME_TYPE_AUDIO: 337 ctrl_frame_en = CTRL_AUDIO_EN; 338 ctrl_reg = GRL_CTRL; 339 break; 340 case HDMI_INFOFRAME_TYPE_VENDOR: 341 ctrl_frame_en = VS_EN; 342 ctrl_reg = GRL_ACP_ISRC_CTRL; 343 break; 344 default: 345 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); 346 return; 347 } 348 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 349 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); 350 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); 351 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); 352 353 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); 354 for (i = 0; i < frame_len; i++) 355 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); 356 357 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); 358 } 359 360 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) 361 { 362 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, 363 AUDIO_PACKET_OFF); 364 } 365 366 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) 367 { 368 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 369 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); 370 usleep_range(2000, 4000); 371 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 372 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); 373 } 374 375 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) 376 { 377 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, 378 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, 379 COLOR_8BIT_MODE); 380 } 381 382 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) 383 { 384 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 385 usleep_range(2000, 4000); 386 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); 387 } 388 389 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) 390 { 391 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, 392 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 393 usleep_range(2000, 4000); 394 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, 395 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); 396 } 397 398 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) 399 { 400 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, 401 CTS_CTRL_SOFT); 402 } 403 404 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, 405 bool enable) 406 { 407 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, 408 NCTS_WRI_ANYTIME); 409 } 410 411 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, 412 struct drm_display_mode *mode) 413 { 414 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); 415 416 if (mode->flags & DRM_MODE_FLAG_INTERLACE && 417 mode->clock == 74250 && 418 mode->vdisplay == 1080) 419 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 420 else 421 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); 422 } 423 424 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, 425 enum hdmi_aud_channel_swap_type swap) 426 { 427 u8 swap_bit; 428 429 switch (swap) { 430 case HDMI_AUD_SWAP_LR: 431 swap_bit = LR_SWAP; 432 break; 433 case HDMI_AUD_SWAP_LFE_CC: 434 swap_bit = LFE_CC_SWAP; 435 break; 436 case HDMI_AUD_SWAP_LSRS: 437 swap_bit = LSRS_SWAP; 438 break; 439 case HDMI_AUD_SWAP_RLS_RRS: 440 swap_bit = RLS_RRS_SWAP; 441 break; 442 case HDMI_AUD_SWAP_LR_STATUS: 443 swap_bit = LR_STATUS_SWAP; 444 break; 445 default: 446 swap_bit = LFE_CC_SWAP; 447 break; 448 } 449 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); 450 } 451 452 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, 453 enum hdmi_audio_sample_size bit_num) 454 { 455 u32 val; 456 457 switch (bit_num) { 458 case HDMI_AUDIO_SAMPLE_SIZE_16: 459 val = AOUT_16BIT; 460 break; 461 case HDMI_AUDIO_SAMPLE_SIZE_20: 462 val = AOUT_20BIT; 463 break; 464 case HDMI_AUDIO_SAMPLE_SIZE_24: 465 case HDMI_AUDIO_SAMPLE_SIZE_STREAM: 466 val = AOUT_24BIT; 467 break; 468 } 469 470 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); 471 } 472 473 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, 474 enum hdmi_aud_i2s_fmt i2s_fmt) 475 { 476 u32 val; 477 478 val = mtk_hdmi_read(hdmi, GRL_CFG0); 479 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); 480 481 switch (i2s_fmt) { 482 case HDMI_I2S_MODE_RJT_24BIT: 483 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; 484 break; 485 case HDMI_I2S_MODE_RJT_16BIT: 486 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; 487 break; 488 case HDMI_I2S_MODE_LJT_24BIT: 489 default: 490 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; 491 break; 492 case HDMI_I2S_MODE_LJT_16BIT: 493 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; 494 break; 495 case HDMI_I2S_MODE_I2S_24BIT: 496 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; 497 break; 498 case HDMI_I2S_MODE_I2S_16BIT: 499 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; 500 break; 501 } 502 mtk_hdmi_write(hdmi, GRL_CFG0, val); 503 } 504 505 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) 506 { 507 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; 508 u8 val; 509 510 /* Disable high bitrate, set DST packet normal/double */ 511 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); 512 513 if (dst) 514 val = DST_NORMAL_DOUBLE | SACD_DST; 515 else 516 val = 0; 517 518 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); 519 } 520 521 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, 522 enum hdmi_aud_channel_type channel_type, 523 u8 channel_count) 524 { 525 unsigned int ch_switch; 526 u8 i2s_uv; 527 528 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | 529 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | 530 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | 531 CH_SWITCH(2, 1) | CH_SWITCH(0, 0); 532 533 if (channel_count == 2) { 534 i2s_uv = I2S_UV_CH_EN(0); 535 } else if (channel_count == 3 || channel_count == 4) { 536 if (channel_count == 4 && 537 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || 538 channel_type == HDMI_AUD_CHAN_TYPE_4_0)) 539 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); 540 else 541 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); 542 } else if (channel_count == 6 || channel_count == 5) { 543 if (channel_count == 6 && 544 channel_type != HDMI_AUD_CHAN_TYPE_5_1 && 545 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { 546 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 547 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 548 } else { 549 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | 550 I2S_UV_CH_EN(0); 551 } 552 } else if (channel_count == 8 || channel_count == 7) { 553 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | 554 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); 555 } else { 556 i2s_uv = I2S_UV_CH_EN(0); 557 } 558 559 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); 560 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); 561 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); 562 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); 563 } 564 565 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, 566 enum hdmi_aud_input_type input_type) 567 { 568 u32 val; 569 570 val = mtk_hdmi_read(hdmi, GRL_CFG1); 571 if (input_type == HDMI_AUD_INPUT_I2S && 572 (val & CFG1_SPDIF) == CFG1_SPDIF) { 573 val &= ~CFG1_SPDIF; 574 } else if (input_type == HDMI_AUD_INPUT_SPDIF && 575 (val & CFG1_SPDIF) == 0) { 576 val |= CFG1_SPDIF; 577 } 578 mtk_hdmi_write(hdmi, GRL_CFG1, val); 579 } 580 581 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, 582 u8 *channel_status) 583 { 584 int i; 585 586 for (i = 0; i < 5; i++) { 587 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); 588 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); 589 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); 590 } 591 for (; i < 24; i++) { 592 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); 593 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); 594 } 595 } 596 597 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) 598 { 599 u32 val; 600 601 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 602 if (val & MIX_CTRL_SRC_EN) { 603 val &= ~MIX_CTRL_SRC_EN; 604 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 605 usleep_range(255, 512); 606 val |= MIX_CTRL_SRC_EN; 607 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 608 } 609 } 610 611 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) 612 { 613 u32 val; 614 615 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); 616 val &= ~MIX_CTRL_SRC_EN; 617 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); 618 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); 619 } 620 621 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, 622 enum hdmi_aud_mclk mclk) 623 { 624 u32 val; 625 626 val = mtk_hdmi_read(hdmi, GRL_CFG5); 627 val &= CFG5_CD_RATIO_MASK; 628 629 switch (mclk) { 630 case HDMI_AUD_MCLK_128FS: 631 val |= CFG5_FS128; 632 break; 633 case HDMI_AUD_MCLK_256FS: 634 val |= CFG5_FS256; 635 break; 636 case HDMI_AUD_MCLK_384FS: 637 val |= CFG5_FS384; 638 break; 639 case HDMI_AUD_MCLK_512FS: 640 val |= CFG5_FS512; 641 break; 642 case HDMI_AUD_MCLK_768FS: 643 val |= CFG5_FS768; 644 break; 645 default: 646 val |= CFG5_FS256; 647 break; 648 } 649 mtk_hdmi_write(hdmi, GRL_CFG5, val); 650 } 651 652 struct hdmi_acr_n { 653 unsigned int clock; 654 unsigned int n[3]; 655 }; 656 657 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ 658 static const struct hdmi_acr_n hdmi_rec_n_table[] = { 659 /* Clock, N: 32kHz 44.1kHz 48kHz */ 660 { 25175, { 4576, 7007, 6864 } }, 661 { 74176, { 11648, 17836, 11648 } }, 662 { 148352, { 11648, 8918, 5824 } }, 663 { 296703, { 5824, 4459, 5824 } }, 664 { 297000, { 3072, 4704, 5120 } }, 665 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ 666 }; 667 668 /** 669 * hdmi_recommended_n() - Return N value recommended by HDMI specification 670 * @freq: audio sample rate in Hz 671 * @clock: rounded TMDS clock in kHz 672 */ 673 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) 674 { 675 const struct hdmi_acr_n *recommended; 676 unsigned int i; 677 678 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { 679 if (clock == hdmi_rec_n_table[i].clock) 680 break; 681 } 682 recommended = hdmi_rec_n_table + i; 683 684 switch (freq) { 685 case 32000: 686 return recommended->n[0]; 687 case 44100: 688 return recommended->n[1]; 689 case 48000: 690 return recommended->n[2]; 691 case 88200: 692 return recommended->n[1] * 2; 693 case 96000: 694 return recommended->n[2] * 2; 695 case 176400: 696 return recommended->n[1] * 4; 697 case 192000: 698 return recommended->n[2] * 4; 699 default: 700 return (128 * freq) / 1000; 701 } 702 } 703 704 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) 705 { 706 switch (clock) { 707 case 25175: 708 return 25174825; /* 25.2/1.001 MHz */ 709 case 74176: 710 return 74175824; /* 74.25/1.001 MHz */ 711 case 148352: 712 return 148351648; /* 148.5/1.001 MHz */ 713 case 296703: 714 return 296703297; /* 297/1.001 MHz */ 715 default: 716 return clock * 1000; 717 } 718 } 719 720 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, 721 unsigned int tmds_clock, unsigned int n) 722 { 723 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, 724 128 * audio_sample_rate); 725 } 726 727 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, 728 unsigned int cts) 729 { 730 unsigned char val[NCTS_BYTES]; 731 int i; 732 733 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 734 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 735 mtk_hdmi_write(hdmi, GRL_NCTS, 0); 736 memset(val, 0, sizeof(val)); 737 738 val[0] = (cts >> 24) & 0xff; 739 val[1] = (cts >> 16) & 0xff; 740 val[2] = (cts >> 8) & 0xff; 741 val[3] = cts & 0xff; 742 743 val[4] = (n >> 16) & 0xff; 744 val[5] = (n >> 8) & 0xff; 745 val[6] = n & 0xff; 746 747 for (i = 0; i < NCTS_BYTES; i++) 748 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); 749 } 750 751 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, 752 unsigned int sample_rate, 753 unsigned int clock) 754 { 755 unsigned int n, cts; 756 757 n = hdmi_recommended_n(sample_rate, clock); 758 cts = hdmi_expected_cts(sample_rate, clock, n); 759 760 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", 761 __func__, sample_rate, clock, n, cts); 762 763 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, 764 AUDIO_I2S_NCTS_SEL); 765 do_hdmi_hw_aud_set_ncts(hdmi, n, cts); 766 } 767 768 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) 769 { 770 switch (channel_type) { 771 case HDMI_AUD_CHAN_TYPE_1_0: 772 case HDMI_AUD_CHAN_TYPE_1_1: 773 case HDMI_AUD_CHAN_TYPE_2_0: 774 return 2; 775 case HDMI_AUD_CHAN_TYPE_2_1: 776 case HDMI_AUD_CHAN_TYPE_3_0: 777 return 3; 778 case HDMI_AUD_CHAN_TYPE_3_1: 779 case HDMI_AUD_CHAN_TYPE_4_0: 780 case HDMI_AUD_CHAN_TYPE_3_0_LRS: 781 return 4; 782 case HDMI_AUD_CHAN_TYPE_4_1: 783 case HDMI_AUD_CHAN_TYPE_5_0: 784 case HDMI_AUD_CHAN_TYPE_3_1_LRS: 785 case HDMI_AUD_CHAN_TYPE_4_0_CLRS: 786 return 5; 787 case HDMI_AUD_CHAN_TYPE_5_1: 788 case HDMI_AUD_CHAN_TYPE_6_0: 789 case HDMI_AUD_CHAN_TYPE_4_1_CLRS: 790 case HDMI_AUD_CHAN_TYPE_6_0_CS: 791 case HDMI_AUD_CHAN_TYPE_6_0_CH: 792 case HDMI_AUD_CHAN_TYPE_6_0_OH: 793 case HDMI_AUD_CHAN_TYPE_6_0_CHR: 794 return 6; 795 case HDMI_AUD_CHAN_TYPE_6_1: 796 case HDMI_AUD_CHAN_TYPE_6_1_CS: 797 case HDMI_AUD_CHAN_TYPE_6_1_CH: 798 case HDMI_AUD_CHAN_TYPE_6_1_OH: 799 case HDMI_AUD_CHAN_TYPE_6_1_CHR: 800 case HDMI_AUD_CHAN_TYPE_7_0: 801 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: 802 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: 803 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: 804 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: 805 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: 806 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: 807 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: 808 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: 809 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: 810 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: 811 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: 812 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: 813 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: 814 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: 815 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: 816 return 7; 817 case HDMI_AUD_CHAN_TYPE_7_1: 818 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: 819 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: 820 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: 821 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: 822 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: 823 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: 824 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: 825 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: 826 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: 827 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: 828 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: 829 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: 830 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: 831 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: 832 return 8; 833 default: 834 return 2; 835 } 836 } 837 838 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) 839 { 840 unsigned long rate; 841 int ret; 842 843 /* The DPI driver already should have set TVDPLL to the correct rate */ 844 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); 845 if (ret) { 846 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, 847 ret); 848 return ret; 849 } 850 851 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 852 853 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) 854 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, 855 rate); 856 else 857 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); 858 859 mtk_hdmi_hw_config_sys(hdmi); 860 mtk_hdmi_hw_set_deep_color_mode(hdmi); 861 return 0; 862 } 863 864 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, 865 struct drm_display_mode *mode) 866 { 867 mtk_hdmi_hw_reset(hdmi); 868 mtk_hdmi_hw_enable_notice(hdmi, true); 869 mtk_hdmi_hw_write_int_mask(hdmi, 0xff); 870 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); 871 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); 872 873 mtk_hdmi_hw_msic_setting(hdmi, mode); 874 } 875 876 static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable) 877 { 878 mtk_hdmi_hw_send_aud_packet(hdmi, enable); 879 return 0; 880 } 881 882 static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on) 883 { 884 mtk_hdmi_hw_ncts_enable(hdmi, on); 885 return 0; 886 } 887 888 static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) 889 { 890 enum hdmi_aud_channel_type chan_type; 891 u8 chan_count; 892 bool dst; 893 894 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); 895 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); 896 897 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && 898 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { 899 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 900 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { 901 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; 902 } 903 904 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); 905 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); 906 907 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && 908 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); 909 mtk_hdmi_hw_audio_config(hdmi, dst); 910 911 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) 912 chan_type = HDMI_AUD_CHAN_TYPE_2_0; 913 else 914 chan_type = hdmi->aud_param.aud_input_chan_type; 915 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); 916 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); 917 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); 918 919 return 0; 920 } 921 922 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, 923 struct drm_display_mode *display_mode) 924 { 925 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; 926 927 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false); 928 mtk_hdmi_hw_aud_src_disable(hdmi); 929 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); 930 931 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { 932 switch (sample_rate) { 933 case 32000: 934 case 44100: 935 case 48000: 936 case 88200: 937 case 96000: 938 break; 939 default: 940 return -EINVAL; 941 } 942 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); 943 } else { 944 switch (sample_rate) { 945 case 32000: 946 case 44100: 947 case 48000: 948 break; 949 default: 950 return -EINVAL; 951 } 952 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); 953 } 954 955 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); 956 957 mtk_hdmi_hw_aud_src_reenable(hdmi); 958 return 0; 959 } 960 961 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, 962 struct drm_display_mode *display_mode) 963 { 964 mtk_hdmi_hw_aud_mute(hdmi); 965 mtk_hdmi_aud_enable_packet(hdmi, false); 966 967 mtk_hdmi_aud_set_input(hdmi); 968 mtk_hdmi_aud_set_src(hdmi, display_mode); 969 mtk_hdmi_hw_aud_set_channel_status(hdmi, 970 hdmi->aud_param.codec_params.iec.status); 971 972 usleep_range(50, 100); 973 974 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true); 975 mtk_hdmi_aud_enable_packet(hdmi, true); 976 mtk_hdmi_hw_aud_unmute(hdmi); 977 return 0; 978 } 979 980 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, 981 struct drm_display_mode *mode) 982 { 983 struct hdmi_avi_infoframe frame; 984 u8 buffer[17]; 985 ssize_t err; 986 987 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 988 &hdmi->conn, mode); 989 if (err < 0) { 990 dev_err(hdmi->dev, 991 "Failed to get AVI infoframe from mode: %zd\n", err); 992 return err; 993 } 994 995 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 996 if (err < 0) { 997 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); 998 return err; 999 } 1000 1001 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1002 return 0; 1003 } 1004 1005 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, 1006 const char *vendor, 1007 const char *product) 1008 { 1009 struct hdmi_spd_infoframe frame; 1010 u8 buffer[29]; 1011 ssize_t err; 1012 1013 err = hdmi_spd_infoframe_init(&frame, vendor, product); 1014 if (err < 0) { 1015 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", 1016 err); 1017 return err; 1018 } 1019 1020 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); 1021 if (err < 0) { 1022 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); 1023 return err; 1024 } 1025 1026 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1027 return 0; 1028 } 1029 1030 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) 1031 { 1032 struct hdmi_audio_infoframe frame; 1033 u8 buffer[14]; 1034 ssize_t err; 1035 1036 err = hdmi_audio_infoframe_init(&frame); 1037 if (err < 0) { 1038 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", 1039 err); 1040 return err; 1041 } 1042 1043 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 1044 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 1045 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 1046 frame.channels = mtk_hdmi_aud_get_chnl_count( 1047 hdmi->aud_param.aud_input_chan_type); 1048 1049 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 1050 if (err < 0) { 1051 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", 1052 err); 1053 return err; 1054 } 1055 1056 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1057 return 0; 1058 } 1059 1060 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, 1061 struct drm_display_mode *mode) 1062 { 1063 struct hdmi_vendor_infoframe frame; 1064 u8 buffer[10]; 1065 ssize_t err; 1066 1067 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1068 &hdmi->conn, mode); 1069 if (err) { 1070 dev_err(hdmi->dev, 1071 "Failed to get vendor infoframe from mode: %zd\n", err); 1072 return err; 1073 } 1074 1075 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1076 if (err < 0) { 1077 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1078 err); 1079 return err; 1080 } 1081 1082 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); 1083 return 0; 1084 } 1085 1086 static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) 1087 { 1088 struct hdmi_audio_param *aud_param = &hdmi->aud_param; 1089 1090 hdmi->csp = HDMI_COLORSPACE_RGB; 1091 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1092 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1093 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; 1094 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1095 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; 1096 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1097 1098 return 0; 1099 } 1100 1101 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) 1102 { 1103 mtk_hdmi_aud_enable_packet(hdmi, true); 1104 hdmi->audio_enable = true; 1105 } 1106 1107 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) 1108 { 1109 mtk_hdmi_aud_enable_packet(hdmi, false); 1110 hdmi->audio_enable = false; 1111 } 1112 1113 static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, 1114 struct hdmi_audio_param *param) 1115 { 1116 if (!hdmi->audio_enable) { 1117 dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); 1118 return -EINVAL; 1119 } 1120 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", 1121 param->aud_codec, param->aud_input_type, 1122 param->aud_input_chan_type, param->codec_params.sample_rate); 1123 memcpy(&hdmi->aud_param, param, sizeof(*param)); 1124 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); 1125 } 1126 1127 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, 1128 struct drm_display_mode *mode) 1129 { 1130 int ret; 1131 1132 mtk_hdmi_hw_vid_black(hdmi, true); 1133 mtk_hdmi_hw_aud_mute(hdmi); 1134 mtk_hdmi_hw_send_av_mute(hdmi); 1135 phy_power_off(hdmi->phy); 1136 1137 ret = mtk_hdmi_video_change_vpll(hdmi, 1138 mode->clock * 1000); 1139 if (ret) { 1140 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); 1141 return ret; 1142 } 1143 mtk_hdmi_video_set_display_mode(hdmi, mode); 1144 1145 phy_power_on(hdmi->phy); 1146 mtk_hdmi_aud_output_config(hdmi, mode); 1147 1148 mtk_hdmi_hw_vid_black(hdmi, false); 1149 mtk_hdmi_hw_aud_unmute(hdmi); 1150 mtk_hdmi_hw_send_av_unmute(hdmi); 1151 1152 return 0; 1153 } 1154 1155 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { 1156 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", 1157 [MTK_HDMI_CLK_HDMI_PLL] = "pll", 1158 [MTK_HDMI_CLK_AUD_BCLK] = "bclk", 1159 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", 1160 }; 1161 1162 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, 1163 struct device_node *np) 1164 { 1165 int i; 1166 1167 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { 1168 hdmi->clk[i] = of_clk_get_by_name(np, 1169 mtk_hdmi_clk_names[i]); 1170 if (IS_ERR(hdmi->clk[i])) 1171 return PTR_ERR(hdmi->clk[i]); 1172 } 1173 return 0; 1174 } 1175 1176 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) 1177 { 1178 int ret; 1179 1180 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1181 if (ret) 1182 return ret; 1183 1184 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1185 if (ret) 1186 goto err; 1187 1188 return 0; 1189 err: 1190 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1191 return ret; 1192 } 1193 1194 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) 1195 { 1196 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); 1197 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); 1198 } 1199 1200 static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, 1201 bool force) 1202 { 1203 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1204 1205 return mtk_cec_hpd_high(hdmi->cec_dev) ? 1206 connector_status_connected : connector_status_disconnected; 1207 } 1208 1209 static void hdmi_conn_destroy(struct drm_connector *conn) 1210 { 1211 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1212 1213 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); 1214 1215 drm_connector_cleanup(conn); 1216 } 1217 1218 static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) 1219 { 1220 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1221 struct edid *edid; 1222 int ret; 1223 1224 if (!hdmi->ddc_adpt) 1225 return -ENODEV; 1226 1227 edid = drm_get_edid(conn, hdmi->ddc_adpt); 1228 if (!edid) 1229 return -ENODEV; 1230 1231 hdmi->dvi_mode = !drm_detect_monitor_audio(edid); 1232 1233 drm_connector_update_edid_property(conn, edid); 1234 1235 ret = drm_add_edid_modes(conn, edid); 1236 kfree(edid); 1237 return ret; 1238 } 1239 1240 static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, 1241 struct drm_display_mode *mode) 1242 { 1243 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1244 1245 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 1246 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1247 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); 1248 1249 if (hdmi->bridge.next) { 1250 struct drm_display_mode adjusted_mode; 1251 1252 drm_mode_copy(&adjusted_mode, mode); 1253 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode, 1254 &adjusted_mode)) 1255 return MODE_BAD; 1256 } 1257 1258 if (mode->clock < 27000) 1259 return MODE_CLOCK_LOW; 1260 if (mode->clock > 297000) 1261 return MODE_CLOCK_HIGH; 1262 1263 return drm_mode_validate_size(mode, 0x1fff, 0x1fff); 1264 } 1265 1266 static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) 1267 { 1268 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); 1269 1270 return hdmi->bridge.encoder; 1271 } 1272 1273 static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { 1274 .detect = hdmi_conn_detect, 1275 .fill_modes = drm_helper_probe_single_connector_modes, 1276 .destroy = hdmi_conn_destroy, 1277 .reset = drm_atomic_helper_connector_reset, 1278 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1279 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1280 }; 1281 1282 static const struct drm_connector_helper_funcs 1283 mtk_hdmi_connector_helper_funcs = { 1284 .get_modes = mtk_hdmi_conn_get_modes, 1285 .mode_valid = mtk_hdmi_conn_mode_valid, 1286 .best_encoder = mtk_hdmi_conn_best_enc, 1287 }; 1288 1289 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) 1290 { 1291 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1292 1293 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) 1294 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); 1295 } 1296 1297 /* 1298 * Bridge callbacks 1299 */ 1300 1301 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge) 1302 { 1303 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1304 int ret; 1305 1306 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn, 1307 &mtk_hdmi_connector_funcs, 1308 DRM_MODE_CONNECTOR_HDMIA); 1309 if (ret) { 1310 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); 1311 return ret; 1312 } 1313 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); 1314 1315 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; 1316 hdmi->conn.interlace_allowed = true; 1317 hdmi->conn.doublescan_allowed = false; 1318 1319 ret = drm_connector_attach_encoder(&hdmi->conn, 1320 bridge->encoder); 1321 if (ret) { 1322 dev_err(hdmi->dev, 1323 "Failed to attach connector to encoder: %d\n", ret); 1324 return ret; 1325 } 1326 1327 if (hdmi->next_bridge) { 1328 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 1329 bridge); 1330 if (ret) { 1331 dev_err(hdmi->dev, 1332 "Failed to attach external bridge: %d\n", ret); 1333 return ret; 1334 } 1335 } 1336 1337 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); 1338 1339 return 0; 1340 } 1341 1342 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1343 const struct drm_display_mode *mode, 1344 struct drm_display_mode *adjusted_mode) 1345 { 1346 return true; 1347 } 1348 1349 static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) 1350 { 1351 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1352 1353 if (!hdmi->enabled) 1354 return; 1355 1356 phy_power_off(hdmi->phy); 1357 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1358 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1359 1360 hdmi->enabled = false; 1361 } 1362 1363 static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) 1364 { 1365 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1366 1367 if (!hdmi->powered) 1368 return; 1369 1370 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1371 mtk_hdmi_hw_make_reg_writable(hdmi, false); 1372 1373 hdmi->powered = false; 1374 } 1375 1376 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1377 const struct drm_display_mode *mode, 1378 const struct drm_display_mode *adjusted_mode) 1379 { 1380 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1381 1382 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", 1383 adjusted_mode->name, adjusted_mode->hdisplay); 1384 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", 1385 adjusted_mode->hsync_start, adjusted_mode->hsync_end, 1386 adjusted_mode->htotal); 1387 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", 1388 adjusted_mode->hskew, adjusted_mode->vdisplay); 1389 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", 1390 adjusted_mode->vsync_start, adjusted_mode->vsync_end, 1391 adjusted_mode->vtotal); 1392 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", 1393 adjusted_mode->vscan, adjusted_mode->flags); 1394 1395 drm_mode_copy(&hdmi->mode, adjusted_mode); 1396 } 1397 1398 static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) 1399 { 1400 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1401 1402 mtk_hdmi_hw_make_reg_writable(hdmi, true); 1403 mtk_hdmi_hw_1p4_version_enable(hdmi, true); 1404 1405 hdmi->powered = true; 1406 } 1407 1408 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, 1409 struct drm_display_mode *mode) 1410 { 1411 mtk_hdmi_setup_audio_infoframe(hdmi); 1412 mtk_hdmi_setup_avi_infoframe(hdmi, mode); 1413 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); 1414 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 1415 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); 1416 } 1417 1418 static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) 1419 { 1420 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); 1421 1422 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); 1423 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); 1424 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); 1425 phy_power_on(hdmi->phy); 1426 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); 1427 1428 hdmi->enabled = true; 1429 } 1430 1431 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { 1432 .attach = mtk_hdmi_bridge_attach, 1433 .mode_fixup = mtk_hdmi_bridge_mode_fixup, 1434 .disable = mtk_hdmi_bridge_disable, 1435 .post_disable = mtk_hdmi_bridge_post_disable, 1436 .mode_set = mtk_hdmi_bridge_mode_set, 1437 .pre_enable = mtk_hdmi_bridge_pre_enable, 1438 .enable = mtk_hdmi_bridge_enable, 1439 }; 1440 1441 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, 1442 struct platform_device *pdev) 1443 { 1444 struct device *dev = &pdev->dev; 1445 struct device_node *np = dev->of_node; 1446 struct device_node *cec_np, *remote, *i2c_np; 1447 struct platform_device *cec_pdev; 1448 struct regmap *regmap; 1449 struct resource *mem; 1450 int ret; 1451 1452 ret = mtk_hdmi_get_all_clk(hdmi, np); 1453 if (ret) { 1454 dev_err(dev, "Failed to get clocks: %d\n", ret); 1455 return ret; 1456 } 1457 1458 /* The CEC module handles HDMI hotplug detection */ 1459 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); 1460 if (!cec_np) { 1461 dev_err(dev, "Failed to find CEC node\n"); 1462 return -EINVAL; 1463 } 1464 1465 cec_pdev = of_find_device_by_node(cec_np); 1466 if (!cec_pdev) { 1467 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", 1468 cec_np); 1469 of_node_put(cec_np); 1470 return -EPROBE_DEFER; 1471 } 1472 of_node_put(cec_np); 1473 hdmi->cec_dev = &cec_pdev->dev; 1474 1475 /* 1476 * The mediatek,syscon-hdmi property contains a phandle link to the 1477 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG 1478 * registers it contains. 1479 */ 1480 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); 1481 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, 1482 &hdmi->sys_offset); 1483 if (IS_ERR(regmap)) 1484 ret = PTR_ERR(regmap); 1485 if (ret) { 1486 dev_err(dev, 1487 "Failed to get system configuration registers: %d\n", 1488 ret); 1489 return ret; 1490 } 1491 hdmi->sys_regmap = regmap; 1492 1493 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1494 hdmi->regs = devm_ioremap_resource(dev, mem); 1495 if (IS_ERR(hdmi->regs)) 1496 return PTR_ERR(hdmi->regs); 1497 1498 remote = of_graph_get_remote_node(np, 1, 0); 1499 if (!remote) 1500 return -EINVAL; 1501 1502 if (!of_device_is_compatible(remote, "hdmi-connector")) { 1503 hdmi->next_bridge = of_drm_find_bridge(remote); 1504 if (!hdmi->next_bridge) { 1505 dev_err(dev, "Waiting for external bridge\n"); 1506 of_node_put(remote); 1507 return -EPROBE_DEFER; 1508 } 1509 } 1510 1511 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); 1512 if (!i2c_np) { 1513 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", 1514 remote); 1515 of_node_put(remote); 1516 return -EINVAL; 1517 } 1518 of_node_put(remote); 1519 1520 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); 1521 of_node_put(i2c_np); 1522 if (!hdmi->ddc_adpt) { 1523 dev_err(dev, "Failed to get ddc i2c adapter by node\n"); 1524 return -EINVAL; 1525 } 1526 1527 return 0; 1528 } 1529 1530 /* 1531 * HDMI audio codec callbacks 1532 */ 1533 1534 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, 1535 struct hdmi_codec_daifmt *daifmt, 1536 struct hdmi_codec_params *params) 1537 { 1538 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1539 struct hdmi_audio_param hdmi_params; 1540 unsigned int chan = params->cea.channels; 1541 1542 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1543 params->sample_rate, params->sample_width, chan); 1544 1545 if (!hdmi->bridge.encoder) 1546 return -ENODEV; 1547 1548 switch (chan) { 1549 case 2: 1550 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; 1551 break; 1552 case 4: 1553 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; 1554 break; 1555 case 6: 1556 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; 1557 break; 1558 case 8: 1559 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; 1560 break; 1561 default: 1562 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); 1563 return -EINVAL; 1564 } 1565 1566 switch (params->sample_rate) { 1567 case 32000: 1568 case 44100: 1569 case 48000: 1570 case 88200: 1571 case 96000: 1572 case 176400: 1573 case 192000: 1574 break; 1575 default: 1576 dev_err(hdmi->dev, "rate[%d] not supported!\n", 1577 params->sample_rate); 1578 return -EINVAL; 1579 } 1580 1581 switch (daifmt->fmt) { 1582 case HDMI_I2S: 1583 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1584 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1585 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; 1586 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; 1587 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; 1588 break; 1589 case HDMI_SPDIF: 1590 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; 1591 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; 1592 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; 1593 break; 1594 default: 1595 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, 1596 daifmt->fmt); 1597 return -EINVAL; 1598 } 1599 1600 memcpy(&hdmi_params.codec_params, params, 1601 sizeof(hdmi_params.codec_params)); 1602 1603 mtk_hdmi_audio_set_param(hdmi, &hdmi_params); 1604 1605 return 0; 1606 } 1607 1608 static int mtk_hdmi_audio_startup(struct device *dev, void *data) 1609 { 1610 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1611 1612 dev_dbg(dev, "%s\n", __func__); 1613 1614 mtk_hdmi_audio_enable(hdmi); 1615 1616 return 0; 1617 } 1618 1619 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) 1620 { 1621 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1622 1623 dev_dbg(dev, "%s\n", __func__); 1624 1625 mtk_hdmi_audio_disable(hdmi); 1626 } 1627 1628 static int 1629 mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) 1630 { 1631 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1632 1633 dev_dbg(dev, "%s(%d)\n", __func__, enable); 1634 1635 if (enable) 1636 mtk_hdmi_hw_aud_mute(hdmi); 1637 else 1638 mtk_hdmi_hw_aud_unmute(hdmi); 1639 1640 return 0; 1641 } 1642 1643 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1644 { 1645 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1646 1647 dev_dbg(dev, "%s\n", __func__); 1648 1649 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); 1650 1651 return 0; 1652 } 1653 1654 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { 1655 .hw_params = mtk_hdmi_audio_hw_params, 1656 .audio_startup = mtk_hdmi_audio_startup, 1657 .audio_shutdown = mtk_hdmi_audio_shutdown, 1658 .digital_mute = mtk_hdmi_audio_digital_mute, 1659 .get_eld = mtk_hdmi_audio_get_eld, 1660 }; 1661 1662 static void mtk_hdmi_register_audio_driver(struct device *dev) 1663 { 1664 struct hdmi_codec_pdata codec_data = { 1665 .ops = &mtk_hdmi_audio_codec_ops, 1666 .max_i2s_channels = 2, 1667 .i2s = 1, 1668 }; 1669 struct platform_device *pdev; 1670 1671 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1672 PLATFORM_DEVID_AUTO, &codec_data, 1673 sizeof(codec_data)); 1674 if (IS_ERR(pdev)) 1675 return; 1676 1677 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); 1678 } 1679 1680 static int mtk_drm_hdmi_probe(struct platform_device *pdev) 1681 { 1682 struct mtk_hdmi *hdmi; 1683 struct device *dev = &pdev->dev; 1684 int ret; 1685 1686 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1687 if (!hdmi) 1688 return -ENOMEM; 1689 1690 hdmi->dev = dev; 1691 1692 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); 1693 if (ret) 1694 return ret; 1695 1696 hdmi->phy = devm_phy_get(dev, "hdmi"); 1697 if (IS_ERR(hdmi->phy)) { 1698 ret = PTR_ERR(hdmi->phy); 1699 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); 1700 return ret; 1701 } 1702 1703 platform_set_drvdata(pdev, hdmi); 1704 1705 ret = mtk_hdmi_output_init(hdmi); 1706 if (ret) { 1707 dev_err(dev, "Failed to initialize hdmi output\n"); 1708 return ret; 1709 } 1710 1711 mtk_hdmi_register_audio_driver(dev); 1712 1713 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; 1714 hdmi->bridge.of_node = pdev->dev.of_node; 1715 drm_bridge_add(&hdmi->bridge); 1716 1717 ret = mtk_hdmi_clk_enable_audio(hdmi); 1718 if (ret) { 1719 dev_err(dev, "Failed to enable audio clocks: %d\n", ret); 1720 goto err_bridge_remove; 1721 } 1722 1723 dev_dbg(dev, "mediatek hdmi probe success\n"); 1724 return 0; 1725 1726 err_bridge_remove: 1727 drm_bridge_remove(&hdmi->bridge); 1728 return ret; 1729 } 1730 1731 static int mtk_drm_hdmi_remove(struct platform_device *pdev) 1732 { 1733 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); 1734 1735 drm_bridge_remove(&hdmi->bridge); 1736 mtk_hdmi_clk_disable_audio(hdmi); 1737 return 0; 1738 } 1739 1740 #ifdef CONFIG_PM_SLEEP 1741 static int mtk_hdmi_suspend(struct device *dev) 1742 { 1743 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1744 1745 mtk_hdmi_clk_disable_audio(hdmi); 1746 dev_dbg(dev, "hdmi suspend success!\n"); 1747 return 0; 1748 } 1749 1750 static int mtk_hdmi_resume(struct device *dev) 1751 { 1752 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); 1753 int ret = 0; 1754 1755 ret = mtk_hdmi_clk_enable_audio(hdmi); 1756 if (ret) { 1757 dev_err(dev, "hdmi resume failed!\n"); 1758 return ret; 1759 } 1760 1761 dev_dbg(dev, "hdmi resume success!\n"); 1762 return 0; 1763 } 1764 #endif 1765 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, 1766 mtk_hdmi_suspend, mtk_hdmi_resume); 1767 1768 static const struct of_device_id mtk_drm_hdmi_of_ids[] = { 1769 { .compatible = "mediatek,mt8173-hdmi", }, 1770 {} 1771 }; 1772 1773 static struct platform_driver mtk_hdmi_driver = { 1774 .probe = mtk_drm_hdmi_probe, 1775 .remove = mtk_drm_hdmi_remove, 1776 .driver = { 1777 .name = "mediatek-drm-hdmi", 1778 .of_match_table = mtk_drm_hdmi_of_ids, 1779 .pm = &mtk_hdmi_pm_ops, 1780 }, 1781 }; 1782 1783 static struct platform_driver * const mtk_hdmi_drivers[] = { 1784 &mtk_hdmi_phy_driver, 1785 &mtk_hdmi_ddc_driver, 1786 &mtk_cec_driver, 1787 &mtk_hdmi_driver, 1788 }; 1789 1790 static int __init mtk_hdmitx_init(void) 1791 { 1792 return platform_register_drivers(mtk_hdmi_drivers, 1793 ARRAY_SIZE(mtk_hdmi_drivers)); 1794 } 1795 1796 static void __exit mtk_hdmitx_exit(void) 1797 { 1798 platform_unregister_drivers(mtk_hdmi_drivers, 1799 ARRAY_SIZE(mtk_hdmi_drivers)); 1800 } 1801 1802 module_init(mtk_hdmitx_init); 1803 module_exit(mtk_hdmitx_exit); 1804 1805 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); 1806 MODULE_DESCRIPTION("MediaTek HDMI Driver"); 1807 MODULE_LICENSE("GPL v2"); 1808