14b11cb7fSPaul Cercueil /* SPDX-License-Identifier: GPL-2.0 */ 24b11cb7fSPaul Cercueil // 34b11cb7fSPaul Cercueil // Ingenic JZ47xx KMS driver - Register definitions and private API 44b11cb7fSPaul Cercueil // 54b11cb7fSPaul Cercueil // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 64b11cb7fSPaul Cercueil 74b11cb7fSPaul Cercueil #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 84b11cb7fSPaul Cercueil #define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 94b11cb7fSPaul Cercueil 104b11cb7fSPaul Cercueil #include <linux/bitops.h> 114b11cb7fSPaul Cercueil 124b11cb7fSPaul Cercueil #define JZ_REG_LCD_CFG 0x00 134b11cb7fSPaul Cercueil #define JZ_REG_LCD_VSYNC 0x04 144b11cb7fSPaul Cercueil #define JZ_REG_LCD_HSYNC 0x08 154b11cb7fSPaul Cercueil #define JZ_REG_LCD_VAT 0x0C 164b11cb7fSPaul Cercueil #define JZ_REG_LCD_DAH 0x10 174b11cb7fSPaul Cercueil #define JZ_REG_LCD_DAV 0x14 184b11cb7fSPaul Cercueil #define JZ_REG_LCD_PS 0x18 194b11cb7fSPaul Cercueil #define JZ_REG_LCD_CLS 0x1C 204b11cb7fSPaul Cercueil #define JZ_REG_LCD_SPL 0x20 214b11cb7fSPaul Cercueil #define JZ_REG_LCD_REV 0x24 224b11cb7fSPaul Cercueil #define JZ_REG_LCD_CTRL 0x30 234b11cb7fSPaul Cercueil #define JZ_REG_LCD_STATE 0x34 244b11cb7fSPaul Cercueil #define JZ_REG_LCD_IID 0x38 254b11cb7fSPaul Cercueil #define JZ_REG_LCD_DA0 0x40 264b11cb7fSPaul Cercueil #define JZ_REG_LCD_SA0 0x44 274b11cb7fSPaul Cercueil #define JZ_REG_LCD_FID0 0x48 284b11cb7fSPaul Cercueil #define JZ_REG_LCD_CMD0 0x4C 294b11cb7fSPaul Cercueil #define JZ_REG_LCD_DA1 0x50 304b11cb7fSPaul Cercueil #define JZ_REG_LCD_SA1 0x54 314b11cb7fSPaul Cercueil #define JZ_REG_LCD_FID1 0x58 324b11cb7fSPaul Cercueil #define JZ_REG_LCD_CMD1 0x5C 334b11cb7fSPaul Cercueil 344b11cb7fSPaul Cercueil #define JZ_LCD_CFG_SLCD BIT(31) 354b11cb7fSPaul Cercueil #define JZ_LCD_CFG_PS_DISABLE BIT(23) 364b11cb7fSPaul Cercueil #define JZ_LCD_CFG_CLS_DISABLE BIT(22) 374b11cb7fSPaul Cercueil #define JZ_LCD_CFG_SPL_DISABLE BIT(21) 384b11cb7fSPaul Cercueil #define JZ_LCD_CFG_REV_DISABLE BIT(20) 394b11cb7fSPaul Cercueil #define JZ_LCD_CFG_HSYNCM BIT(19) 404b11cb7fSPaul Cercueil #define JZ_LCD_CFG_PCLKM BIT(18) 414b11cb7fSPaul Cercueil #define JZ_LCD_CFG_INV BIT(17) 424b11cb7fSPaul Cercueil #define JZ_LCD_CFG_SYNC_DIR BIT(16) 434b11cb7fSPaul Cercueil #define JZ_LCD_CFG_PS_POLARITY BIT(15) 444b11cb7fSPaul Cercueil #define JZ_LCD_CFG_CLS_POLARITY BIT(14) 454b11cb7fSPaul Cercueil #define JZ_LCD_CFG_SPL_POLARITY BIT(13) 464b11cb7fSPaul Cercueil #define JZ_LCD_CFG_REV_POLARITY BIT(12) 474b11cb7fSPaul Cercueil #define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) 484b11cb7fSPaul Cercueil #define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) 494b11cb7fSPaul Cercueil #define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) 504b11cb7fSPaul Cercueil #define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) 514b11cb7fSPaul Cercueil #define JZ_LCD_CFG_18_BIT BIT(7) 524b11cb7fSPaul Cercueil #define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) 534b11cb7fSPaul Cercueil 544b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 554b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) 564b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) 574b11cb7fSPaul Cercueil 584b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1 594b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2 604b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_SPECIAL_TFT_3 3 614b11cb7fSPaul Cercueil 624b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_TV_OUT_P 4 634b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_TV_OUT_I 6 644b11cb7fSPaul Cercueil 654b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_SINGLE_COLOR_STN 8 664b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_SINGLE_MONOCHROME_STN 9 674b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_DUAL_COLOR_STN 10 684b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_DUAL_MONOCHROME_STN 11 694b11cb7fSPaul Cercueil 704b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_8BIT_SERIAL 12 714b11cb7fSPaul Cercueil #define JZ_LCD_CFG_MODE_LCM 13 724b11cb7fSPaul Cercueil 734b11cb7fSPaul Cercueil #define JZ_LCD_VSYNC_VPS_OFFSET 16 744b11cb7fSPaul Cercueil #define JZ_LCD_VSYNC_VPE_OFFSET 0 754b11cb7fSPaul Cercueil 764b11cb7fSPaul Cercueil #define JZ_LCD_HSYNC_HPS_OFFSET 16 774b11cb7fSPaul Cercueil #define JZ_LCD_HSYNC_HPE_OFFSET 0 784b11cb7fSPaul Cercueil 794b11cb7fSPaul Cercueil #define JZ_LCD_VAT_HT_OFFSET 16 804b11cb7fSPaul Cercueil #define JZ_LCD_VAT_VT_OFFSET 0 814b11cb7fSPaul Cercueil 824b11cb7fSPaul Cercueil #define JZ_LCD_DAH_HDS_OFFSET 16 834b11cb7fSPaul Cercueil #define JZ_LCD_DAH_HDE_OFFSET 0 844b11cb7fSPaul Cercueil 854b11cb7fSPaul Cercueil #define JZ_LCD_DAV_VDS_OFFSET 16 864b11cb7fSPaul Cercueil #define JZ_LCD_DAV_VDE_OFFSET 0 874b11cb7fSPaul Cercueil 884b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BURST_4 (0x0 << 28) 894b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BURST_8 (0x1 << 28) 904b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BURST_16 (0x2 << 28) 914b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_RGB555 BIT(27) 924b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_OFUP BIT(26) 934b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24) 944b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24) 954b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24) 964b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_PDD_MASK (0xff << 16) 974b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_EOF_IRQ BIT(13) 984b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_SOF_IRQ BIT(12) 994b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_OFU_IRQ BIT(11) 1004b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_IFU0_IRQ BIT(10) 1014b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_IFU1_IRQ BIT(9) 1024b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_DD_IRQ BIT(8) 1034b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_QDD_IRQ BIT(7) 1044b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6) 1054b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_LSB_FISRT BIT(5) 1064b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_DISABLE BIT(4) 1074b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_ENABLE BIT(3) 1084b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_1 0x0 1094b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_2 0x1 1104b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_4 0x2 1114b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_8 0x3 1124b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_15_16 0x4 1134b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_18_24 0x5 1144b11cb7fSPaul Cercueil #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 1154b11cb7fSPaul Cercueil 1164b11cb7fSPaul Cercueil #define JZ_LCD_CMD_SOF_IRQ BIT(31) 1174b11cb7fSPaul Cercueil #define JZ_LCD_CMD_EOF_IRQ BIT(30) 1184b11cb7fSPaul Cercueil #define JZ_LCD_CMD_ENABLE_PAL BIT(28) 1194b11cb7fSPaul Cercueil 1204b11cb7fSPaul Cercueil #define JZ_LCD_SYNC_MASK 0x3ff 1214b11cb7fSPaul Cercueil 1224b11cb7fSPaul Cercueil #define JZ_LCD_STATE_EOF_IRQ BIT(5) 1234b11cb7fSPaul Cercueil #define JZ_LCD_STATE_SOF_IRQ BIT(4) 1244b11cb7fSPaul Cercueil #define JZ_LCD_STATE_DISABLED BIT(0) 1254b11cb7fSPaul Cercueil 1264b11cb7fSPaul Cercueil #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ 127