1 // SPDX-License-Identifier: GPL-2.0-only 2 // SPDX-FileCopyrightText: 2020 Marian Cichy <M.Cichy@pengutronix.de> 3 4 #include <drm/drm_bridge_connector.h> 5 #include <drm/drm_damage_helper.h> 6 #include <drm/drm_drv.h> 7 #include <drm/drm_fbdev_generic.h> 8 #include <drm/drm_fb_dma_helper.h> 9 #include <drm/drm_fourcc.h> 10 #include <drm/drm_framebuffer.h> 11 #include <drm/drm_gem_atomic_helper.h> 12 #include <drm/drm_gem_dma_helper.h> 13 #include <drm/drm_gem_framebuffer_helper.h> 14 #include <drm/drm_of.h> 15 #include <drm/drm_probe_helper.h> 16 #include <drm/drm_simple_kms_helper.h> 17 #include <drm/drm_vblank.h> 18 #include <linux/bitfield.h> 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/module.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 25 #define IMX21LCDC_LSSAR 0x0000 /* LCDC Screen Start Address Register */ 26 #define IMX21LCDC_LSR 0x0004 /* LCDC Size Register */ 27 #define IMX21LCDC_LVPWR 0x0008 /* LCDC Virtual Page Width Register */ 28 #define IMX21LCDC_LCPR 0x000C /* LCDC Cursor Position Register */ 29 #define IMX21LCDC_LCWHB 0x0010 /* LCDC Cursor Width Height and Blink Register*/ 30 #define IMX21LCDC_LCCMR 0x0014 /* LCDC Color Cursor Mapping Register */ 31 #define IMX21LCDC_LPCR 0x0018 /* LCDC Panel Configuration Register */ 32 #define IMX21LCDC_LHCR 0x001C /* LCDC Horizontal Configuration Register */ 33 #define IMX21LCDC_LVCR 0x0020 /* LCDC Vertical Configuration Register */ 34 #define IMX21LCDC_LPOR 0x0024 /* LCDC Panning Offset Register */ 35 #define IMX21LCDC_LSCR 0x0028 /* LCDC Sharp Configuration Register */ 36 #define IMX21LCDC_LPCCR 0x002C /* LCDC PWM Contrast Control Register */ 37 #define IMX21LCDC_LDCR 0x0030 /* LCDC DMA Control Register */ 38 #define IMX21LCDC_LRMCR 0x0034 /* LCDC Refresh Mode Control Register */ 39 #define IMX21LCDC_LICR 0x0038 /* LCDC Interrupt Configuration Register */ 40 #define IMX21LCDC_LIER 0x003C /* LCDC Interrupt Enable Register */ 41 #define IMX21LCDC_LISR 0x0040 /* LCDC Interrupt Status Register */ 42 #define IMX21LCDC_LGWSAR 0x0050 /* LCDC Graphic Window Start Address Register */ 43 #define IMX21LCDC_LGWSR 0x0054 /* LCDC Graph Window Size Register */ 44 #define IMX21LCDC_LGWVPWR 0x0058 /* LCDC Graphic Window Virtual Page Width Register */ 45 #define IMX21LCDC_LGWPOR 0x005C /* LCDC Graphic Window Panning Offset Register */ 46 #define IMX21LCDC_LGWPR 0x0060 /* LCDC Graphic Window Position Register */ 47 #define IMX21LCDC_LGWCR 0x0064 /* LCDC Graphic Window Control Register */ 48 #define IMX21LCDC_LGWDCR 0x0068 /* LCDC Graphic Window DMA Control Register */ 49 #define IMX21LCDC_LAUSCR 0x0080 /* LCDC AUS Mode Control Register */ 50 #define IMX21LCDC_LAUSCCR 0x0084 /* LCDC AUS Mode Cursor Control Register */ 51 #define IMX21LCDC_BGLUT 0x0800 /* Background Lookup Table */ 52 #define IMX21LCDC_GWLUT 0x0C00 /* Graphic Window Lookup Table */ 53 54 #define IMX21LCDC_LCPR_CC0 BIT(30) /* Cursor Control Bit 0 */ 55 #define IMX21LCDC_LCPR_CC1 BIT(31) /* Cursor Control Bit 1 */ 56 57 /* Values HSYNC, VSYNC and Framesize Register */ 58 #define IMX21LCDC_LHCR_HWIDTH GENMASK(31, 26) 59 #define IMX21LCDC_LHCR_HFPORCH GENMASK(15, 8) /* H_WAIT_1 in the i.MX25 Reference manual */ 60 #define IMX21LCDC_LHCR_HBPORCH GENMASK(7, 0) /* H_WAIT_2 in the i.MX25 Reference manual */ 61 62 #define IMX21LCDC_LVCR_VWIDTH GENMASK(31, 26) 63 #define IMX21LCDC_LVCR_VFPORCH GENMASK(15, 8) /* V_WAIT_1 in the i.MX25 Reference manual */ 64 #define IMX21LCDC_LVCR_VBPORCH GENMASK(7, 0) /* V_WAIT_2 in the i.MX25 Reference manual */ 65 66 #define IMX21LCDC_LSR_XMAX GENMASK(25, 20) 67 #define IMX21LCDC_LSR_YMAX GENMASK(9, 0) 68 69 /* Values for LPCR Register */ 70 #define IMX21LCDC_LPCR_PCD GENMASK(5, 0) 71 #define IMX21LCDC_LPCR_SHARP BIT(6) 72 #define IMX21LCDC_LPCR_SCLKSEL BIT(7) 73 #define IMX21LCDC_LPCR_ACD GENMASK(14, 8) 74 #define IMX21LCDC_LPCR_ACDSEL BIT(15) 75 #define IMX21LCDC_LPCR_REV_VS BIT(16) 76 #define IMX21LCDC_LPCR_SWAP_SEL BIT(17) 77 #define IMX21LCDC_LPCR_END_SEL BIT(18) 78 #define IMX21LCDC_LPCR_SCLKIDLE BIT(19) 79 #define IMX21LCDC_LPCR_OEPOL BIT(20) 80 #define IMX21LCDC_LPCR_CLKPOL BIT(21) 81 #define IMX21LCDC_LPCR_LPPOL BIT(22) 82 #define IMX21LCDC_LPCR_FLMPOL BIT(23) 83 #define IMX21LCDC_LPCR_PIXPOL BIT(24) 84 #define IMX21LCDC_LPCR_BPIX GENMASK(27, 25) 85 #define IMX21LCDC_LPCR_PBSIZ GENMASK(29, 28) 86 #define IMX21LCDC_LPCR_COLOR BIT(30) 87 #define IMX21LCDC_LPCR_TFT BIT(31) 88 89 #define INTR_EOF BIT(1) /* VBLANK Interrupt Bit */ 90 91 #define BPP_RGB565 0x05 92 #define BPP_XRGB8888 0x07 93 94 #define LCDC_MIN_XRES 64 95 #define LCDC_MIN_YRES 64 96 97 #define LCDC_MAX_XRES 1024 98 #define LCDC_MAX_YRES 1024 99 100 struct imx_lcdc { 101 struct drm_device drm; 102 struct drm_simple_display_pipe pipe; 103 struct drm_connector *connector; 104 void __iomem *base; 105 106 struct clk *clk_ipg; 107 struct clk *clk_ahb; 108 struct clk *clk_per; 109 }; 110 111 static const u32 imx_lcdc_formats[] = { 112 DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, 113 }; 114 115 static inline struct imx_lcdc *imx_lcdc_from_drmdev(struct drm_device *drm) 116 { 117 return container_of(drm, struct imx_lcdc, drm); 118 } 119 120 static unsigned int imx_lcdc_get_format(unsigned int drm_format) 121 { 122 switch (drm_format) { 123 default: 124 DRM_WARN("Format not supported - fallback to XRGB8888\n"); 125 fallthrough; 126 127 case DRM_FORMAT_XRGB8888: 128 return BPP_XRGB8888; 129 130 case DRM_FORMAT_RGB565: 131 return BPP_RGB565; 132 } 133 } 134 135 static void imx_lcdc_update_hw_registers(struct drm_simple_display_pipe *pipe, 136 struct drm_plane_state *old_state, 137 bool mode_set) 138 { 139 struct drm_crtc *crtc = &pipe->crtc; 140 struct drm_plane_state *new_state = pipe->plane.state; 141 struct drm_framebuffer *fb = new_state->fb; 142 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); 143 u32 lpcr, lvcr, lhcr; 144 u32 framesize; 145 dma_addr_t addr; 146 147 addr = drm_fb_dma_get_gem_addr(fb, new_state, 0); 148 /* The LSSAR register specifies the LCD screen start address (SSA). */ 149 writel(addr, lcdc->base + IMX21LCDC_LSSAR); 150 151 if (!mode_set) 152 return; 153 154 /* Disable PER clock to make register write possible */ 155 if (old_state && old_state->crtc && old_state->crtc->enabled) 156 clk_disable_unprepare(lcdc->clk_per); 157 158 /* Framesize */ 159 framesize = FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) | 160 FIELD_PREP(IMX21LCDC_LSR_YMAX, crtc->mode.vdisplay); 161 writel(framesize, lcdc->base + IMX21LCDC_LSR); 162 163 /* HSYNC */ 164 lhcr = FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc->mode.hdisplay - 1) | 165 FIELD_PREP(IMX21LCDC_LHCR_HWIDTH, crtc->mode.hsync_end - crtc->mode.hsync_start - 1) | 166 FIELD_PREP(IMX21LCDC_LHCR_HBPORCH, crtc->mode.htotal - crtc->mode.hsync_end - 3); 167 writel(lhcr, lcdc->base + IMX21LCDC_LHCR); 168 169 /* VSYNC */ 170 lvcr = FIELD_PREP(IMX21LCDC_LVCR_VFPORCH, crtc->mode.vsync_start - crtc->mode.vdisplay) | 171 FIELD_PREP(IMX21LCDC_LVCR_VWIDTH, crtc->mode.vsync_end - crtc->mode.vsync_start) | 172 FIELD_PREP(IMX21LCDC_LVCR_VBPORCH, crtc->mode.vtotal - crtc->mode.vsync_end); 173 writel(lvcr, lcdc->base + IMX21LCDC_LVCR); 174 175 lpcr = readl(lcdc->base + IMX21LCDC_LPCR); 176 lpcr &= ~IMX21LCDC_LPCR_BPIX; 177 lpcr |= FIELD_PREP(IMX21LCDC_LPCR_BPIX, imx_lcdc_get_format(fb->format->format)); 178 writel(lpcr, lcdc->base + IMX21LCDC_LPCR); 179 180 /* Virtual Page Width */ 181 writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR); 182 183 /* Enable PER clock */ 184 if (new_state->crtc->enabled) 185 clk_prepare_enable(lcdc->clk_per); 186 } 187 188 static void imx_lcdc_pipe_enable(struct drm_simple_display_pipe *pipe, 189 struct drm_crtc_state *crtc_state, 190 struct drm_plane_state *plane_state) 191 { 192 int ret; 193 int clk_div; 194 int bpp; 195 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); 196 struct drm_display_mode *mode = &pipe->crtc.mode; 197 struct drm_display_info *disp_info = &lcdc->connector->display_info; 198 const int hsync_pol = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : 1; 199 const int vsync_pol = (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : 1; 200 const int data_enable_pol = 201 (disp_info->bus_flags & DRM_BUS_FLAG_DE_HIGH) ? 0 : 1; 202 const int clk_pol = 203 (disp_info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) ? 0 : 1; 204 205 clk_div = DIV_ROUND_CLOSEST_ULL(clk_get_rate(lcdc->clk_per), 206 mode->clock * 1000); 207 bpp = imx_lcdc_get_format(plane_state->fb->format->format); 208 209 writel(FIELD_PREP(IMX21LCDC_LPCR_PCD, clk_div - 1) | 210 FIELD_PREP(IMX21LCDC_LPCR_LPPOL, hsync_pol) | 211 FIELD_PREP(IMX21LCDC_LPCR_FLMPOL, vsync_pol) | 212 FIELD_PREP(IMX21LCDC_LPCR_OEPOL, data_enable_pol) | 213 FIELD_PREP(IMX21LCDC_LPCR_TFT, 1) | 214 FIELD_PREP(IMX21LCDC_LPCR_COLOR, 1) | 215 FIELD_PREP(IMX21LCDC_LPCR_PBSIZ, 3) | 216 FIELD_PREP(IMX21LCDC_LPCR_BPIX, bpp) | 217 FIELD_PREP(IMX21LCDC_LPCR_SCLKSEL, 1) | 218 FIELD_PREP(IMX21LCDC_LPCR_PIXPOL, 0) | 219 FIELD_PREP(IMX21LCDC_LPCR_CLKPOL, clk_pol), 220 lcdc->base + IMX21LCDC_LPCR); 221 222 /* 0px panning offset */ 223 writel(0x00000000, lcdc->base + IMX21LCDC_LPOR); 224 225 /* disable hardware cursor */ 226 writel(readl(lcdc->base + IMX21LCDC_LCPR) & ~(IMX21LCDC_LCPR_CC0 | IMX21LCDC_LCPR_CC1), 227 lcdc->base + IMX21LCDC_LCPR); 228 229 ret = clk_prepare_enable(lcdc->clk_ipg); 230 if (ret) { 231 dev_err(pipe->crtc.dev->dev, "Cannot enable ipg clock: %pe\n", ERR_PTR(ret)); 232 return; 233 } 234 ret = clk_prepare_enable(lcdc->clk_ahb); 235 if (ret) { 236 dev_err(pipe->crtc.dev->dev, "Cannot enable ahb clock: %pe\n", ERR_PTR(ret)); 237 238 clk_disable_unprepare(lcdc->clk_ipg); 239 240 return; 241 } 242 243 imx_lcdc_update_hw_registers(pipe, NULL, true); 244 245 /* Enable VBLANK Interrupt */ 246 writel(INTR_EOF, lcdc->base + IMX21LCDC_LIER); 247 } 248 249 static void imx_lcdc_pipe_disable(struct drm_simple_display_pipe *pipe) 250 { 251 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(pipe->crtc.dev); 252 struct drm_crtc *crtc = &lcdc->pipe.crtc; 253 struct drm_pending_vblank_event *event; 254 255 clk_disable_unprepare(lcdc->clk_ahb); 256 clk_disable_unprepare(lcdc->clk_ipg); 257 258 if (pipe->crtc.enabled) 259 clk_disable_unprepare(lcdc->clk_per); 260 261 spin_lock_irq(&lcdc->drm.event_lock); 262 event = crtc->state->event; 263 if (event) { 264 crtc->state->event = NULL; 265 drm_crtc_send_vblank_event(crtc, event); 266 } 267 spin_unlock_irq(&lcdc->drm.event_lock); 268 269 /* Disable VBLANK Interrupt */ 270 writel(0, lcdc->base + IMX21LCDC_LIER); 271 } 272 273 static int imx_lcdc_pipe_check(struct drm_simple_display_pipe *pipe, 274 struct drm_plane_state *plane_state, 275 struct drm_crtc_state *crtc_state) 276 { 277 const struct drm_display_mode *mode = &crtc_state->mode; 278 const struct drm_display_mode *old_mode = &pipe->crtc.state->mode; 279 280 if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES || 281 mode->vdisplay < LCDC_MIN_YRES || mode->vdisplay > LCDC_MAX_YRES || 282 mode->hdisplay % 0x10) { /* must be multiple of 16 */ 283 drm_err(pipe->crtc.dev, "unsupported display mode (%u x %u)\n", 284 mode->hdisplay, mode->vdisplay); 285 return -EINVAL; 286 } 287 288 crtc_state->mode_changed = 289 old_mode->hdisplay != mode->hdisplay || 290 old_mode->vdisplay != mode->vdisplay; 291 292 return 0; 293 } 294 295 static void imx_lcdc_pipe_update(struct drm_simple_display_pipe *pipe, 296 struct drm_plane_state *old_state) 297 { 298 struct drm_crtc *crtc = &pipe->crtc; 299 struct drm_pending_vblank_event *event = crtc->state->event; 300 struct drm_plane_state *new_state = pipe->plane.state; 301 struct drm_framebuffer *fb = new_state->fb; 302 struct drm_framebuffer *old_fb = old_state->fb; 303 struct drm_crtc *old_crtc = old_state->crtc; 304 bool mode_changed = false; 305 306 if (old_fb && old_fb->format != fb->format) 307 mode_changed = true; 308 else if (old_crtc != crtc) 309 mode_changed = true; 310 311 imx_lcdc_update_hw_registers(pipe, old_state, mode_changed); 312 313 if (event) { 314 crtc->state->event = NULL; 315 316 spin_lock_irq(&crtc->dev->event_lock); 317 318 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 319 drm_crtc_arm_vblank_event(crtc, event); 320 else 321 drm_crtc_send_vblank_event(crtc, event); 322 323 spin_unlock_irq(&crtc->dev->event_lock); 324 } 325 } 326 327 static const struct drm_simple_display_pipe_funcs imx_lcdc_pipe_funcs = { 328 .enable = imx_lcdc_pipe_enable, 329 .disable = imx_lcdc_pipe_disable, 330 .check = imx_lcdc_pipe_check, 331 .update = imx_lcdc_pipe_update, 332 }; 333 334 static const struct drm_mode_config_funcs imx_lcdc_mode_config_funcs = { 335 .fb_create = drm_gem_fb_create_with_dirty, 336 .atomic_check = drm_atomic_helper_check, 337 .atomic_commit = drm_atomic_helper_commit, 338 }; 339 340 static const struct drm_mode_config_helper_funcs imx_lcdc_mode_config_helpers = { 341 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 342 }; 343 344 static void imx_lcdc_release(struct drm_device *drm) 345 { 346 struct imx_lcdc *lcdc = imx_lcdc_from_drmdev(drm); 347 348 drm_kms_helper_poll_fini(drm); 349 kfree(lcdc); 350 } 351 352 DEFINE_DRM_GEM_DMA_FOPS(imx_lcdc_drm_fops); 353 354 static struct drm_driver imx_lcdc_drm_driver = { 355 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 356 .fops = &imx_lcdc_drm_fops, 357 DRM_GEM_DMA_DRIVER_OPS_VMAP, 358 .release = imx_lcdc_release, 359 .name = "imx-lcdc", 360 .desc = "i.MX LCDC driver", 361 .date = "20200716", 362 }; 363 364 static const struct of_device_id imx_lcdc_of_dev_id[] = { 365 { 366 .compatible = "fsl,imx21-lcdc", 367 }, 368 { 369 .compatible = "fsl,imx25-lcdc", 370 }, 371 { /* sentinel */ } 372 }; 373 MODULE_DEVICE_TABLE(of, imx_lcdc_of_dev_id); 374 375 static irqreturn_t imx_lcdc_irq_handler(int irq, void *arg) 376 { 377 struct imx_lcdc *lcdc = arg; 378 struct drm_crtc *crtc = &lcdc->pipe.crtc; 379 unsigned int status; 380 381 status = readl(lcdc->base + IMX21LCDC_LISR); 382 383 if (status & INTR_EOF) { 384 drm_crtc_handle_vblank(crtc); 385 return IRQ_HANDLED; 386 } 387 388 return IRQ_NONE; 389 } 390 391 static int imx_lcdc_probe(struct platform_device *pdev) 392 { 393 struct imx_lcdc *lcdc; 394 struct drm_device *drm; 395 struct drm_bridge *bridge; 396 int irq; 397 int ret; 398 struct device *dev = &pdev->dev; 399 400 lcdc = devm_drm_dev_alloc(dev, &imx_lcdc_drm_driver, 401 struct imx_lcdc, drm); 402 if (!lcdc) 403 return -ENOMEM; 404 405 drm = &lcdc->drm; 406 407 lcdc->base = devm_platform_ioremap_resource(pdev, 0); 408 if (IS_ERR(lcdc->base)) 409 return dev_err_probe(dev, PTR_ERR(lcdc->base), "Cannot get IO memory\n"); 410 411 bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0); 412 if (IS_ERR(bridge)) 413 return dev_err_probe(dev, PTR_ERR(bridge), "Failed to find bridge\n"); 414 415 /* Get Clocks */ 416 lcdc->clk_ipg = devm_clk_get(dev, "ipg"); 417 if (IS_ERR(lcdc->clk_ipg)) 418 return dev_err_probe(dev, PTR_ERR(lcdc->clk_ipg), "Failed to get %s clk\n", "ipg"); 419 420 lcdc->clk_ahb = devm_clk_get(dev, "ahb"); 421 if (IS_ERR(lcdc->clk_ahb)) 422 return dev_err_probe(dev, PTR_ERR(lcdc->clk_ahb), "Failed to get %s clk\n", "ahb"); 423 424 lcdc->clk_per = devm_clk_get(dev, "per"); 425 if (IS_ERR(lcdc->clk_per)) 426 return dev_err_probe(dev, PTR_ERR(lcdc->clk_per), "Failed to get %s clk\n", "per"); 427 428 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 429 if (ret) 430 return dev_err_probe(dev, ret, "Cannot set DMA Mask\n"); 431 432 /* Modeset init */ 433 ret = drmm_mode_config_init(drm); 434 if (ret) 435 return dev_err_probe(dev, ret, "Cannot initialize mode configuration structure\n"); 436 437 /* CRTC, Plane, Encoder */ 438 ret = drm_simple_display_pipe_init(drm, &lcdc->pipe, 439 &imx_lcdc_pipe_funcs, 440 imx_lcdc_formats, 441 ARRAY_SIZE(imx_lcdc_formats), NULL, NULL); 442 if (ret < 0) 443 return dev_err_probe(drm->dev, ret, "Cannot setup simple display pipe\n"); 444 445 ret = drm_vblank_init(drm, drm->mode_config.num_crtc); 446 if (ret < 0) 447 return dev_err_probe(drm->dev, ret, "Failed to initialize vblank\n"); 448 449 ret = drm_bridge_attach(&lcdc->pipe.encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 450 if (ret) 451 return dev_err_probe(drm->dev, ret, "Cannot attach bridge\n"); 452 453 lcdc->connector = drm_bridge_connector_init(drm, &lcdc->pipe.encoder); 454 if (IS_ERR(lcdc->connector)) 455 return dev_err_probe(drm->dev, PTR_ERR(lcdc->connector), "Cannot init bridge connector\n"); 456 457 drm_connector_attach_encoder(lcdc->connector, &lcdc->pipe.encoder); 458 459 /* 460 * The LCDC controller does not have an enable bit. The 461 * controller starts directly when the clocks are enabled. 462 * If the clocks are enabled when the controller is not yet 463 * programmed with proper register values (enabled at the 464 * bootloader, for example) then it just goes into some undefined 465 * state. 466 * To avoid this issue, let's enable and disable LCDC IPG, 467 * PER and AHB clock so that we force some kind of 'reset' 468 * to the LCDC block. 469 */ 470 471 ret = clk_prepare_enable(lcdc->clk_ipg); 472 if (ret) 473 return dev_err_probe(dev, ret, "Cannot enable ipg clock\n"); 474 clk_disable_unprepare(lcdc->clk_ipg); 475 476 ret = clk_prepare_enable(lcdc->clk_per); 477 if (ret) 478 return dev_err_probe(dev, ret, "Cannot enable per clock\n"); 479 clk_disable_unprepare(lcdc->clk_per); 480 481 ret = clk_prepare_enable(lcdc->clk_ahb); 482 if (ret) 483 return dev_err_probe(dev, ret, "Cannot enable ahb clock\n"); 484 clk_disable_unprepare(lcdc->clk_ahb); 485 486 drm->mode_config.min_width = LCDC_MIN_XRES; 487 drm->mode_config.max_width = LCDC_MAX_XRES; 488 drm->mode_config.min_height = LCDC_MIN_YRES; 489 drm->mode_config.max_height = LCDC_MAX_YRES; 490 drm->mode_config.preferred_depth = 16; 491 drm->mode_config.funcs = &imx_lcdc_mode_config_funcs; 492 drm->mode_config.helper_private = &imx_lcdc_mode_config_helpers; 493 494 drm_mode_config_reset(drm); 495 496 irq = platform_get_irq(pdev, 0); 497 if (irq < 0) { 498 ret = irq; 499 return ret; 500 } 501 502 ret = devm_request_irq(dev, irq, imx_lcdc_irq_handler, 0, "imx-lcdc", lcdc); 503 if (ret < 0) 504 return dev_err_probe(drm->dev, ret, "Failed to install IRQ handler\n"); 505 506 platform_set_drvdata(pdev, drm); 507 508 ret = drm_dev_register(&lcdc->drm, 0); 509 if (ret) 510 return dev_err_probe(dev, ret, "Cannot register device\n"); 511 512 drm_fbdev_generic_setup(drm, 0); 513 514 return 0; 515 } 516 517 static int imx_lcdc_remove(struct platform_device *pdev) 518 { 519 struct drm_device *drm = platform_get_drvdata(pdev); 520 521 drm_dev_unregister(drm); 522 drm_atomic_helper_shutdown(drm); 523 524 return 0; 525 } 526 527 static void imx_lcdc_shutdown(struct platform_device *pdev) 528 { 529 drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); 530 } 531 532 static struct platform_driver imx_lcdc_driver = { 533 .driver = { 534 .name = "imx-lcdc", 535 .of_match_table = imx_lcdc_of_dev_id, 536 }, 537 .probe = imx_lcdc_probe, 538 .remove = imx_lcdc_remove, 539 .shutdown = imx_lcdc_shutdown, 540 }; 541 module_platform_driver(imx_lcdc_driver); 542 543 MODULE_AUTHOR("Marian Cichy <M.Cichy@pengutronix.de>"); 544 MODULE_DESCRIPTION("Freescale i.MX LCDC driver"); 545 MODULE_LICENSE("GPL"); 546