1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <linux/device.h> 29 #include <linux/module.h> 30 #include <linux/stat.h> 31 #include <linux/sysfs.h> 32 33 #include "gt/intel_rc6.h" 34 35 #include "i915_drv.h" 36 #include "i915_sysfs.h" 37 #include "intel_pm.h" 38 #include "intel_sideband.h" 39 40 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) 41 { 42 struct drm_minor *minor = dev_get_drvdata(kdev); 43 return to_i915(minor->dev); 44 } 45 46 #ifdef CONFIG_PM 47 static u32 calc_residency(struct drm_i915_private *dev_priv, 48 i915_reg_t reg) 49 { 50 intel_wakeref_t wakeref; 51 u64 res = 0; 52 53 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) 54 res = intel_rc6_residency_us(&dev_priv->gt.rc6, reg); 55 56 return DIV_ROUND_CLOSEST_ULL(res, 1000); 57 } 58 59 static ssize_t 60 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) 61 { 62 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 63 unsigned int mask; 64 65 mask = 0; 66 if (HAS_RC6(dev_priv)) 67 mask |= BIT(0); 68 if (HAS_RC6p(dev_priv)) 69 mask |= BIT(1); 70 if (HAS_RC6pp(dev_priv)) 71 mask |= BIT(2); 72 73 return snprintf(buf, PAGE_SIZE, "%x\n", mask); 74 } 75 76 static ssize_t 77 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 78 { 79 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 80 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); 81 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 82 } 83 84 static ssize_t 85 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) 86 { 87 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 88 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); 89 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 90 } 91 92 static ssize_t 93 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) 94 { 95 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 96 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); 97 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 98 } 99 100 static ssize_t 101 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 102 { 103 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 104 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); 105 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 106 } 107 108 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); 109 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); 110 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); 111 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); 112 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); 113 114 static struct attribute *rc6_attrs[] = { 115 &dev_attr_rc6_enable.attr, 116 &dev_attr_rc6_residency_ms.attr, 117 NULL 118 }; 119 120 static const struct attribute_group rc6_attr_group = { 121 .name = power_group_name, 122 .attrs = rc6_attrs 123 }; 124 125 static struct attribute *rc6p_attrs[] = { 126 &dev_attr_rc6p_residency_ms.attr, 127 &dev_attr_rc6pp_residency_ms.attr, 128 NULL 129 }; 130 131 static const struct attribute_group rc6p_attr_group = { 132 .name = power_group_name, 133 .attrs = rc6p_attrs 134 }; 135 136 static struct attribute *media_rc6_attrs[] = { 137 &dev_attr_media_rc6_residency_ms.attr, 138 NULL 139 }; 140 141 static const struct attribute_group media_rc6_attr_group = { 142 .name = power_group_name, 143 .attrs = media_rc6_attrs 144 }; 145 #endif 146 147 static int l3_access_valid(struct drm_i915_private *i915, loff_t offset) 148 { 149 if (!HAS_L3_DPF(i915)) 150 return -EPERM; 151 152 if (!IS_ALIGNED(offset, sizeof(u32))) 153 return -EINVAL; 154 155 if (offset >= GEN7_L3LOG_SIZE) 156 return -ENXIO; 157 158 return 0; 159 } 160 161 static ssize_t 162 i915_l3_read(struct file *filp, struct kobject *kobj, 163 struct bin_attribute *attr, char *buf, 164 loff_t offset, size_t count) 165 { 166 struct device *kdev = kobj_to_dev(kobj); 167 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 168 int slice = (int)(uintptr_t)attr->private; 169 int ret; 170 171 ret = l3_access_valid(i915, offset); 172 if (ret) 173 return ret; 174 175 count = round_down(count, sizeof(u32)); 176 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 177 memset(buf, 0, count); 178 179 spin_lock(&i915->gem.contexts.lock); 180 if (i915->l3_parity.remap_info[slice]) 181 memcpy(buf, 182 i915->l3_parity.remap_info[slice] + offset / sizeof(u32), 183 count); 184 spin_unlock(&i915->gem.contexts.lock); 185 186 return count; 187 } 188 189 static ssize_t 190 i915_l3_write(struct file *filp, struct kobject *kobj, 191 struct bin_attribute *attr, char *buf, 192 loff_t offset, size_t count) 193 { 194 struct device *kdev = kobj_to_dev(kobj); 195 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 196 int slice = (int)(uintptr_t)attr->private; 197 u32 *remap_info, *freeme = NULL; 198 struct i915_gem_context *ctx; 199 int ret; 200 201 ret = l3_access_valid(i915, offset); 202 if (ret) 203 return ret; 204 205 if (count < sizeof(u32)) 206 return -EINVAL; 207 208 remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 209 if (!remap_info) 210 return -ENOMEM; 211 212 spin_lock(&i915->gem.contexts.lock); 213 214 if (i915->l3_parity.remap_info[slice]) { 215 freeme = remap_info; 216 remap_info = i915->l3_parity.remap_info[slice]; 217 } else { 218 i915->l3_parity.remap_info[slice] = remap_info; 219 } 220 221 count = round_down(count, sizeof(u32)); 222 memcpy(remap_info + offset / sizeof(u32), buf, count); 223 224 /* NB: We defer the remapping until we switch to the context */ 225 list_for_each_entry(ctx, &i915->gem.contexts.list, link) 226 ctx->remap_slice |= BIT(slice); 227 228 spin_unlock(&i915->gem.contexts.lock); 229 kfree(freeme); 230 231 /* 232 * TODO: Ideally we really want a GPU reset here to make sure errors 233 * aren't propagated. Since I cannot find a stable way to reset the GPU 234 * at this point it is left as a TODO. 235 */ 236 237 return count; 238 } 239 240 static const struct bin_attribute dpf_attrs = { 241 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 242 .size = GEN7_L3LOG_SIZE, 243 .read = i915_l3_read, 244 .write = i915_l3_write, 245 .mmap = NULL, 246 .private = (void *)0 247 }; 248 249 static const struct bin_attribute dpf_attrs_1 = { 250 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 251 .size = GEN7_L3LOG_SIZE, 252 .read = i915_l3_read, 253 .write = i915_l3_write, 254 .mmap = NULL, 255 .private = (void *)1 256 }; 257 258 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 259 struct device_attribute *attr, char *buf) 260 { 261 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 262 intel_wakeref_t wakeref; 263 u32 freq; 264 265 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 266 267 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 268 vlv_punit_get(dev_priv); 269 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 270 vlv_punit_put(dev_priv); 271 272 freq = (freq >> 8) & 0xff; 273 } else { 274 freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1)); 275 } 276 277 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 278 279 return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq)); 280 } 281 282 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 283 struct device_attribute *attr, char *buf) 284 { 285 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 286 287 return snprintf(buf, PAGE_SIZE, "%d\n", 288 intel_gpu_freq(dev_priv, 289 dev_priv->gt_pm.rps.cur_freq)); 290 } 291 292 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 293 { 294 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 295 296 return snprintf(buf, PAGE_SIZE, "%d\n", 297 intel_gpu_freq(dev_priv, 298 dev_priv->gt_pm.rps.boost_freq)); 299 } 300 301 static ssize_t gt_boost_freq_mhz_store(struct device *kdev, 302 struct device_attribute *attr, 303 const char *buf, size_t count) 304 { 305 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 306 struct intel_rps *rps = &dev_priv->gt_pm.rps; 307 bool boost = false; 308 ssize_t ret; 309 u32 val; 310 311 ret = kstrtou32(buf, 0, &val); 312 if (ret) 313 return ret; 314 315 /* Validate against (static) hardware limits */ 316 val = intel_freq_opcode(dev_priv, val); 317 if (val < rps->min_freq || val > rps->max_freq) 318 return -EINVAL; 319 320 mutex_lock(&rps->lock); 321 if (val != rps->boost_freq) { 322 rps->boost_freq = val; 323 boost = atomic_read(&rps->num_waiters); 324 } 325 mutex_unlock(&rps->lock); 326 if (boost) 327 schedule_work(&rps->work); 328 329 return count; 330 } 331 332 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 333 struct device_attribute *attr, char *buf) 334 { 335 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 336 337 return snprintf(buf, PAGE_SIZE, "%d\n", 338 intel_gpu_freq(dev_priv, 339 dev_priv->gt_pm.rps.efficient_freq)); 340 } 341 342 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 343 { 344 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 345 346 return snprintf(buf, PAGE_SIZE, "%d\n", 347 intel_gpu_freq(dev_priv, 348 dev_priv->gt_pm.rps.max_freq_softlimit)); 349 } 350 351 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 352 struct device_attribute *attr, 353 const char *buf, size_t count) 354 { 355 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 356 struct intel_rps *rps = &dev_priv->gt_pm.rps; 357 intel_wakeref_t wakeref; 358 u32 val; 359 ssize_t ret; 360 361 ret = kstrtou32(buf, 0, &val); 362 if (ret) 363 return ret; 364 365 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 366 mutex_lock(&rps->lock); 367 368 val = intel_freq_opcode(dev_priv, val); 369 if (val < rps->min_freq || 370 val > rps->max_freq || 371 val < rps->min_freq_softlimit) { 372 ret = -EINVAL; 373 goto unlock; 374 } 375 376 if (val > rps->rp0_freq) 377 DRM_DEBUG("User requested overclocking to %d\n", 378 intel_gpu_freq(dev_priv, val)); 379 380 rps->max_freq_softlimit = val; 381 382 val = clamp_t(int, rps->cur_freq, 383 rps->min_freq_softlimit, 384 rps->max_freq_softlimit); 385 386 /* We still need *_set_rps to process the new max_delay and 387 * update the interrupt limits and PMINTRMSK even though 388 * frequency request may be unchanged. */ 389 ret = intel_set_rps(dev_priv, val); 390 391 unlock: 392 mutex_unlock(&rps->lock); 393 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 394 395 return ret ?: count; 396 } 397 398 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 399 { 400 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 401 402 return snprintf(buf, PAGE_SIZE, "%d\n", 403 intel_gpu_freq(dev_priv, 404 dev_priv->gt_pm.rps.min_freq_softlimit)); 405 } 406 407 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 408 struct device_attribute *attr, 409 const char *buf, size_t count) 410 { 411 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 412 struct intel_rps *rps = &dev_priv->gt_pm.rps; 413 intel_wakeref_t wakeref; 414 u32 val; 415 ssize_t ret; 416 417 ret = kstrtou32(buf, 0, &val); 418 if (ret) 419 return ret; 420 421 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 422 mutex_lock(&rps->lock); 423 424 val = intel_freq_opcode(dev_priv, val); 425 if (val < rps->min_freq || 426 val > rps->max_freq || 427 val > rps->max_freq_softlimit) { 428 ret = -EINVAL; 429 goto unlock; 430 } 431 432 rps->min_freq_softlimit = val; 433 434 val = clamp_t(int, rps->cur_freq, 435 rps->min_freq_softlimit, 436 rps->max_freq_softlimit); 437 438 /* We still need *_set_rps to process the new min_delay and 439 * update the interrupt limits and PMINTRMSK even though 440 * frequency request may be unchanged. */ 441 ret = intel_set_rps(dev_priv, val); 442 443 unlock: 444 mutex_unlock(&rps->lock); 445 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 446 447 return ret ?: count; 448 } 449 450 static DEVICE_ATTR_RO(gt_act_freq_mhz); 451 static DEVICE_ATTR_RO(gt_cur_freq_mhz); 452 static DEVICE_ATTR_RW(gt_boost_freq_mhz); 453 static DEVICE_ATTR_RW(gt_max_freq_mhz); 454 static DEVICE_ATTR_RW(gt_min_freq_mhz); 455 456 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz); 457 458 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 459 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 460 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 461 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 462 463 /* For now we have a static number of RP states */ 464 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 465 { 466 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 467 struct intel_rps *rps = &dev_priv->gt_pm.rps; 468 u32 val; 469 470 if (attr == &dev_attr_gt_RP0_freq_mhz) 471 val = intel_gpu_freq(dev_priv, rps->rp0_freq); 472 else if (attr == &dev_attr_gt_RP1_freq_mhz) 473 val = intel_gpu_freq(dev_priv, rps->rp1_freq); 474 else if (attr == &dev_attr_gt_RPn_freq_mhz) 475 val = intel_gpu_freq(dev_priv, rps->min_freq); 476 else 477 BUG(); 478 479 return snprintf(buf, PAGE_SIZE, "%d\n", val); 480 } 481 482 static const struct attribute * const gen6_attrs[] = { 483 &dev_attr_gt_act_freq_mhz.attr, 484 &dev_attr_gt_cur_freq_mhz.attr, 485 &dev_attr_gt_boost_freq_mhz.attr, 486 &dev_attr_gt_max_freq_mhz.attr, 487 &dev_attr_gt_min_freq_mhz.attr, 488 &dev_attr_gt_RP0_freq_mhz.attr, 489 &dev_attr_gt_RP1_freq_mhz.attr, 490 &dev_attr_gt_RPn_freq_mhz.attr, 491 NULL, 492 }; 493 494 static const struct attribute * const vlv_attrs[] = { 495 &dev_attr_gt_act_freq_mhz.attr, 496 &dev_attr_gt_cur_freq_mhz.attr, 497 &dev_attr_gt_boost_freq_mhz.attr, 498 &dev_attr_gt_max_freq_mhz.attr, 499 &dev_attr_gt_min_freq_mhz.attr, 500 &dev_attr_gt_RP0_freq_mhz.attr, 501 &dev_attr_gt_RP1_freq_mhz.attr, 502 &dev_attr_gt_RPn_freq_mhz.attr, 503 &dev_attr_vlv_rpe_freq_mhz.attr, 504 NULL, 505 }; 506 507 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 508 509 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 510 struct bin_attribute *attr, char *buf, 511 loff_t off, size_t count) 512 { 513 514 struct device *kdev = kobj_to_dev(kobj); 515 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 516 struct i915_gpu_state *gpu; 517 ssize_t ret; 518 519 gpu = i915_first_error_state(i915); 520 if (IS_ERR(gpu)) { 521 ret = PTR_ERR(gpu); 522 } else if (gpu) { 523 ret = i915_gpu_state_copy_to_buffer(gpu, buf, off, count); 524 i915_gpu_state_put(gpu); 525 } else { 526 const char *str = "No error state collected\n"; 527 size_t len = strlen(str); 528 529 ret = min_t(size_t, count, len - off); 530 memcpy(buf, str + off, ret); 531 } 532 533 return ret; 534 } 535 536 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 537 struct bin_attribute *attr, char *buf, 538 loff_t off, size_t count) 539 { 540 struct device *kdev = kobj_to_dev(kobj); 541 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 542 543 DRM_DEBUG_DRIVER("Resetting error state\n"); 544 i915_reset_error_state(dev_priv); 545 546 return count; 547 } 548 549 static const struct bin_attribute error_state_attr = { 550 .attr.name = "error", 551 .attr.mode = S_IRUSR | S_IWUSR, 552 .size = 0, 553 .read = error_state_read, 554 .write = error_state_write, 555 }; 556 557 static void i915_setup_error_capture(struct device *kdev) 558 { 559 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 560 DRM_ERROR("error_state sysfs setup failed\n"); 561 } 562 563 static void i915_teardown_error_capture(struct device *kdev) 564 { 565 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 566 } 567 #else 568 static void i915_setup_error_capture(struct device *kdev) {} 569 static void i915_teardown_error_capture(struct device *kdev) {} 570 #endif 571 572 void i915_setup_sysfs(struct drm_i915_private *dev_priv) 573 { 574 struct device *kdev = dev_priv->drm.primary->kdev; 575 int ret; 576 577 #ifdef CONFIG_PM 578 if (HAS_RC6(dev_priv)) { 579 ret = sysfs_merge_group(&kdev->kobj, 580 &rc6_attr_group); 581 if (ret) 582 DRM_ERROR("RC6 residency sysfs setup failed\n"); 583 } 584 if (HAS_RC6p(dev_priv)) { 585 ret = sysfs_merge_group(&kdev->kobj, 586 &rc6p_attr_group); 587 if (ret) 588 DRM_ERROR("RC6p residency sysfs setup failed\n"); 589 } 590 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 591 ret = sysfs_merge_group(&kdev->kobj, 592 &media_rc6_attr_group); 593 if (ret) 594 DRM_ERROR("Media RC6 residency sysfs setup failed\n"); 595 } 596 #endif 597 if (HAS_L3_DPF(dev_priv)) { 598 ret = device_create_bin_file(kdev, &dpf_attrs); 599 if (ret) 600 DRM_ERROR("l3 parity sysfs setup failed\n"); 601 602 if (NUM_L3_SLICES(dev_priv) > 1) { 603 ret = device_create_bin_file(kdev, 604 &dpf_attrs_1); 605 if (ret) 606 DRM_ERROR("l3 parity slice 1 setup failed\n"); 607 } 608 } 609 610 ret = 0; 611 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 612 ret = sysfs_create_files(&kdev->kobj, vlv_attrs); 613 else if (INTEL_GEN(dev_priv) >= 6) 614 ret = sysfs_create_files(&kdev->kobj, gen6_attrs); 615 if (ret) 616 DRM_ERROR("RPS sysfs setup failed\n"); 617 618 i915_setup_error_capture(kdev); 619 } 620 621 void i915_teardown_sysfs(struct drm_i915_private *dev_priv) 622 { 623 struct device *kdev = dev_priv->drm.primary->kdev; 624 625 i915_teardown_error_capture(kdev); 626 627 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 628 sysfs_remove_files(&kdev->kobj, vlv_attrs); 629 else 630 sysfs_remove_files(&kdev->kobj, gen6_attrs); 631 device_remove_bin_file(kdev, &dpf_attrs_1); 632 device_remove_bin_file(kdev, &dpf_attrs); 633 #ifdef CONFIG_PM 634 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group); 635 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group); 636 #endif 637 } 638