1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <linux/device.h> 29 #include <linux/module.h> 30 #include <linux/stat.h> 31 #include <linux/sysfs.h> 32 #include "intel_drv.h" 33 #include "i915_drv.h" 34 35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) 36 { 37 struct drm_minor *minor = dev_get_drvdata(kdev); 38 return to_i915(minor->dev); 39 } 40 41 #ifdef CONFIG_PM 42 static u32 calc_residency(struct drm_i915_private *dev_priv, 43 i915_reg_t reg) 44 { 45 return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg), 46 1000); 47 } 48 49 static ssize_t 50 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) 51 { 52 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6()); 53 } 54 55 static ssize_t 56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 57 { 58 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 59 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); 60 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 61 } 62 63 static ssize_t 64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) 65 { 66 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 67 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); 68 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 69 } 70 71 static ssize_t 72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) 73 { 74 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 75 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); 76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 77 } 78 79 static ssize_t 80 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) 81 { 82 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 83 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); 84 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); 85 } 86 87 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); 88 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL); 89 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL); 90 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL); 91 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL); 92 93 static struct attribute *rc6_attrs[] = { 94 &dev_attr_rc6_enable.attr, 95 &dev_attr_rc6_residency_ms.attr, 96 NULL 97 }; 98 99 static const struct attribute_group rc6_attr_group = { 100 .name = power_group_name, 101 .attrs = rc6_attrs 102 }; 103 104 static struct attribute *rc6p_attrs[] = { 105 &dev_attr_rc6p_residency_ms.attr, 106 &dev_attr_rc6pp_residency_ms.attr, 107 NULL 108 }; 109 110 static const struct attribute_group rc6p_attr_group = { 111 .name = power_group_name, 112 .attrs = rc6p_attrs 113 }; 114 115 static struct attribute *media_rc6_attrs[] = { 116 &dev_attr_media_rc6_residency_ms.attr, 117 NULL 118 }; 119 120 static const struct attribute_group media_rc6_attr_group = { 121 .name = power_group_name, 122 .attrs = media_rc6_attrs 123 }; 124 #endif 125 126 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset) 127 { 128 if (!HAS_L3_DPF(dev_priv)) 129 return -EPERM; 130 131 if (offset % 4 != 0) 132 return -EINVAL; 133 134 if (offset >= GEN7_L3LOG_SIZE) 135 return -ENXIO; 136 137 return 0; 138 } 139 140 static ssize_t 141 i915_l3_read(struct file *filp, struct kobject *kobj, 142 struct bin_attribute *attr, char *buf, 143 loff_t offset, size_t count) 144 { 145 struct device *kdev = kobj_to_dev(kobj); 146 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 147 struct drm_device *dev = &dev_priv->drm; 148 int slice = (int)(uintptr_t)attr->private; 149 int ret; 150 151 count = round_down(count, 4); 152 153 ret = l3_access_valid(dev_priv, offset); 154 if (ret) 155 return ret; 156 157 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 158 159 ret = i915_mutex_lock_interruptible(dev); 160 if (ret) 161 return ret; 162 163 if (dev_priv->l3_parity.remap_info[slice]) 164 memcpy(buf, 165 dev_priv->l3_parity.remap_info[slice] + (offset/4), 166 count); 167 else 168 memset(buf, 0, count); 169 170 mutex_unlock(&dev->struct_mutex); 171 172 return count; 173 } 174 175 static ssize_t 176 i915_l3_write(struct file *filp, struct kobject *kobj, 177 struct bin_attribute *attr, char *buf, 178 loff_t offset, size_t count) 179 { 180 struct device *kdev = kobj_to_dev(kobj); 181 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 182 struct drm_device *dev = &dev_priv->drm; 183 struct i915_gem_context *ctx; 184 int slice = (int)(uintptr_t)attr->private; 185 u32 **remap_info; 186 int ret; 187 188 ret = l3_access_valid(dev_priv, offset); 189 if (ret) 190 return ret; 191 192 ret = i915_mutex_lock_interruptible(dev); 193 if (ret) 194 return ret; 195 196 remap_info = &dev_priv->l3_parity.remap_info[slice]; 197 if (!*remap_info) { 198 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 199 if (!*remap_info) { 200 ret = -ENOMEM; 201 goto out; 202 } 203 } 204 205 /* TODO: Ideally we really want a GPU reset here to make sure errors 206 * aren't propagated. Since I cannot find a stable way to reset the GPU 207 * at this point it is left as a TODO. 208 */ 209 memcpy(*remap_info + (offset/4), buf, count); 210 211 /* NB: We defer the remapping until we switch to the context */ 212 list_for_each_entry(ctx, &dev_priv->contexts.list, link) 213 ctx->remap_slice |= (1<<slice); 214 215 ret = count; 216 217 out: 218 mutex_unlock(&dev->struct_mutex); 219 220 return ret; 221 } 222 223 static const struct bin_attribute dpf_attrs = { 224 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 225 .size = GEN7_L3LOG_SIZE, 226 .read = i915_l3_read, 227 .write = i915_l3_write, 228 .mmap = NULL, 229 .private = (void *)0 230 }; 231 232 static const struct bin_attribute dpf_attrs_1 = { 233 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 234 .size = GEN7_L3LOG_SIZE, 235 .read = i915_l3_read, 236 .write = i915_l3_write, 237 .mmap = NULL, 238 .private = (void *)1 239 }; 240 241 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 242 struct device_attribute *attr, char *buf) 243 { 244 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 245 int ret; 246 247 intel_runtime_pm_get(dev_priv); 248 249 mutex_lock(&dev_priv->rps.hw_lock); 250 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 251 u32 freq; 252 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 253 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff); 254 } else { 255 u32 rpstat = I915_READ(GEN6_RPSTAT1); 256 if (INTEL_GEN(dev_priv) >= 9) 257 ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 258 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 259 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 260 else 261 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 262 ret = intel_gpu_freq(dev_priv, ret); 263 } 264 mutex_unlock(&dev_priv->rps.hw_lock); 265 266 intel_runtime_pm_put(dev_priv); 267 268 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 269 } 270 271 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 272 struct device_attribute *attr, char *buf) 273 { 274 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 275 276 return snprintf(buf, PAGE_SIZE, "%d\n", 277 intel_gpu_freq(dev_priv, 278 dev_priv->rps.cur_freq)); 279 } 280 281 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 282 { 283 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 284 285 return snprintf(buf, PAGE_SIZE, "%d\n", 286 intel_gpu_freq(dev_priv, 287 dev_priv->rps.boost_freq)); 288 } 289 290 static ssize_t gt_boost_freq_mhz_store(struct device *kdev, 291 struct device_attribute *attr, 292 const char *buf, size_t count) 293 { 294 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 295 u32 val; 296 ssize_t ret; 297 298 ret = kstrtou32(buf, 0, &val); 299 if (ret) 300 return ret; 301 302 /* Validate against (static) hardware limits */ 303 val = intel_freq_opcode(dev_priv, val); 304 if (val < dev_priv->rps.min_freq || val > dev_priv->rps.max_freq) 305 return -EINVAL; 306 307 mutex_lock(&dev_priv->rps.hw_lock); 308 dev_priv->rps.boost_freq = val; 309 mutex_unlock(&dev_priv->rps.hw_lock); 310 311 return count; 312 } 313 314 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 315 struct device_attribute *attr, char *buf) 316 { 317 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 318 319 return snprintf(buf, PAGE_SIZE, "%d\n", 320 intel_gpu_freq(dev_priv, 321 dev_priv->rps.efficient_freq)); 322 } 323 324 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 325 { 326 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 327 328 return snprintf(buf, PAGE_SIZE, "%d\n", 329 intel_gpu_freq(dev_priv, 330 dev_priv->rps.max_freq_softlimit)); 331 } 332 333 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 334 struct device_attribute *attr, 335 const char *buf, size_t count) 336 { 337 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 338 u32 val; 339 ssize_t ret; 340 341 ret = kstrtou32(buf, 0, &val); 342 if (ret) 343 return ret; 344 345 intel_runtime_pm_get(dev_priv); 346 347 mutex_lock(&dev_priv->rps.hw_lock); 348 349 val = intel_freq_opcode(dev_priv, val); 350 351 if (val < dev_priv->rps.min_freq || 352 val > dev_priv->rps.max_freq || 353 val < dev_priv->rps.min_freq_softlimit) { 354 mutex_unlock(&dev_priv->rps.hw_lock); 355 intel_runtime_pm_put(dev_priv); 356 return -EINVAL; 357 } 358 359 if (val > dev_priv->rps.rp0_freq) 360 DRM_DEBUG("User requested overclocking to %d\n", 361 intel_gpu_freq(dev_priv, val)); 362 363 dev_priv->rps.max_freq_softlimit = val; 364 365 val = clamp_t(int, dev_priv->rps.cur_freq, 366 dev_priv->rps.min_freq_softlimit, 367 dev_priv->rps.max_freq_softlimit); 368 369 /* We still need *_set_rps to process the new max_delay and 370 * update the interrupt limits and PMINTRMSK even though 371 * frequency request may be unchanged. */ 372 ret = intel_set_rps(dev_priv, val); 373 374 mutex_unlock(&dev_priv->rps.hw_lock); 375 376 intel_runtime_pm_put(dev_priv); 377 378 return ret ?: count; 379 } 380 381 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 382 { 383 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 384 385 return snprintf(buf, PAGE_SIZE, "%d\n", 386 intel_gpu_freq(dev_priv, 387 dev_priv->rps.min_freq_softlimit)); 388 } 389 390 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 391 struct device_attribute *attr, 392 const char *buf, size_t count) 393 { 394 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 395 u32 val; 396 ssize_t ret; 397 398 ret = kstrtou32(buf, 0, &val); 399 if (ret) 400 return ret; 401 402 intel_runtime_pm_get(dev_priv); 403 404 mutex_lock(&dev_priv->rps.hw_lock); 405 406 val = intel_freq_opcode(dev_priv, val); 407 408 if (val < dev_priv->rps.min_freq || 409 val > dev_priv->rps.max_freq || 410 val > dev_priv->rps.max_freq_softlimit) { 411 mutex_unlock(&dev_priv->rps.hw_lock); 412 intel_runtime_pm_put(dev_priv); 413 return -EINVAL; 414 } 415 416 dev_priv->rps.min_freq_softlimit = val; 417 418 val = clamp_t(int, dev_priv->rps.cur_freq, 419 dev_priv->rps.min_freq_softlimit, 420 dev_priv->rps.max_freq_softlimit); 421 422 /* We still need *_set_rps to process the new min_delay and 423 * update the interrupt limits and PMINTRMSK even though 424 * frequency request may be unchanged. */ 425 ret = intel_set_rps(dev_priv, val); 426 427 mutex_unlock(&dev_priv->rps.hw_lock); 428 429 intel_runtime_pm_put(dev_priv); 430 431 return ret ?: count; 432 } 433 434 static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); 435 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 436 static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO | S_IWUSR, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store); 437 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 438 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 439 440 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL); 441 442 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 443 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 444 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 445 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 446 447 /* For now we have a static number of RP states */ 448 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 449 { 450 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 451 u32 val; 452 453 if (attr == &dev_attr_gt_RP0_freq_mhz) 454 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); 455 else if (attr == &dev_attr_gt_RP1_freq_mhz) 456 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); 457 else if (attr == &dev_attr_gt_RPn_freq_mhz) 458 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq); 459 else 460 BUG(); 461 462 return snprintf(buf, PAGE_SIZE, "%d\n", val); 463 } 464 465 static const struct attribute *gen6_attrs[] = { 466 &dev_attr_gt_act_freq_mhz.attr, 467 &dev_attr_gt_cur_freq_mhz.attr, 468 &dev_attr_gt_boost_freq_mhz.attr, 469 &dev_attr_gt_max_freq_mhz.attr, 470 &dev_attr_gt_min_freq_mhz.attr, 471 &dev_attr_gt_RP0_freq_mhz.attr, 472 &dev_attr_gt_RP1_freq_mhz.attr, 473 &dev_attr_gt_RPn_freq_mhz.attr, 474 NULL, 475 }; 476 477 static const struct attribute *vlv_attrs[] = { 478 &dev_attr_gt_act_freq_mhz.attr, 479 &dev_attr_gt_cur_freq_mhz.attr, 480 &dev_attr_gt_boost_freq_mhz.attr, 481 &dev_attr_gt_max_freq_mhz.attr, 482 &dev_attr_gt_min_freq_mhz.attr, 483 &dev_attr_gt_RP0_freq_mhz.attr, 484 &dev_attr_gt_RP1_freq_mhz.attr, 485 &dev_attr_gt_RPn_freq_mhz.attr, 486 &dev_attr_vlv_rpe_freq_mhz.attr, 487 NULL, 488 }; 489 490 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 491 492 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 493 struct bin_attribute *attr, char *buf, 494 loff_t off, size_t count) 495 { 496 497 struct device *kdev = kobj_to_dev(kobj); 498 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 499 struct drm_i915_error_state_buf error_str; 500 struct i915_gpu_state *gpu; 501 ssize_t ret; 502 503 ret = i915_error_state_buf_init(&error_str, dev_priv, count, off); 504 if (ret) 505 return ret; 506 507 gpu = i915_first_error_state(dev_priv); 508 ret = i915_error_state_to_str(&error_str, gpu); 509 if (ret) 510 goto out; 511 512 ret = count < error_str.bytes ? count : error_str.bytes; 513 memcpy(buf, error_str.buf, ret); 514 515 out: 516 i915_gpu_state_put(gpu); 517 i915_error_state_buf_release(&error_str); 518 519 return ret; 520 } 521 522 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 523 struct bin_attribute *attr, char *buf, 524 loff_t off, size_t count) 525 { 526 struct device *kdev = kobj_to_dev(kobj); 527 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 528 529 DRM_DEBUG_DRIVER("Resetting error state\n"); 530 i915_reset_error_state(dev_priv); 531 532 return count; 533 } 534 535 static const struct bin_attribute error_state_attr = { 536 .attr.name = "error", 537 .attr.mode = S_IRUSR | S_IWUSR, 538 .size = 0, 539 .read = error_state_read, 540 .write = error_state_write, 541 }; 542 543 static void i915_setup_error_capture(struct device *kdev) 544 { 545 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 546 DRM_ERROR("error_state sysfs setup failed\n"); 547 } 548 549 static void i915_teardown_error_capture(struct device *kdev) 550 { 551 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 552 } 553 #else 554 static void i915_setup_error_capture(struct device *kdev) {} 555 static void i915_teardown_error_capture(struct device *kdev) {} 556 #endif 557 558 void i915_setup_sysfs(struct drm_i915_private *dev_priv) 559 { 560 struct device *kdev = dev_priv->drm.primary->kdev; 561 int ret; 562 563 #ifdef CONFIG_PM 564 if (HAS_RC6(dev_priv)) { 565 ret = sysfs_merge_group(&kdev->kobj, 566 &rc6_attr_group); 567 if (ret) 568 DRM_ERROR("RC6 residency sysfs setup failed\n"); 569 } 570 if (HAS_RC6p(dev_priv)) { 571 ret = sysfs_merge_group(&kdev->kobj, 572 &rc6p_attr_group); 573 if (ret) 574 DRM_ERROR("RC6p residency sysfs setup failed\n"); 575 } 576 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 577 ret = sysfs_merge_group(&kdev->kobj, 578 &media_rc6_attr_group); 579 if (ret) 580 DRM_ERROR("Media RC6 residency sysfs setup failed\n"); 581 } 582 #endif 583 if (HAS_L3_DPF(dev_priv)) { 584 ret = device_create_bin_file(kdev, &dpf_attrs); 585 if (ret) 586 DRM_ERROR("l3 parity sysfs setup failed\n"); 587 588 if (NUM_L3_SLICES(dev_priv) > 1) { 589 ret = device_create_bin_file(kdev, 590 &dpf_attrs_1); 591 if (ret) 592 DRM_ERROR("l3 parity slice 1 setup failed\n"); 593 } 594 } 595 596 ret = 0; 597 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 598 ret = sysfs_create_files(&kdev->kobj, vlv_attrs); 599 else if (INTEL_GEN(dev_priv) >= 6) 600 ret = sysfs_create_files(&kdev->kobj, gen6_attrs); 601 if (ret) 602 DRM_ERROR("RPS sysfs setup failed\n"); 603 604 i915_setup_error_capture(kdev); 605 } 606 607 void i915_teardown_sysfs(struct drm_i915_private *dev_priv) 608 { 609 struct device *kdev = dev_priv->drm.primary->kdev; 610 611 i915_teardown_error_capture(kdev); 612 613 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 614 sysfs_remove_files(&kdev->kobj, vlv_attrs); 615 else 616 sysfs_remove_files(&kdev->kobj, gen6_attrs); 617 device_remove_bin_file(kdev, &dpf_attrs_1); 618 device_remove_bin_file(kdev, &dpf_attrs); 619 #ifdef CONFIG_PM 620 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group); 621 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group); 622 #endif 623 } 624