1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28 #include <linux/device.h> 29 #include <linux/module.h> 30 #include <linux/stat.h> 31 #include <linux/sysfs.h> 32 33 #include "gt/intel_rc6.h" 34 #include "gt/intel_rps.h" 35 #include "gt/sysfs_engines.h" 36 37 #include "i915_drv.h" 38 #include "i915_sysfs.h" 39 #include "intel_pm.h" 40 #include "intel_sideband.h" 41 42 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev) 43 { 44 struct drm_minor *minor = dev_get_drvdata(kdev); 45 return to_i915(minor->dev); 46 } 47 48 #ifdef CONFIG_PM 49 static u32 calc_residency(struct drm_i915_private *dev_priv, 50 i915_reg_t reg) 51 { 52 intel_wakeref_t wakeref; 53 u64 res = 0; 54 55 with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) 56 res = intel_rc6_residency_us(&dev_priv->gt.rc6, reg); 57 58 return DIV_ROUND_CLOSEST_ULL(res, 1000); 59 } 60 61 static ssize_t rc6_enable_show(struct device *kdev, 62 struct device_attribute *attr, char *buf) 63 { 64 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 65 unsigned int mask; 66 67 mask = 0; 68 if (HAS_RC6(dev_priv)) 69 mask |= BIT(0); 70 if (HAS_RC6p(dev_priv)) 71 mask |= BIT(1); 72 if (HAS_RC6pp(dev_priv)) 73 mask |= BIT(2); 74 75 return sysfs_emit(buf, "%x\n", mask); 76 } 77 78 static ssize_t rc6_residency_ms_show(struct device *kdev, 79 struct device_attribute *attr, char *buf) 80 { 81 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 82 u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); 83 return sysfs_emit(buf, "%u\n", rc6_residency); 84 } 85 86 static ssize_t rc6p_residency_ms_show(struct device *kdev, 87 struct device_attribute *attr, char *buf) 88 { 89 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 90 u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); 91 return sysfs_emit(buf, "%u\n", rc6p_residency); 92 } 93 94 static ssize_t rc6pp_residency_ms_show(struct device *kdev, 95 struct device_attribute *attr, char *buf) 96 { 97 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 98 u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); 99 return sysfs_emit(buf, "%u\n", rc6pp_residency); 100 } 101 102 static ssize_t media_rc6_residency_ms_show(struct device *kdev, 103 struct device_attribute *attr, char *buf) 104 { 105 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 106 u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); 107 return sysfs_emit(buf, "%u\n", rc6_residency); 108 } 109 110 static DEVICE_ATTR_RO(rc6_enable); 111 static DEVICE_ATTR_RO(rc6_residency_ms); 112 static DEVICE_ATTR_RO(rc6p_residency_ms); 113 static DEVICE_ATTR_RO(rc6pp_residency_ms); 114 static DEVICE_ATTR_RO(media_rc6_residency_ms); 115 116 static struct attribute *rc6_attrs[] = { 117 &dev_attr_rc6_enable.attr, 118 &dev_attr_rc6_residency_ms.attr, 119 NULL 120 }; 121 122 static const struct attribute_group rc6_attr_group = { 123 .name = power_group_name, 124 .attrs = rc6_attrs 125 }; 126 127 static struct attribute *rc6p_attrs[] = { 128 &dev_attr_rc6p_residency_ms.attr, 129 &dev_attr_rc6pp_residency_ms.attr, 130 NULL 131 }; 132 133 static const struct attribute_group rc6p_attr_group = { 134 .name = power_group_name, 135 .attrs = rc6p_attrs 136 }; 137 138 static struct attribute *media_rc6_attrs[] = { 139 &dev_attr_media_rc6_residency_ms.attr, 140 NULL 141 }; 142 143 static const struct attribute_group media_rc6_attr_group = { 144 .name = power_group_name, 145 .attrs = media_rc6_attrs 146 }; 147 #endif 148 149 static int l3_access_valid(struct drm_i915_private *i915, loff_t offset) 150 { 151 if (!HAS_L3_DPF(i915)) 152 return -EPERM; 153 154 if (!IS_ALIGNED(offset, sizeof(u32))) 155 return -EINVAL; 156 157 if (offset >= GEN7_L3LOG_SIZE) 158 return -ENXIO; 159 160 return 0; 161 } 162 163 static ssize_t 164 i915_l3_read(struct file *filp, struct kobject *kobj, 165 struct bin_attribute *attr, char *buf, 166 loff_t offset, size_t count) 167 { 168 struct device *kdev = kobj_to_dev(kobj); 169 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 170 int slice = (int)(uintptr_t)attr->private; 171 int ret; 172 173 ret = l3_access_valid(i915, offset); 174 if (ret) 175 return ret; 176 177 count = round_down(count, sizeof(u32)); 178 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count); 179 memset(buf, 0, count); 180 181 spin_lock(&i915->gem.contexts.lock); 182 if (i915->l3_parity.remap_info[slice]) 183 memcpy(buf, 184 i915->l3_parity.remap_info[slice] + offset / sizeof(u32), 185 count); 186 spin_unlock(&i915->gem.contexts.lock); 187 188 return count; 189 } 190 191 static ssize_t 192 i915_l3_write(struct file *filp, struct kobject *kobj, 193 struct bin_attribute *attr, char *buf, 194 loff_t offset, size_t count) 195 { 196 struct device *kdev = kobj_to_dev(kobj); 197 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 198 int slice = (int)(uintptr_t)attr->private; 199 u32 *remap_info, *freeme = NULL; 200 struct i915_gem_context *ctx; 201 int ret; 202 203 ret = l3_access_valid(i915, offset); 204 if (ret) 205 return ret; 206 207 if (count < sizeof(u32)) 208 return -EINVAL; 209 210 remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL); 211 if (!remap_info) 212 return -ENOMEM; 213 214 spin_lock(&i915->gem.contexts.lock); 215 216 if (i915->l3_parity.remap_info[slice]) { 217 freeme = remap_info; 218 remap_info = i915->l3_parity.remap_info[slice]; 219 } else { 220 i915->l3_parity.remap_info[slice] = remap_info; 221 } 222 223 count = round_down(count, sizeof(u32)); 224 memcpy(remap_info + offset / sizeof(u32), buf, count); 225 226 /* NB: We defer the remapping until we switch to the context */ 227 list_for_each_entry(ctx, &i915->gem.contexts.list, link) 228 ctx->remap_slice |= BIT(slice); 229 230 spin_unlock(&i915->gem.contexts.lock); 231 kfree(freeme); 232 233 /* 234 * TODO: Ideally we really want a GPU reset here to make sure errors 235 * aren't propagated. Since I cannot find a stable way to reset the GPU 236 * at this point it is left as a TODO. 237 */ 238 239 return count; 240 } 241 242 static const struct bin_attribute dpf_attrs = { 243 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, 244 .size = GEN7_L3LOG_SIZE, 245 .read = i915_l3_read, 246 .write = i915_l3_write, 247 .mmap = NULL, 248 .private = (void *)0 249 }; 250 251 static const struct bin_attribute dpf_attrs_1 = { 252 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, 253 .size = GEN7_L3LOG_SIZE, 254 .read = i915_l3_read, 255 .write = i915_l3_write, 256 .mmap = NULL, 257 .private = (void *)1 258 }; 259 260 static ssize_t gt_act_freq_mhz_show(struct device *kdev, 261 struct device_attribute *attr, char *buf) 262 { 263 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 264 struct intel_rps *rps = &i915->gt.rps; 265 266 return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps)); 267 } 268 269 static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 270 struct device_attribute *attr, char *buf) 271 { 272 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 273 struct intel_rps *rps = &i915->gt.rps; 274 275 return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps)); 276 } 277 278 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 279 { 280 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 281 struct intel_rps *rps = &i915->gt.rps; 282 283 return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->boost_freq)); 284 } 285 286 static ssize_t gt_boost_freq_mhz_store(struct device *kdev, 287 struct device_attribute *attr, 288 const char *buf, size_t count) 289 { 290 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 291 struct intel_rps *rps = &dev_priv->gt.rps; 292 bool boost = false; 293 ssize_t ret; 294 u32 val; 295 296 ret = kstrtou32(buf, 0, &val); 297 if (ret) 298 return ret; 299 300 /* Validate against (static) hardware limits */ 301 val = intel_freq_opcode(rps, val); 302 if (val < rps->min_freq || val > rps->max_freq) 303 return -EINVAL; 304 305 mutex_lock(&rps->lock); 306 if (val != rps->boost_freq) { 307 rps->boost_freq = val; 308 boost = atomic_read(&rps->num_waiters); 309 } 310 mutex_unlock(&rps->lock); 311 if (boost) 312 schedule_work(&rps->work); 313 314 return count; 315 } 316 317 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 318 struct device_attribute *attr, char *buf) 319 { 320 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 321 struct intel_rps *rps = &dev_priv->gt.rps; 322 323 return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq)); 324 } 325 326 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 327 { 328 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 329 struct intel_gt *gt = &dev_priv->gt; 330 struct intel_rps *rps = >->rps; 331 332 return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps)); 333 } 334 335 static ssize_t gt_max_freq_mhz_store(struct device *kdev, 336 struct device_attribute *attr, 337 const char *buf, size_t count) 338 { 339 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 340 struct intel_gt *gt = &dev_priv->gt; 341 struct intel_rps *rps = >->rps; 342 ssize_t ret; 343 u32 val; 344 345 ret = kstrtou32(buf, 0, &val); 346 if (ret) 347 return ret; 348 349 ret = intel_rps_set_max_frequency(rps, val); 350 351 return ret ?: count; 352 } 353 354 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 355 { 356 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 357 struct intel_gt *gt = &i915->gt; 358 struct intel_rps *rps = >->rps; 359 360 return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps)); 361 } 362 363 static ssize_t gt_min_freq_mhz_store(struct device *kdev, 364 struct device_attribute *attr, 365 const char *buf, size_t count) 366 { 367 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 368 struct intel_rps *rps = &i915->gt.rps; 369 ssize_t ret; 370 u32 val; 371 372 ret = kstrtou32(buf, 0, &val); 373 if (ret) 374 return ret; 375 376 ret = intel_rps_set_min_frequency(rps, val); 377 378 return ret ?: count; 379 } 380 381 static DEVICE_ATTR_RO(gt_act_freq_mhz); 382 static DEVICE_ATTR_RO(gt_cur_freq_mhz); 383 static DEVICE_ATTR_RW(gt_boost_freq_mhz); 384 static DEVICE_ATTR_RW(gt_max_freq_mhz); 385 static DEVICE_ATTR_RW(gt_min_freq_mhz); 386 387 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz); 388 389 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf); 390 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 391 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 392 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL); 393 394 /* For now we have a static number of RP states */ 395 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 396 { 397 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 398 struct intel_rps *rps = &dev_priv->gt.rps; 399 u32 val; 400 401 if (attr == &dev_attr_gt_RP0_freq_mhz) 402 val = intel_rps_get_rp0_frequency(rps); 403 else if (attr == &dev_attr_gt_RP1_freq_mhz) 404 val = intel_rps_get_rp1_frequency(rps); 405 else if (attr == &dev_attr_gt_RPn_freq_mhz) 406 val = intel_rps_get_rpn_frequency(rps); 407 else 408 BUG(); 409 410 return sysfs_emit(buf, "%d\n", val); 411 } 412 413 static const struct attribute * const gen6_attrs[] = { 414 &dev_attr_gt_act_freq_mhz.attr, 415 &dev_attr_gt_cur_freq_mhz.attr, 416 &dev_attr_gt_boost_freq_mhz.attr, 417 &dev_attr_gt_max_freq_mhz.attr, 418 &dev_attr_gt_min_freq_mhz.attr, 419 &dev_attr_gt_RP0_freq_mhz.attr, 420 &dev_attr_gt_RP1_freq_mhz.attr, 421 &dev_attr_gt_RPn_freq_mhz.attr, 422 NULL, 423 }; 424 425 static const struct attribute * const vlv_attrs[] = { 426 &dev_attr_gt_act_freq_mhz.attr, 427 &dev_attr_gt_cur_freq_mhz.attr, 428 &dev_attr_gt_boost_freq_mhz.attr, 429 &dev_attr_gt_max_freq_mhz.attr, 430 &dev_attr_gt_min_freq_mhz.attr, 431 &dev_attr_gt_RP0_freq_mhz.attr, 432 &dev_attr_gt_RP1_freq_mhz.attr, 433 &dev_attr_gt_RPn_freq_mhz.attr, 434 &dev_attr_vlv_rpe_freq_mhz.attr, 435 NULL, 436 }; 437 438 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 439 440 static ssize_t error_state_read(struct file *filp, struct kobject *kobj, 441 struct bin_attribute *attr, char *buf, 442 loff_t off, size_t count) 443 { 444 445 struct device *kdev = kobj_to_dev(kobj); 446 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); 447 struct i915_gpu_coredump *gpu; 448 ssize_t ret; 449 450 gpu = i915_first_error_state(i915); 451 if (IS_ERR(gpu)) { 452 ret = PTR_ERR(gpu); 453 } else if (gpu) { 454 ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count); 455 i915_gpu_coredump_put(gpu); 456 } else { 457 const char *str = "No error state collected\n"; 458 size_t len = strlen(str); 459 460 ret = min_t(size_t, count, len - off); 461 memcpy(buf, str + off, ret); 462 } 463 464 return ret; 465 } 466 467 static ssize_t error_state_write(struct file *file, struct kobject *kobj, 468 struct bin_attribute *attr, char *buf, 469 loff_t off, size_t count) 470 { 471 struct device *kdev = kobj_to_dev(kobj); 472 struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); 473 474 drm_dbg(&dev_priv->drm, "Resetting error state\n"); 475 i915_reset_error_state(dev_priv); 476 477 return count; 478 } 479 480 static const struct bin_attribute error_state_attr = { 481 .attr.name = "error", 482 .attr.mode = S_IRUSR | S_IWUSR, 483 .size = 0, 484 .read = error_state_read, 485 .write = error_state_write, 486 }; 487 488 static void i915_setup_error_capture(struct device *kdev) 489 { 490 if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr)) 491 DRM_ERROR("error_state sysfs setup failed\n"); 492 } 493 494 static void i915_teardown_error_capture(struct device *kdev) 495 { 496 sysfs_remove_bin_file(&kdev->kobj, &error_state_attr); 497 } 498 #else 499 static void i915_setup_error_capture(struct device *kdev) {} 500 static void i915_teardown_error_capture(struct device *kdev) {} 501 #endif 502 503 void i915_setup_sysfs(struct drm_i915_private *dev_priv) 504 { 505 struct device *kdev = dev_priv->drm.primary->kdev; 506 int ret; 507 508 #ifdef CONFIG_PM 509 if (HAS_RC6(dev_priv)) { 510 ret = sysfs_merge_group(&kdev->kobj, 511 &rc6_attr_group); 512 if (ret) 513 drm_err(&dev_priv->drm, 514 "RC6 residency sysfs setup failed\n"); 515 } 516 if (HAS_RC6p(dev_priv)) { 517 ret = sysfs_merge_group(&kdev->kobj, 518 &rc6p_attr_group); 519 if (ret) 520 drm_err(&dev_priv->drm, 521 "RC6p residency sysfs setup failed\n"); 522 } 523 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 524 ret = sysfs_merge_group(&kdev->kobj, 525 &media_rc6_attr_group); 526 if (ret) 527 drm_err(&dev_priv->drm, 528 "Media RC6 residency sysfs setup failed\n"); 529 } 530 #endif 531 if (HAS_L3_DPF(dev_priv)) { 532 ret = device_create_bin_file(kdev, &dpf_attrs); 533 if (ret) 534 drm_err(&dev_priv->drm, 535 "l3 parity sysfs setup failed\n"); 536 537 if (NUM_L3_SLICES(dev_priv) > 1) { 538 ret = device_create_bin_file(kdev, 539 &dpf_attrs_1); 540 if (ret) 541 drm_err(&dev_priv->drm, 542 "l3 parity slice 1 setup failed\n"); 543 } 544 } 545 546 ret = 0; 547 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 548 ret = sysfs_create_files(&kdev->kobj, vlv_attrs); 549 else if (GRAPHICS_VER(dev_priv) >= 6) 550 ret = sysfs_create_files(&kdev->kobj, gen6_attrs); 551 if (ret) 552 drm_err(&dev_priv->drm, "RPS sysfs setup failed\n"); 553 554 i915_setup_error_capture(kdev); 555 556 intel_engines_add_sysfs(dev_priv); 557 } 558 559 void i915_teardown_sysfs(struct drm_i915_private *dev_priv) 560 { 561 struct device *kdev = dev_priv->drm.primary->kdev; 562 563 i915_teardown_error_capture(kdev); 564 565 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 566 sysfs_remove_files(&kdev->kobj, vlv_attrs); 567 else 568 sysfs_remove_files(&kdev->kobj, gen6_attrs); 569 device_remove_bin_file(kdev, &dpf_attrs_1); 570 device_remove_bin_file(kdev, &dpf_attrs); 571 #ifdef CONFIG_PM 572 sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group); 573 sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group); 574 #endif 575 } 576