1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include <drm/drm_cache.h>
7 #include <linux/string_helpers.h>
8 
9 #include "i915_drv.h"
10 #include "i915_reg.h"
11 #include "intel_guc_slpc.h"
12 #include "intel_mchbar_regs.h"
13 #include "gt/intel_gt.h"
14 #include "gt/intel_gt_regs.h"
15 #include "gt/intel_rps.h"
16 
17 static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
18 {
19 	return container_of(slpc, struct intel_guc, slpc);
20 }
21 
22 static inline struct intel_gt *slpc_to_gt(struct intel_guc_slpc *slpc)
23 {
24 	return guc_to_gt(slpc_to_guc(slpc));
25 }
26 
27 static inline struct drm_i915_private *slpc_to_i915(struct intel_guc_slpc *slpc)
28 {
29 	return slpc_to_gt(slpc)->i915;
30 }
31 
32 static bool __detect_slpc_supported(struct intel_guc *guc)
33 {
34 	/* GuC SLPC is unavailable for pre-Gen12 */
35 	return guc->submission_supported &&
36 		GRAPHICS_VER(guc_to_gt(guc)->i915) >= 12;
37 }
38 
39 static bool __guc_slpc_selected(struct intel_guc *guc)
40 {
41 	if (!intel_guc_slpc_is_supported(guc))
42 		return false;
43 
44 	return guc->submission_selected;
45 }
46 
47 void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
48 {
49 	struct intel_guc *guc = slpc_to_guc(slpc);
50 
51 	slpc->supported = __detect_slpc_supported(guc);
52 	slpc->selected = __guc_slpc_selected(guc);
53 }
54 
55 static void slpc_mem_set_param(struct slpc_shared_data *data,
56 			       u32 id, u32 value)
57 {
58 	GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
59 	/*
60 	 * When the flag bit is set, corresponding value will be read
61 	 * and applied by SLPC.
62 	 */
63 	data->override_params.bits[id >> 5] |= (1 << (id % 32));
64 	data->override_params.values[id] = value;
65 }
66 
67 static void slpc_mem_set_enabled(struct slpc_shared_data *data,
68 				 u8 enable_id, u8 disable_id)
69 {
70 	/*
71 	 * Enabling a param involves setting the enable_id
72 	 * to 1 and disable_id to 0.
73 	 */
74 	slpc_mem_set_param(data, enable_id, 1);
75 	slpc_mem_set_param(data, disable_id, 0);
76 }
77 
78 static void slpc_mem_set_disabled(struct slpc_shared_data *data,
79 				  u8 enable_id, u8 disable_id)
80 {
81 	/*
82 	 * Disabling a param involves setting the enable_id
83 	 * to 0 and disable_id to 1.
84 	 */
85 	slpc_mem_set_param(data, disable_id, 1);
86 	slpc_mem_set_param(data, enable_id, 0);
87 }
88 
89 static u32 slpc_get_state(struct intel_guc_slpc *slpc)
90 {
91 	struct slpc_shared_data *data;
92 
93 	GEM_BUG_ON(!slpc->vma);
94 
95 	drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
96 	data = slpc->vaddr;
97 
98 	return data->header.global_state;
99 }
100 
101 static int guc_action_slpc_set_param_nb(struct intel_guc *guc, u8 id, u32 value)
102 {
103 	u32 request[] = {
104 		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
105 		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
106 		id,
107 		value,
108 	};
109 	int ret;
110 
111 	ret = intel_guc_send_nb(guc, request, ARRAY_SIZE(request), 0);
112 
113 	return ret > 0 ? -EPROTO : ret;
114 }
115 
116 static int slpc_set_param_nb(struct intel_guc_slpc *slpc, u8 id, u32 value)
117 {
118 	struct intel_guc *guc = slpc_to_guc(slpc);
119 
120 	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
121 
122 	return guc_action_slpc_set_param_nb(guc, id, value);
123 }
124 
125 static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
126 {
127 	u32 request[] = {
128 		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
129 		SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2),
130 		id,
131 		value,
132 	};
133 	int ret;
134 
135 	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
136 
137 	return ret > 0 ? -EPROTO : ret;
138 }
139 
140 static int guc_action_slpc_unset_param(struct intel_guc *guc, u8 id)
141 {
142 	u32 request[] = {
143 		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
144 		SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
145 		id,
146 	};
147 
148 	return intel_guc_send(guc, request, ARRAY_SIZE(request));
149 }
150 
151 static bool slpc_is_running(struct intel_guc_slpc *slpc)
152 {
153 	return slpc_get_state(slpc) == SLPC_GLOBAL_STATE_RUNNING;
154 }
155 
156 static int guc_action_slpc_query(struct intel_guc *guc, u32 offset)
157 {
158 	u32 request[] = {
159 		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
160 		SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2),
161 		offset,
162 		0,
163 	};
164 	int ret;
165 
166 	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
167 
168 	return ret > 0 ? -EPROTO : ret;
169 }
170 
171 static int slpc_query_task_state(struct intel_guc_slpc *slpc)
172 {
173 	struct intel_guc *guc = slpc_to_guc(slpc);
174 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
175 	u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
176 	int ret;
177 
178 	ret = guc_action_slpc_query(guc, offset);
179 	if (unlikely(ret))
180 		i915_probe_error(i915, "Failed to query task state (%pe)\n",
181 				 ERR_PTR(ret));
182 
183 	drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
184 
185 	return ret;
186 }
187 
188 static int slpc_set_param(struct intel_guc_slpc *slpc, u8 id, u32 value)
189 {
190 	struct intel_guc *guc = slpc_to_guc(slpc);
191 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
192 	int ret;
193 
194 	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
195 
196 	ret = guc_action_slpc_set_param(guc, id, value);
197 	if (ret)
198 		i915_probe_error(i915, "Failed to set param %d to %u (%pe)\n",
199 				 id, value, ERR_PTR(ret));
200 
201 	return ret;
202 }
203 
204 static int slpc_unset_param(struct intel_guc_slpc *slpc,
205 			    u8 id)
206 {
207 	struct intel_guc *guc = slpc_to_guc(slpc);
208 
209 	GEM_BUG_ON(id >= SLPC_MAX_PARAM);
210 
211 	return guc_action_slpc_unset_param(guc, id);
212 }
213 
214 static int slpc_force_min_freq(struct intel_guc_slpc *slpc, u32 freq)
215 {
216 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
217 	struct intel_guc *guc = slpc_to_guc(slpc);
218 	intel_wakeref_t wakeref;
219 	int ret = 0;
220 
221 	lockdep_assert_held(&slpc->lock);
222 
223 	if (!intel_guc_is_ready(guc))
224 		return -ENODEV;
225 
226 	/*
227 	 * This function is a little different as compared to
228 	 * intel_guc_slpc_set_min_freq(). Softlimit will not be updated
229 	 * here since this is used to temporarily change min freq,
230 	 * for example, during a waitboost. Caller is responsible for
231 	 * checking bounds.
232 	 */
233 
234 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
235 		/* Non-blocking request will avoid stalls */
236 		ret = slpc_set_param_nb(slpc,
237 					SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
238 					freq);
239 		if (ret)
240 			drm_notice(&i915->drm,
241 				   "Failed to send set_param for min freq(%d): (%d)\n",
242 				   freq, ret);
243 	}
244 
245 	return ret;
246 }
247 
248 static void slpc_boost_work(struct work_struct *work)
249 {
250 	struct intel_guc_slpc *slpc = container_of(work, typeof(*slpc), boost_work);
251 	int err;
252 
253 	/*
254 	 * Raise min freq to boost. It's possible that
255 	 * this is greater than current max. But it will
256 	 * certainly be limited by RP0. An error setting
257 	 * the min param is not fatal.
258 	 */
259 	mutex_lock(&slpc->lock);
260 	if (atomic_read(&slpc->num_waiters)) {
261 		err = slpc_force_min_freq(slpc, slpc->boost_freq);
262 		if (!err)
263 			slpc->num_boosts++;
264 	}
265 	mutex_unlock(&slpc->lock);
266 }
267 
268 int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
269 {
270 	struct intel_guc *guc = slpc_to_guc(slpc);
271 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
272 	u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
273 	int err;
274 
275 	GEM_BUG_ON(slpc->vma);
276 
277 	err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
278 	if (unlikely(err)) {
279 		i915_probe_error(i915,
280 				 "Failed to allocate SLPC struct (err=%pe)\n",
281 				 ERR_PTR(err));
282 		return err;
283 	}
284 
285 	slpc->max_freq_softlimit = 0;
286 	slpc->min_freq_softlimit = 0;
287 
288 	slpc->boost_freq = 0;
289 	atomic_set(&slpc->num_waiters, 0);
290 	slpc->num_boosts = 0;
291 	slpc->media_ratio_mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL;
292 
293 	mutex_init(&slpc->lock);
294 	INIT_WORK(&slpc->boost_work, slpc_boost_work);
295 
296 	return err;
297 }
298 
299 static const char *slpc_global_state_to_string(enum slpc_global_state state)
300 {
301 	switch (state) {
302 	case SLPC_GLOBAL_STATE_NOT_RUNNING:
303 		return "not running";
304 	case SLPC_GLOBAL_STATE_INITIALIZING:
305 		return "initializing";
306 	case SLPC_GLOBAL_STATE_RESETTING:
307 		return "resetting";
308 	case SLPC_GLOBAL_STATE_RUNNING:
309 		return "running";
310 	case SLPC_GLOBAL_STATE_SHUTTING_DOWN:
311 		return "shutting down";
312 	case SLPC_GLOBAL_STATE_ERROR:
313 		return "error";
314 	default:
315 		return "unknown";
316 	}
317 }
318 
319 static const char *slpc_get_state_string(struct intel_guc_slpc *slpc)
320 {
321 	return slpc_global_state_to_string(slpc_get_state(slpc));
322 }
323 
324 static int guc_action_slpc_reset(struct intel_guc *guc, u32 offset)
325 {
326 	u32 request[] = {
327 		GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
328 		SLPC_EVENT(SLPC_EVENT_RESET, 2),
329 		offset,
330 		0,
331 	};
332 	int ret;
333 
334 	ret = intel_guc_send(guc, request, ARRAY_SIZE(request));
335 
336 	return ret > 0 ? -EPROTO : ret;
337 }
338 
339 static int slpc_reset(struct intel_guc_slpc *slpc)
340 {
341 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
342 	struct intel_guc *guc = slpc_to_guc(slpc);
343 	u32 offset = intel_guc_ggtt_offset(guc, slpc->vma);
344 	int ret;
345 
346 	ret = guc_action_slpc_reset(guc, offset);
347 
348 	if (unlikely(ret < 0)) {
349 		i915_probe_error(i915, "SLPC reset action failed (%pe)\n",
350 				 ERR_PTR(ret));
351 		return ret;
352 	}
353 
354 	if (!ret) {
355 		if (wait_for(slpc_is_running(slpc), SLPC_RESET_TIMEOUT_MS)) {
356 			i915_probe_error(i915, "SLPC not enabled! State = %s\n",
357 					 slpc_get_state_string(slpc));
358 			return -EIO;
359 		}
360 	}
361 
362 	return 0;
363 }
364 
365 static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
366 {
367 	struct slpc_shared_data *data = slpc->vaddr;
368 
369 	GEM_BUG_ON(!slpc->vma);
370 
371 	return	DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
372 				  data->task_state_data.freq) *
373 				  GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
374 }
375 
376 static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
377 {
378 	struct slpc_shared_data *data = slpc->vaddr;
379 
380 	GEM_BUG_ON(!slpc->vma);
381 
382 	return	DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
383 				  data->task_state_data.freq) *
384 				  GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
385 }
386 
387 static void slpc_shared_data_reset(struct slpc_shared_data *data)
388 {
389 	memset(data, 0, sizeof(struct slpc_shared_data));
390 
391 	data->header.size = sizeof(struct slpc_shared_data);
392 
393 	/* Enable only GTPERF task, disable others */
394 	slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
395 			     SLPC_PARAM_TASK_DISABLE_GTPERF);
396 
397 	slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
398 			      SLPC_PARAM_TASK_DISABLE_BALANCER);
399 
400 	slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
401 			      SLPC_PARAM_TASK_DISABLE_DCC);
402 }
403 
404 /**
405  * intel_guc_slpc_set_max_freq() - Set max frequency limit for SLPC.
406  * @slpc: pointer to intel_guc_slpc.
407  * @val: frequency (MHz)
408  *
409  * This function will invoke GuC SLPC action to update the max frequency
410  * limit for unslice.
411  *
412  * Return: 0 on success, non-zero error code on failure.
413  */
414 int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val)
415 {
416 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
417 	intel_wakeref_t wakeref;
418 	int ret;
419 
420 	if (val < slpc->min_freq ||
421 	    val > slpc->rp0_freq ||
422 	    val < slpc->min_freq_softlimit)
423 		return -EINVAL;
424 
425 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
426 		ret = slpc_set_param(slpc,
427 				     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
428 				     val);
429 
430 		/* Return standardized err code for sysfs calls */
431 		if (ret)
432 			ret = -EIO;
433 	}
434 
435 	if (!ret)
436 		slpc->max_freq_softlimit = val;
437 
438 	return ret;
439 }
440 
441 /**
442  * intel_guc_slpc_get_max_freq() - Get max frequency limit for SLPC.
443  * @slpc: pointer to intel_guc_slpc.
444  * @val: pointer to val which will hold max frequency (MHz)
445  *
446  * This function will invoke GuC SLPC action to read the max frequency
447  * limit for unslice.
448  *
449  * Return: 0 on success, non-zero error code on failure.
450  */
451 int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val)
452 {
453 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
454 	intel_wakeref_t wakeref;
455 	int ret = 0;
456 
457 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
458 		/* Force GuC to update task data */
459 		ret = slpc_query_task_state(slpc);
460 
461 		if (!ret)
462 			*val = slpc_decode_max_freq(slpc);
463 	}
464 
465 	return ret;
466 }
467 
468 /**
469  * intel_guc_slpc_set_min_freq() - Set min frequency limit for SLPC.
470  * @slpc: pointer to intel_guc_slpc.
471  * @val: frequency (MHz)
472  *
473  * This function will invoke GuC SLPC action to update the min unslice
474  * frequency.
475  *
476  * Return: 0 on success, non-zero error code on failure.
477  */
478 int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val)
479 {
480 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
481 	intel_wakeref_t wakeref;
482 	int ret;
483 
484 	if (val < slpc->min_freq ||
485 	    val > slpc->rp0_freq ||
486 	    val > slpc->max_freq_softlimit)
487 		return -EINVAL;
488 
489 	/* Need a lock now since waitboost can be modifying min as well */
490 	mutex_lock(&slpc->lock);
491 
492 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
493 
494 		ret = slpc_set_param(slpc,
495 				     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
496 				     val);
497 
498 		/* Return standardized err code for sysfs calls */
499 		if (ret)
500 			ret = -EIO;
501 	}
502 
503 	if (!ret)
504 		slpc->min_freq_softlimit = val;
505 
506 	mutex_unlock(&slpc->lock);
507 
508 	return ret;
509 }
510 
511 /**
512  * intel_guc_slpc_get_min_freq() - Get min frequency limit for SLPC.
513  * @slpc: pointer to intel_guc_slpc.
514  * @val: pointer to val which will hold min frequency (MHz)
515  *
516  * This function will invoke GuC SLPC action to read the min frequency
517  * limit for unslice.
518  *
519  * Return: 0 on success, non-zero error code on failure.
520  */
521 int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val)
522 {
523 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
524 	intel_wakeref_t wakeref;
525 	int ret = 0;
526 
527 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
528 		/* Force GuC to update task data */
529 		ret = slpc_query_task_state(slpc);
530 
531 		if (!ret)
532 			*val = slpc_decode_min_freq(slpc);
533 	}
534 
535 	return ret;
536 }
537 
538 int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val)
539 {
540 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
541 	intel_wakeref_t wakeref;
542 	int ret = 0;
543 
544 	if (!HAS_MEDIA_RATIO_MODE(i915))
545 		return -ENODEV;
546 
547 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
548 		ret = slpc_set_param(slpc,
549 				     SLPC_PARAM_MEDIA_FF_RATIO_MODE,
550 				     val);
551 	return ret;
552 }
553 
554 void intel_guc_pm_intrmsk_enable(struct intel_gt *gt)
555 {
556 	u32 pm_intrmsk_mbz = 0;
557 
558 	/*
559 	 * Allow GuC to receive ARAT timer expiry event.
560 	 * This interrupt register is setup by RPS code
561 	 * when host based Turbo is enabled.
562 	 */
563 	pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
564 
565 	intel_uncore_rmw(gt->uncore,
566 			 GEN6_PMINTRMSK, pm_intrmsk_mbz, 0);
567 }
568 
569 static int slpc_set_softlimits(struct intel_guc_slpc *slpc)
570 {
571 	int ret = 0;
572 
573 	/*
574 	 * Softlimits are initially equivalent to platform limits
575 	 * unless they have deviated from defaults, in which case,
576 	 * we retain the values and set min/max accordingly.
577 	 */
578 	if (!slpc->max_freq_softlimit)
579 		slpc->max_freq_softlimit = slpc->rp0_freq;
580 	else if (slpc->max_freq_softlimit != slpc->rp0_freq)
581 		ret = intel_guc_slpc_set_max_freq(slpc,
582 						  slpc->max_freq_softlimit);
583 
584 	if (unlikely(ret))
585 		return ret;
586 
587 	if (!slpc->min_freq_softlimit)
588 		slpc->min_freq_softlimit = slpc->min_freq;
589 	else if (slpc->min_freq_softlimit != slpc->min_freq)
590 		return intel_guc_slpc_set_min_freq(slpc,
591 						   slpc->min_freq_softlimit);
592 
593 	return 0;
594 }
595 
596 static int slpc_ignore_eff_freq(struct intel_guc_slpc *slpc, bool ignore)
597 {
598 	int ret = 0;
599 
600 	if (ignore) {
601 		ret = slpc_set_param(slpc,
602 				     SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY,
603 				     ignore);
604 		if (!ret)
605 			return slpc_set_param(slpc,
606 					      SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
607 					      slpc->min_freq);
608 	} else {
609 		ret = slpc_unset_param(slpc,
610 				       SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY);
611 		if (!ret)
612 			return slpc_unset_param(slpc,
613 						SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ);
614 	}
615 
616 	return ret;
617 }
618 
619 static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
620 {
621 	/* Force SLPC to used platform rp0 */
622 	return slpc_set_param(slpc,
623 			      SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
624 			      slpc->rp0_freq);
625 }
626 
627 static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
628 {
629 	struct intel_rps *rps = &slpc_to_gt(slpc)->rps;
630 	struct intel_rps_freq_caps caps;
631 
632 	gen6_rps_get_freq_caps(rps, &caps);
633 	slpc->rp0_freq = intel_gpu_freq(rps, caps.rp0_freq);
634 	slpc->rp1_freq = intel_gpu_freq(rps, caps.rp1_freq);
635 	slpc->min_freq = intel_gpu_freq(rps, caps.min_freq);
636 
637 	if (!slpc->boost_freq)
638 		slpc->boost_freq = slpc->rp0_freq;
639 }
640 
641 /*
642  * intel_guc_slpc_enable() - Start SLPC
643  * @slpc: pointer to intel_guc_slpc.
644  *
645  * SLPC is enabled by setting up the shared data structure and
646  * sending reset event to GuC SLPC. Initial data is setup in
647  * intel_guc_slpc_init. Here we send the reset event. We do
648  * not currently need a slpc_disable since this is taken care
649  * of automatically when a reset/suspend occurs and the GuC
650  * CTB is destroyed.
651  *
652  * Return: 0 on success, non-zero error code on failure.
653  */
654 int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
655 {
656 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
657 	int ret;
658 
659 	GEM_BUG_ON(!slpc->vma);
660 
661 	slpc_shared_data_reset(slpc->vaddr);
662 
663 	ret = slpc_reset(slpc);
664 	if (unlikely(ret < 0)) {
665 		i915_probe_error(i915, "SLPC Reset event returned (%pe)\n",
666 				 ERR_PTR(ret));
667 		return ret;
668 	}
669 
670 	ret = slpc_query_task_state(slpc);
671 	if (unlikely(ret < 0))
672 		return ret;
673 
674 	intel_guc_pm_intrmsk_enable(to_gt(i915));
675 
676 	slpc_get_rp_values(slpc);
677 
678 	/* Ignore efficient freq and set min to platform min */
679 	ret = slpc_ignore_eff_freq(slpc, true);
680 	if (unlikely(ret)) {
681 		i915_probe_error(i915, "Failed to set SLPC min to RPn (%pe)\n",
682 				 ERR_PTR(ret));
683 		return ret;
684 	}
685 
686 	/* Set SLPC max limit to RP0 */
687 	ret = slpc_use_fused_rp0(slpc);
688 	if (unlikely(ret)) {
689 		i915_probe_error(i915, "Failed to set SLPC max to RP0 (%pe)\n",
690 				 ERR_PTR(ret));
691 		return ret;
692 	}
693 
694 	/* Revert SLPC min/max to softlimits if necessary */
695 	ret = slpc_set_softlimits(slpc);
696 	if (unlikely(ret)) {
697 		i915_probe_error(i915, "Failed to set SLPC softlimits (%pe)\n",
698 				 ERR_PTR(ret));
699 		return ret;
700 	}
701 
702 	/* Set cached media freq ratio mode */
703 	intel_guc_slpc_set_media_ratio_mode(slpc, slpc->media_ratio_mode);
704 
705 	return 0;
706 }
707 
708 int intel_guc_slpc_set_boost_freq(struct intel_guc_slpc *slpc, u32 val)
709 {
710 	int ret = 0;
711 
712 	if (val < slpc->min_freq || val > slpc->rp0_freq)
713 		return -EINVAL;
714 
715 	mutex_lock(&slpc->lock);
716 
717 	if (slpc->boost_freq != val) {
718 		/* Apply only if there are active waiters */
719 		if (atomic_read(&slpc->num_waiters)) {
720 			ret = slpc_force_min_freq(slpc, val);
721 			if (ret) {
722 				ret = -EIO;
723 				goto done;
724 			}
725 		}
726 
727 		slpc->boost_freq = val;
728 	}
729 
730 done:
731 	mutex_unlock(&slpc->lock);
732 	return ret;
733 }
734 
735 void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
736 {
737 	/*
738 	 * Return min back to the softlimit.
739 	 * This is called during request retire,
740 	 * so we don't need to fail that if the
741 	 * set_param fails.
742 	 */
743 	mutex_lock(&slpc->lock);
744 	if (atomic_dec_and_test(&slpc->num_waiters))
745 		slpc_force_min_freq(slpc, slpc->min_freq_softlimit);
746 	mutex_unlock(&slpc->lock);
747 }
748 
749 int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
750 {
751 	struct drm_i915_private *i915 = slpc_to_i915(slpc);
752 	struct slpc_shared_data *data = slpc->vaddr;
753 	struct slpc_task_state_data *slpc_tasks;
754 	intel_wakeref_t wakeref;
755 	int ret = 0;
756 
757 	GEM_BUG_ON(!slpc->vma);
758 
759 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
760 		ret = slpc_query_task_state(slpc);
761 
762 		if (!ret) {
763 			slpc_tasks = &data->task_state_data;
764 
765 			drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
766 			drm_printf(p, "\tGTPERF task active: %s\n",
767 				   str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
768 			drm_printf(p, "\tMax freq: %u MHz\n",
769 				   slpc_decode_max_freq(slpc));
770 			drm_printf(p, "\tMin freq: %u MHz\n",
771 				   slpc_decode_min_freq(slpc));
772 			drm_printf(p, "\twaitboosts: %u\n",
773 				   slpc->num_boosts);
774 		}
775 	}
776 
777 	return ret;
778 }
779 
780 void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
781 {
782 	if (!slpc->vma)
783 		return;
784 
785 	i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
786 }
787