1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #include "gt/intel_context.h"
7 #include "gt/intel_engine_pm.h"
8 #include "gt/intel_gpu_commands.h"
9 #include "gt/intel_gt.h"
10 #include "gt/intel_ring.h"
11 #include "intel_gsc_uc_heci_cmd_submit.h"
12 
13 struct gsc_heci_pkt {
14 	u64 addr_in;
15 	u32 size_in;
16 	u64 addr_out;
17 	u32 size_out;
18 };
19 
emit_gsc_heci_pkt(struct i915_request * rq,struct gsc_heci_pkt * pkt)20 static int emit_gsc_heci_pkt(struct i915_request *rq, struct gsc_heci_pkt *pkt)
21 {
22 	u32 *cs;
23 
24 	cs = intel_ring_begin(rq, 8);
25 	if (IS_ERR(cs))
26 		return PTR_ERR(cs);
27 
28 	*cs++ = GSC_HECI_CMD_PKT;
29 	*cs++ = lower_32_bits(pkt->addr_in);
30 	*cs++ = upper_32_bits(pkt->addr_in);
31 	*cs++ = pkt->size_in;
32 	*cs++ = lower_32_bits(pkt->addr_out);
33 	*cs++ = upper_32_bits(pkt->addr_out);
34 	*cs++ = pkt->size_out;
35 	*cs++ = 0;
36 
37 	intel_ring_advance(rq, cs);
38 
39 	return 0;
40 }
41 
intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc * gsc,u64 addr_in,u32 size_in,u64 addr_out,u32 size_out)42 int intel_gsc_uc_heci_cmd_submit_packet(struct intel_gsc_uc *gsc, u64 addr_in,
43 					u32 size_in, u64 addr_out,
44 					u32 size_out)
45 {
46 	struct intel_context *ce = gsc->ce;
47 	struct i915_request *rq;
48 	struct gsc_heci_pkt pkt = {
49 	.addr_in = addr_in,
50 	.size_in = size_in,
51 	.addr_out = addr_out,
52 	.size_out = size_out
53 	};
54 	int err;
55 
56 	if (!ce)
57 		return -ENODEV;
58 
59 	rq = i915_request_create(ce);
60 	if (IS_ERR(rq))
61 		return PTR_ERR(rq);
62 
63 	if (ce->engine->emit_init_breadcrumb) {
64 		err = ce->engine->emit_init_breadcrumb(rq);
65 		if (err)
66 			goto out_rq;
67 	}
68 
69 	err = emit_gsc_heci_pkt(rq, &pkt);
70 
71 	if (err)
72 		goto out_rq;
73 
74 	err = ce->engine->emit_flush(rq, 0);
75 
76 out_rq:
77 	i915_request_get(rq);
78 
79 	if (unlikely(err))
80 		i915_request_set_error_once(rq, err);
81 
82 	i915_request_add(rq);
83 
84 	if (!err && i915_request_wait(rq, 0, msecs_to_jiffies(500)) < 0)
85 		err = -ETIME;
86 
87 	i915_request_put(rq);
88 
89 	if (err)
90 		drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
91 			"Request submission for GSC heci cmd failed (%d)\n",
92 			err);
93 
94 	return err;
95 }
96 
intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header * header,u8 heci_client_id,u32 message_size,u64 host_session_id)97 void intel_gsc_uc_heci_cmd_emit_mtl_header(struct intel_gsc_mtl_header *header,
98 					   u8 heci_client_id, u32 message_size,
99 					   u64 host_session_id)
100 {
101 	host_session_id &= ~HOST_SESSION_MASK;
102 	if (host_session_id && heci_client_id == HECI_MEADDRESS_PXP)
103 		host_session_id |= HOST_SESSION_PXP_SINGLE;
104 
105 	header->validity_marker = GSC_HECI_VALIDITY_MARKER;
106 	header->heci_client_id = heci_client_id;
107 	header->host_session_handle = host_session_id;
108 	header->header_version = MTL_GSC_HEADER_VERSION;
109 	header->message_size = message_size;
110 }
111 
112 static void
emit_gsc_heci_pkt_nonpriv(u32 * cmd,struct intel_gsc_heci_non_priv_pkt * pkt)113 emit_gsc_heci_pkt_nonpriv(u32 *cmd, struct intel_gsc_heci_non_priv_pkt *pkt)
114 {
115 	*cmd++ = GSC_HECI_CMD_PKT;
116 	*cmd++ = lower_32_bits(pkt->addr_in);
117 	*cmd++ = upper_32_bits(pkt->addr_in);
118 	*cmd++ = pkt->size_in;
119 	*cmd++ = lower_32_bits(pkt->addr_out);
120 	*cmd++ = upper_32_bits(pkt->addr_out);
121 	*cmd++ = pkt->size_out;
122 	*cmd++ = 0;
123 	*cmd++ = MI_BATCH_BUFFER_END;
124 }
125 
126 int
intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc * gsc,struct intel_context * ce,struct intel_gsc_heci_non_priv_pkt * pkt,u32 * cmd,int timeout_ms)127 intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc,
128 				     struct intel_context *ce,
129 				     struct intel_gsc_heci_non_priv_pkt *pkt,
130 				     u32 *cmd, int timeout_ms)
131 {
132 	struct intel_engine_cs *engine;
133 	struct i915_gem_ww_ctx ww;
134 	struct i915_request *rq;
135 	int err, trials = 0;
136 
137 	i915_gem_ww_ctx_init(&ww, false);
138 retry:
139 	err = i915_gem_object_lock(pkt->bb_vma->obj, &ww);
140 	if (err)
141 		goto out_ww;
142 	err = i915_gem_object_lock(pkt->heci_pkt_vma->obj, &ww);
143 	if (err)
144 		goto out_ww;
145 	err = intel_context_pin_ww(ce, &ww);
146 	if (err)
147 		goto out_ww;
148 
149 	rq = i915_request_create(ce);
150 	if (IS_ERR(rq)) {
151 		err = PTR_ERR(rq);
152 		goto out_unpin_ce;
153 	}
154 
155 	emit_gsc_heci_pkt_nonpriv(cmd, pkt);
156 
157 	err = i915_vma_move_to_active(pkt->bb_vma, rq, 0);
158 	if (err)
159 		goto out_rq;
160 	err = i915_vma_move_to_active(pkt->heci_pkt_vma, rq, EXEC_OBJECT_WRITE);
161 	if (err)
162 		goto out_rq;
163 
164 	engine = rq->context->engine;
165 	if (engine->emit_init_breadcrumb) {
166 		err = engine->emit_init_breadcrumb(rq);
167 		if (err)
168 			goto out_rq;
169 	}
170 
171 	err = engine->emit_bb_start(rq, i915_vma_offset(pkt->bb_vma), PAGE_SIZE, 0);
172 	if (err)
173 		goto out_rq;
174 
175 	err = ce->engine->emit_flush(rq, 0);
176 	if (err)
177 		drm_err(&gsc_uc_to_gt(gsc)->i915->drm,
178 			"Failed emit-flush for gsc-heci-non-priv-pkterr=%d\n", err);
179 
180 out_rq:
181 	i915_request_get(rq);
182 
183 	if (unlikely(err))
184 		i915_request_set_error_once(rq, err);
185 
186 	i915_request_add(rq);
187 
188 	if (!err) {
189 		if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE,
190 				      msecs_to_jiffies(timeout_ms)) < 0)
191 			err = -ETIME;
192 	}
193 
194 	i915_request_put(rq);
195 
196 out_unpin_ce:
197 	intel_context_unpin(ce);
198 out_ww:
199 	if (err == -EDEADLK) {
200 		err = i915_gem_ww_ctx_backoff(&ww);
201 		if (!err) {
202 			if (++trials < 10)
203 				goto retry;
204 			else
205 				err = -EAGAIN;
206 		}
207 	}
208 	i915_gem_ww_ctx_fini(&ww);
209 
210 	return err;
211 }
212