1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/util_macros.h> 7 8 #include "intel_ddi.h" 9 #include "intel_ddi_buf_trans.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_snps_phy.h" 13 #include "intel_snps_phy_regs.h" 14 15 /** 16 * DOC: Synopsis PHY support 17 * 18 * Synopsis PHYs are primarily programmed by looking up magic register values 19 * in tables rather than calculating the necessary values at runtime. 20 * 21 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 22 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 23 * platforms and must be programming directly during the modeset sequence 24 * since it is not handled by the shared DPLL framework as on other platforms. 25 */ 26 27 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) 28 { 29 enum phy phy; 30 31 for_each_phy_masked(phy, ~0) { 32 if (!intel_phy_is_snps(i915, phy)) 33 continue; 34 35 if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy), 36 DG2_PHY_DP_TX_ACK_MASK, 25)) 37 drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n", 38 phy_name(phy)); 39 } 40 } 41 42 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, 43 enum phy phy, bool enable) 44 { 45 u32 val; 46 47 if (!intel_phy_is_snps(dev_priv, phy)) 48 return; 49 50 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 51 enable ? 2 : 3); 52 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy), 53 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 54 } 55 56 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 57 const struct intel_crtc_state *crtc_state) 58 { 59 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 60 const struct intel_ddi_buf_trans *trans; 61 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 62 int n_entries, ln; 63 64 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 65 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 66 return; 67 68 for (ln = 0; ln < 4; ln++) { 69 int level = intel_ddi_level(encoder, crtc_state, ln); 70 u32 val = 0; 71 72 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 73 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 74 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 75 76 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 77 } 78 } 79 80 /* 81 * Basic DP link rates with 100 MHz reference clock. 82 */ 83 84 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 85 .clock = 162000, 86 .ref_control = 87 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 88 .mpllb_cp = 89 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 90 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 91 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 92 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 93 .mpllb_div = 94 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 95 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 96 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 97 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 98 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 99 .mpllb_div2 = 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 101 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 102 .mpllb_fracn1 = 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 105 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 106 .mpllb_fracn2 = 107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 108 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 109 }; 110 111 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 112 .clock = 270000, 113 .ref_control = 114 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 115 .mpllb_cp = 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 117 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 118 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 119 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 120 .mpllb_div = 121 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 122 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 123 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 124 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 125 .mpllb_div2 = 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 127 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 128 .mpllb_fracn1 = 129 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 130 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 131 }; 132 133 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 134 .clock = 540000, 135 .ref_control = 136 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 137 .mpllb_cp = 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 139 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 140 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 141 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 142 .mpllb_div = 143 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 144 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 145 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 146 .mpllb_div2 = 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 148 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 149 .mpllb_fracn1 = 150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 151 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 152 }; 153 154 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 155 .clock = 810000, 156 .ref_control = 157 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 158 .mpllb_cp = 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 162 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 163 .mpllb_div = 164 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 165 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 166 .mpllb_div2 = 167 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 168 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 169 .mpllb_fracn1 = 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 171 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 172 }; 173 174 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 175 .clock = 1000000, 176 .ref_control = 177 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 178 .mpllb_cp = 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 180 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 181 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 182 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 183 .mpllb_div = 184 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 185 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 186 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 187 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 190 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 191 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 192 .mpllb_div2 = 193 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 194 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 195 .mpllb_fracn1 = 196 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 197 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 198 199 /* 200 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 201 */ 202 .mpllb_sscen = 203 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 204 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 205 .mpllb_sscstep = 206 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 207 }; 208 209 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 210 .clock = 1350000, 211 .ref_control = 212 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 213 .mpllb_cp = 214 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 215 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 216 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 217 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 218 .mpllb_div = 219 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 220 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 221 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 222 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 224 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 225 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 226 .mpllb_div2 = 227 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 228 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 229 .mpllb_fracn1 = 230 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 231 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 232 233 /* 234 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 235 */ 236 .mpllb_sscen = 237 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 238 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 239 .mpllb_sscstep = 240 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 241 }; 242 243 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 244 &dg2_dp_rbr_100, 245 &dg2_dp_hbr1_100, 246 &dg2_dp_hbr2_100, 247 &dg2_dp_hbr3_100, 248 &dg2_dp_uhbr10_100, 249 &dg2_dp_uhbr13_100, 250 NULL, 251 }; 252 253 /* 254 * eDP link rates with 100 MHz reference clock. 255 */ 256 257 static const struct intel_mpllb_state dg2_edp_r216 = { 258 .clock = 216000, 259 .ref_control = 260 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 261 .mpllb_cp = 262 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 263 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 264 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 265 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 266 .mpllb_div = 267 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 268 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 269 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 270 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 271 .mpllb_div2 = 272 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 273 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 274 .mpllb_fracn1 = 275 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 277 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 278 .mpllb_fracn2 = 279 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 280 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 281 .mpllb_sscen = 282 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 283 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 284 .mpllb_sscstep = 285 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 286 }; 287 288 static const struct intel_mpllb_state dg2_edp_r243 = { 289 .clock = 243000, 290 .ref_control = 291 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 292 .mpllb_cp = 293 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 294 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 295 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 296 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 297 .mpllb_div = 298 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 299 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 300 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 301 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 302 .mpllb_div2 = 303 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 304 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 305 .mpllb_fracn1 = 306 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 307 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 308 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 309 .mpllb_fracn2 = 310 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 311 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 312 .mpllb_sscen = 313 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 314 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 315 .mpllb_sscstep = 316 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 317 }; 318 319 static const struct intel_mpllb_state dg2_edp_r324 = { 320 .clock = 324000, 321 .ref_control = 322 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 323 .mpllb_cp = 324 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 325 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 326 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 327 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 328 .mpllb_div = 329 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 330 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 331 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 332 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 333 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 334 .mpllb_div2 = 335 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 336 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 337 .mpllb_fracn1 = 338 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 341 .mpllb_fracn2 = 342 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 343 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 344 .mpllb_sscen = 345 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 346 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 347 .mpllb_sscstep = 348 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 349 }; 350 351 static const struct intel_mpllb_state dg2_edp_r432 = { 352 .clock = 432000, 353 .ref_control = 354 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 355 .mpllb_cp = 356 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 357 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 358 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 359 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 360 .mpllb_div = 361 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 362 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 363 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 364 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 365 .mpllb_div2 = 366 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 367 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 368 .mpllb_fracn1 = 369 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 372 .mpllb_fracn2 = 373 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 374 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 375 .mpllb_sscen = 376 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 377 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 378 .mpllb_sscstep = 379 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 380 }; 381 382 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 383 &dg2_dp_rbr_100, 384 &dg2_edp_r216, 385 &dg2_edp_r243, 386 &dg2_dp_hbr1_100, 387 &dg2_edp_r324, 388 &dg2_edp_r432, 389 &dg2_dp_hbr2_100, 390 &dg2_dp_hbr3_100, 391 NULL, 392 }; 393 394 /* 395 * HDMI link rates with 100 MHz reference clock. 396 */ 397 398 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 399 .clock = 25175, 400 .ref_control = 401 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 402 .mpllb_cp = 403 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 404 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 405 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 406 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 407 .mpllb_div = 408 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 409 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 410 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 411 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 412 .mpllb_div2 = 413 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 414 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 415 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 416 .mpllb_fracn1 = 417 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 418 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 420 .mpllb_fracn2 = 421 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 422 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 423 .mpllb_sscen = 424 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 425 }; 426 427 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 428 .clock = 27000, 429 .ref_control = 430 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 431 .mpllb_cp = 432 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 433 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 434 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 435 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 436 .mpllb_div = 437 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 438 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 439 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 440 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 441 .mpllb_div2 = 442 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 443 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 444 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 445 .mpllb_fracn1 = 446 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 447 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 448 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 449 .mpllb_fracn2 = 450 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 451 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 452 .mpllb_sscen = 453 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 454 }; 455 456 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 457 .clock = 74250, 458 .ref_control = 459 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 460 .mpllb_cp = 461 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 462 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 463 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 464 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 465 .mpllb_div = 466 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 467 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 468 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 469 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 471 .mpllb_div2 = 472 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 473 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 474 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 475 .mpllb_fracn1 = 476 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 477 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 478 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 479 .mpllb_fracn2 = 480 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 481 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 482 .mpllb_sscen = 483 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 484 }; 485 486 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 487 .clock = 148500, 488 .ref_control = 489 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 490 .mpllb_cp = 491 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 492 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 493 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 494 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 495 .mpllb_div = 496 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 497 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 498 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 499 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 500 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 501 .mpllb_div2 = 502 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 503 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 504 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 505 .mpllb_fracn1 = 506 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 507 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 508 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 509 .mpllb_fracn2 = 510 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 511 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 512 .mpllb_sscen = 513 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 514 }; 515 516 static const struct intel_mpllb_state dg2_hdmi_594 = { 517 .clock = 594000, 518 .ref_control = 519 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 520 .mpllb_cp = 521 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 522 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 523 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 524 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 525 .mpllb_div = 526 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 527 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 528 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 529 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 530 .mpllb_div2 = 531 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 532 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 534 .mpllb_fracn1 = 535 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 537 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 538 .mpllb_fracn2 = 539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 540 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 541 .mpllb_sscen = 542 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 543 }; 544 545 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 546 &dg2_hdmi_25_175, 547 &dg2_hdmi_27_0, 548 &dg2_hdmi_74_25, 549 &dg2_hdmi_148_5, 550 &dg2_hdmi_594, 551 NULL, 552 }; 553 554 static const struct intel_mpllb_state * const * 555 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 556 struct intel_encoder *encoder) 557 { 558 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 559 return dg2_edp_tables; 560 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 561 return dg2_dp_100_tables; 562 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 563 return dg2_hdmi_tables; 564 } 565 566 MISSING_CASE(encoder->type); 567 return NULL; 568 } 569 570 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 571 struct intel_encoder *encoder) 572 { 573 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 574 const struct intel_mpllb_state * const *tables; 575 int i; 576 577 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 578 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) 579 != MODE_OK) { 580 /* 581 * FIXME: Can only support fixed HDMI frequencies 582 * until we have a proper algorithm under a valid 583 * license. 584 */ 585 drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n", 586 crtc_state->port_clock); 587 return -EINVAL; 588 } 589 } 590 591 tables = intel_mpllb_tables_get(crtc_state, encoder); 592 if (!tables) 593 return -EINVAL; 594 595 for (i = 0; tables[i]; i++) { 596 if (crtc_state->port_clock <= tables[i]->clock) { 597 crtc_state->mpllb_state = *tables[i]; 598 return 0; 599 } 600 } 601 602 return -EINVAL; 603 } 604 605 void intel_mpllb_enable(struct intel_encoder *encoder, 606 const struct intel_crtc_state *crtc_state) 607 { 608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 609 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; 610 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 611 i915_reg_t enable_reg = (phy <= PHY_D ? 612 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 613 614 /* 615 * 3. Software programs the following PLL registers for the desired 616 * frequency. 617 */ 618 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 619 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 620 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 621 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 622 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 623 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 624 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 625 626 /* 627 * 4. If the frequency will result in a change to the voltage 628 * requirement, follow the Display Voltage Frequency Switching - 629 * Sequence Before Frequency Change. 630 * 631 * We handle this step in bxt_set_cdclk(). 632 */ 633 634 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 635 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE); 636 637 /* 638 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 639 * will keep the PLL running during the DDI lane programming and any 640 * typeC DP cable disconnect. Do not set the force before enabling the 641 * PLL because that will start the PLL before it has sampled the 642 * divider values. 643 */ 644 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), 645 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 646 647 /* 648 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 649 * is locked at new settings. This register bit is sampling PHY 650 * dp_mpllb_state interface signal. 651 */ 652 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) 653 drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy)); 654 655 /* 656 * 11. If the frequency will result in a change to the voltage 657 * requirement, follow the Display Voltage Frequency Switching - 658 * Sequence After Frequency Change. 659 * 660 * We handle this step in bxt_set_cdclk(). 661 */ 662 } 663 664 void intel_mpllb_disable(struct intel_encoder *encoder) 665 { 666 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 667 enum phy phy = intel_port_to_phy(i915, encoder->port); 668 i915_reg_t enable_reg = (phy <= PHY_D ? 669 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 670 671 /* 672 * 1. If the frequency will result in a change to the voltage 673 * requirement, follow the Display Voltage Frequency Switching - 674 * Sequence Before Frequency Change. 675 * 676 * We handle this step in bxt_set_cdclk(). 677 */ 678 679 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 680 intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0); 681 682 /* 683 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 684 * This will allow the PLL to stop running. 685 */ 686 intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy), 687 SNPS_PHY_MPLLB_FORCE_EN, 0); 688 689 /* 690 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 691 * (dp_txX_ack) that the new transmitter setting request is completed. 692 */ 693 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5)) 694 drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy)); 695 696 /* 697 * 6. If the frequency will result in a change to the voltage 698 * requirement, follow the Display Voltage Frequency Switching - 699 * Sequence After Frequency Change. 700 * 701 * We handle this step in bxt_set_cdclk(). 702 */ 703 } 704 705 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 706 const struct intel_mpllb_state *pll_state) 707 { 708 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 709 unsigned int multiplier, tx_clk_div, refclk; 710 bool frac_en; 711 712 if (0) 713 refclk = 38400; 714 else 715 refclk = 100000; 716 717 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 718 719 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 720 721 if (frac_en) { 722 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 723 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 724 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 725 } 726 727 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 728 729 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 730 731 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 732 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 733 10 << (tx_clk_div + 16)); 734 } 735 736 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 737 struct intel_mpllb_state *pll_state) 738 { 739 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 740 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 741 742 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); 743 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); 744 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); 745 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); 746 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); 747 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); 748 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); 749 750 /* 751 * REF_CONTROL is under firmware control and never programmed by the 752 * driver; we read it only for sanity checking purposes. The bspec 753 * only tells us the expected value for one field in this register, 754 * so we'll only read out those specific bits here. 755 */ 756 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & 757 SNPS_PHY_REF_CONTROL_REF_RANGE; 758 759 /* 760 * MPLLB_DIV is programmed twice, once with the software-computed 761 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 762 * extra bit during readout so that we return the actual expected 763 * software state. 764 */ 765 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 766 } 767 768 int intel_snps_phy_check_hdmi_link_rate(int clock) 769 { 770 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; 771 int i; 772 773 for (i = 0; tables[i]; i++) { 774 if (clock == tables[i]->clock) 775 return MODE_OK; 776 } 777 778 return MODE_CLOCK_RANGE; 779 } 780