1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/util_macros.h> 7 8 #include "intel_ddi.h" 9 #include "intel_ddi_buf_trans.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_snps_phy.h" 13 14 /** 15 * DOC: Synopsis PHY support 16 * 17 * Synopsis PHYs are primarily programmed by looking up magic register values 18 * in tables rather than calculating the necessary values at runtime. 19 * 20 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 21 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 22 * platforms and must be programming directly during the modeset sequence 23 * since it is not handled by the shared DPLL framework as on other platforms. 24 */ 25 26 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv) 27 { 28 enum phy phy; 29 30 for_each_phy_masked(phy, ~0) { 31 if (!intel_phy_is_snps(dev_priv, phy)) 32 continue; 33 34 if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy), 35 DG2_PHY_DP_TX_ACK_MASK, 25)) 36 DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n", 37 phy); 38 } 39 } 40 41 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, 42 enum phy phy, bool enable) 43 { 44 u32 val; 45 46 if (!intel_phy_is_snps(dev_priv, phy)) 47 return; 48 49 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 50 enable ? 2 : 3); 51 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy), 52 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 53 } 54 55 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 56 const struct intel_crtc_state *crtc_state) 57 { 58 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 59 const struct intel_ddi_buf_trans *trans; 60 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 61 int level = intel_ddi_level(encoder, crtc_state, 0); 62 int n_entries, ln; 63 64 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 65 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 66 return; 67 68 for (ln = 0; ln < 4; ln++) { 69 u32 val = 0; 70 71 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 72 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 73 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 74 75 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 76 } 77 } 78 79 /* 80 * Basic DP link rates with 100 MHz reference clock. 81 */ 82 83 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 84 .clock = 162000, 85 .ref_control = 86 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 87 .mpllb_cp = 88 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 89 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 90 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 91 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 92 .mpllb_div = 93 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 94 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 95 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 96 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 97 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 98 .mpllb_div2 = 99 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 101 .mpllb_fracn1 = 102 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 105 .mpllb_fracn2 = 106 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 108 }; 109 110 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 111 .clock = 270000, 112 .ref_control = 113 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 114 .mpllb_cp = 115 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 117 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 118 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 119 .mpllb_div = 120 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 121 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 122 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 123 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 124 .mpllb_div2 = 125 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 127 .mpllb_fracn1 = 128 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 129 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 130 }; 131 132 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 133 .clock = 540000, 134 .ref_control = 135 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 136 .mpllb_cp = 137 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 139 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 140 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 141 .mpllb_div = 142 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 143 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 144 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 145 .mpllb_div2 = 146 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 148 .mpllb_fracn1 = 149 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 151 }; 152 153 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 154 .clock = 810000, 155 .ref_control = 156 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 157 .mpllb_cp = 158 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 162 .mpllb_div = 163 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 164 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 165 .mpllb_div2 = 166 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 167 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 168 .mpllb_fracn1 = 169 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 171 }; 172 173 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 174 .clock = 1000000, 175 .ref_control = 176 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 177 .mpllb_cp = 178 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 180 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 181 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 182 .mpllb_div = 183 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 184 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 185 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 186 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 187 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 190 .mpllb_div2 = 191 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 192 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 193 .mpllb_fracn1 = 194 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 195 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 196 197 /* 198 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 199 */ 200 .mpllb_sscen = 201 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 202 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 203 .mpllb_sscstep = 204 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 205 }; 206 207 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 208 .clock = 1350000, 209 .ref_control = 210 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 211 .mpllb_cp = 212 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 213 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 214 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 215 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 216 .mpllb_div = 217 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 218 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 219 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 220 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 221 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 222 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 224 .mpllb_div2 = 225 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 226 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 227 .mpllb_fracn1 = 228 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 229 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 230 231 /* 232 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 233 */ 234 .mpllb_sscen = 235 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 236 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 237 .mpllb_sscstep = 238 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 239 }; 240 241 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 242 &dg2_dp_rbr_100, 243 &dg2_dp_hbr1_100, 244 &dg2_dp_hbr2_100, 245 &dg2_dp_hbr3_100, 246 &dg2_dp_uhbr10_100, 247 &dg2_dp_uhbr13_100, 248 NULL, 249 }; 250 251 /* 252 * Basic DP link rates with 38.4 MHz reference clock. 253 */ 254 255 static const struct intel_mpllb_state dg2_dp_rbr_38_4 = { 256 .clock = 162000, 257 .ref_control = 258 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 259 .mpllb_cp = 260 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 261 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 262 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 263 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 264 .mpllb_div = 265 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 266 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 267 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 268 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 269 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 270 .mpllb_div2 = 271 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 272 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304), 273 .mpllb_fracn1 = 274 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 275 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 277 .mpllb_fracn2 = 278 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152), 279 }; 280 281 static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = { 282 .clock = 270000, 283 .ref_control = 284 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 285 .mpllb_cp = 286 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 287 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 288 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 289 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 290 .mpllb_div = 291 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 292 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 293 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 294 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 295 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 296 .mpllb_div2 = 297 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 298 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 299 .mpllb_fracn1 = 300 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 301 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 302 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 303 .mpllb_fracn2 = 304 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 305 }; 306 307 static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = { 308 .clock = 540000, 309 .ref_control = 310 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 311 .mpllb_cp = 312 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 313 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 314 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 315 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 316 .mpllb_div = 317 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 318 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 319 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 320 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 321 .mpllb_div2 = 322 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 323 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 324 .mpllb_fracn1 = 325 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 326 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 327 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 328 .mpllb_fracn2 = 329 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 330 }; 331 332 static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = { 333 .clock = 810000, 334 .ref_control = 335 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 336 .mpllb_cp = 337 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 338 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 341 .mpllb_div = 342 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 343 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 344 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 345 .mpllb_div2 = 346 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 347 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388), 348 .mpllb_fracn1 = 349 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 350 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 351 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 352 .mpllb_fracn2 = 353 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440), 354 }; 355 356 static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = { 357 .clock = 1000000, 358 .ref_control = 359 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 360 .mpllb_cp = 361 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 362 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 365 .mpllb_div = 366 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 367 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 368 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 369 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 372 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 373 .mpllb_div2 = 374 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 375 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488), 376 .mpllb_fracn1 = 377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 378 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3), 380 .mpllb_fracn2 = 381 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) | 382 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306), 383 384 /* 385 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 386 */ 387 .mpllb_sscen = 388 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 389 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800), 390 .mpllb_sscstep = 391 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024), 392 }; 393 394 static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = { 395 .clock = 1350000, 396 .ref_control = 397 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 398 .mpllb_cp = 399 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 400 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) | 401 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 403 .mpllb_div = 404 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 405 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 406 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 407 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 408 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 409 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 410 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 411 .mpllb_div2 = 412 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 413 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670), 414 .mpllb_fracn1 = 415 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 416 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 417 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 418 .mpllb_fracn2 = 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864), 420 421 /* 422 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 423 */ 424 .mpllb_sscen = 425 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 426 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680), 427 .mpllb_sscstep = 428 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182), 429 }; 430 431 static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = { 432 &dg2_dp_rbr_38_4, 433 &dg2_dp_hbr1_38_4, 434 &dg2_dp_hbr2_38_4, 435 &dg2_dp_hbr3_38_4, 436 &dg2_dp_uhbr10_38_4, 437 &dg2_dp_uhbr13_38_4, 438 NULL, 439 }; 440 441 /* 442 * eDP link rates with 100 MHz reference clock. 443 */ 444 445 static const struct intel_mpllb_state dg2_edp_r216 = { 446 .clock = 216000, 447 .ref_control = 448 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 449 .mpllb_cp = 450 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 451 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 452 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 453 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 454 .mpllb_div = 455 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 456 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 457 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 458 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 459 .mpllb_div2 = 460 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 461 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 462 .mpllb_fracn1 = 463 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 464 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 465 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 466 .mpllb_fracn2 = 467 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 468 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 469 .mpllb_sscen = 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 471 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 472 .mpllb_sscstep = 473 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 474 }; 475 476 static const struct intel_mpllb_state dg2_edp_r243 = { 477 .clock = 243000, 478 .ref_control = 479 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 480 .mpllb_cp = 481 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 482 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 483 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 484 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 485 .mpllb_div = 486 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 487 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 488 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 489 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 490 .mpllb_div2 = 491 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 492 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 493 .mpllb_fracn1 = 494 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 495 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 496 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 497 .mpllb_fracn2 = 498 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 499 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 500 .mpllb_sscen = 501 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 502 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 503 .mpllb_sscstep = 504 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 505 }; 506 507 static const struct intel_mpllb_state dg2_edp_r324 = { 508 .clock = 324000, 509 .ref_control = 510 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 511 .mpllb_cp = 512 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 513 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 514 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 515 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 516 .mpllb_div = 517 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 518 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 519 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 520 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 521 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 522 .mpllb_div2 = 523 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 524 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 525 .mpllb_fracn1 = 526 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 527 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 528 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 529 .mpllb_fracn2 = 530 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 531 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 532 .mpllb_sscen = 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 534 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 535 .mpllb_sscstep = 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 537 }; 538 539 static const struct intel_mpllb_state dg2_edp_r432 = { 540 .clock = 432000, 541 .ref_control = 542 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 543 .mpllb_cp = 544 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 545 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 546 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 547 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 548 .mpllb_div = 549 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 550 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 551 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 552 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 553 .mpllb_div2 = 554 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 555 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 556 .mpllb_fracn1 = 557 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 558 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 559 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 560 .mpllb_fracn2 = 561 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 562 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 563 .mpllb_sscen = 564 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 565 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 566 .mpllb_sscstep = 567 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 568 }; 569 570 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 571 &dg2_dp_rbr_100, 572 &dg2_edp_r216, 573 &dg2_edp_r243, 574 &dg2_dp_hbr1_100, 575 &dg2_edp_r324, 576 &dg2_edp_r432, 577 &dg2_dp_hbr2_100, 578 &dg2_dp_hbr3_100, 579 NULL, 580 }; 581 582 /* 583 * HDMI link rates with 100 MHz reference clock. 584 */ 585 586 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 587 .clock = 25175, 588 .ref_control = 589 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 590 .mpllb_cp = 591 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 592 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 593 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 594 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 595 .mpllb_div = 596 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 597 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 598 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 599 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 600 .mpllb_div2 = 601 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 602 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 603 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 604 .mpllb_fracn1 = 605 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 607 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 608 .mpllb_fracn2 = 609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 610 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 611 .mpllb_sscen = 612 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 613 }; 614 615 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 616 .clock = 27000, 617 .ref_control = 618 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 619 .mpllb_cp = 620 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 621 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 622 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 623 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 624 .mpllb_div = 625 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 626 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 627 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 628 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 629 .mpllb_div2 = 630 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 631 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 632 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 633 .mpllb_fracn1 = 634 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 635 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 636 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 637 .mpllb_fracn2 = 638 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 639 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 640 .mpllb_sscen = 641 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 642 }; 643 644 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 645 .clock = 74250, 646 .ref_control = 647 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 648 .mpllb_cp = 649 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 650 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 651 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 653 .mpllb_div = 654 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 655 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 656 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 657 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 658 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 659 .mpllb_div2 = 660 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 661 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 662 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 663 .mpllb_fracn1 = 664 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 665 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 666 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 667 .mpllb_fracn2 = 668 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 669 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 670 .mpllb_sscen = 671 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 672 }; 673 674 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 675 .clock = 148500, 676 .ref_control = 677 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 678 .mpllb_cp = 679 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 680 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 681 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 683 .mpllb_div = 684 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 685 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 686 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 687 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 688 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 689 .mpllb_div2 = 690 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 691 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 692 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 693 .mpllb_fracn1 = 694 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 695 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 696 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 697 .mpllb_fracn2 = 698 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 699 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 700 .mpllb_sscen = 701 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 702 }; 703 704 static const struct intel_mpllb_state dg2_hdmi_594 = { 705 .clock = 594000, 706 .ref_control = 707 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 708 .mpllb_cp = 709 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 710 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 711 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 713 .mpllb_div = 714 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 715 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 716 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 717 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 718 .mpllb_div2 = 719 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 720 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 721 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 722 .mpllb_fracn1 = 723 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 724 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 725 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 726 .mpllb_fracn2 = 727 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 728 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 729 .mpllb_sscen = 730 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 731 }; 732 733 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 734 &dg2_hdmi_25_175, 735 &dg2_hdmi_27_0, 736 &dg2_hdmi_74_25, 737 &dg2_hdmi_148_5, 738 &dg2_hdmi_594, 739 NULL, 740 }; 741 742 static const struct intel_mpllb_state * const * 743 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 744 struct intel_encoder *encoder) 745 { 746 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 747 return dg2_edp_tables; 748 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 749 /* 750 * FIXME: Initially we're just enabling the "combo" outputs on 751 * port A-D. The MPLLB for those ports takes an input from the 752 * "Display Filter PLL" which always has an output frequency 753 * of 100 MHz, hence the use of the _100 tables below. 754 * 755 * Once we enable port TC1 it will either use the same 100 MHz 756 * "Display Filter PLL" (when strapped to support a native 757 * display connection) or different 38.4 MHz "Filter PLL" when 758 * strapped to support a USB connection, so we'll need to check 759 * that to determine which table to use. 760 */ 761 if (0) 762 return dg2_dp_38_4_tables; 763 else 764 return dg2_dp_100_tables; 765 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 766 return dg2_hdmi_tables; 767 } 768 769 MISSING_CASE(encoder->type); 770 return NULL; 771 } 772 773 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 774 struct intel_encoder *encoder) 775 { 776 const struct intel_mpllb_state * const *tables; 777 int i; 778 779 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 780 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) 781 != MODE_OK) { 782 /* 783 * FIXME: Can only support fixed HDMI frequencies 784 * until we have a proper algorithm under a valid 785 * license. 786 */ 787 DRM_DEBUG_KMS("Can't support HDMI link rate %d\n", 788 crtc_state->port_clock); 789 return -EINVAL; 790 } 791 } 792 793 tables = intel_mpllb_tables_get(crtc_state, encoder); 794 if (!tables) 795 return -EINVAL; 796 797 for (i = 0; tables[i]; i++) { 798 if (crtc_state->port_clock <= tables[i]->clock) { 799 crtc_state->mpllb_state = *tables[i]; 800 return 0; 801 } 802 } 803 804 return -EINVAL; 805 } 806 807 void intel_mpllb_enable(struct intel_encoder *encoder, 808 const struct intel_crtc_state *crtc_state) 809 { 810 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 811 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; 812 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 813 i915_reg_t enable_reg = (phy <= PHY_D ? 814 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 815 816 /* 817 * 3. Software programs the following PLL registers for the desired 818 * frequency. 819 */ 820 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 821 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 822 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 823 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 824 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 825 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 826 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 827 828 /* 829 * 4. If the frequency will result in a change to the voltage 830 * requirement, follow the Display Voltage Frequency Switching - 831 * Sequence Before Frequency Change. 832 * 833 * We handle this step in bxt_set_cdclk(). 834 */ 835 836 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 837 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE); 838 839 /* 840 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 841 * will keep the PLL running during the DDI lane programming and any 842 * typeC DP cable disconnect. Do not set the force before enabling the 843 * PLL because that will start the PLL before it has sampled the 844 * divider values. 845 */ 846 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), 847 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 848 849 /* 850 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 851 * is locked at new settings. This register bit is sampling PHY 852 * dp_mpllb_state interface signal. 853 */ 854 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) 855 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy)); 856 857 /* 858 * 11. If the frequency will result in a change to the voltage 859 * requirement, follow the Display Voltage Frequency Switching - 860 * Sequence After Frequency Change. 861 * 862 * We handle this step in bxt_set_cdclk(). 863 */ 864 } 865 866 void intel_mpllb_disable(struct intel_encoder *encoder) 867 { 868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 869 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 870 i915_reg_t enable_reg = (phy <= PHY_D ? 871 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 872 873 /* 874 * 1. If the frequency will result in a change to the voltage 875 * requirement, follow the Display Voltage Frequency Switching - 876 * Sequence Before Frequency Change. 877 * 878 * We handle this step in bxt_set_cdclk(). 879 */ 880 881 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 882 intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0); 883 884 /* 885 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 886 * This will allow the PLL to stop running. 887 */ 888 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy), 889 SNPS_PHY_MPLLB_FORCE_EN, 0); 890 891 /* 892 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 893 * (dp_txX_ack) that the new transmitter setting request is completed. 894 */ 895 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5)) 896 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy)); 897 898 /* 899 * 6. If the frequency will result in a change to the voltage 900 * requirement, follow the Display Voltage Frequency Switching - 901 * Sequence After Frequency Change. 902 * 903 * We handle this step in bxt_set_cdclk(). 904 */ 905 } 906 907 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 908 const struct intel_mpllb_state *pll_state) 909 { 910 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 911 unsigned int multiplier, tx_clk_div, refclk; 912 bool frac_en; 913 914 if (0) 915 refclk = 38400; 916 else 917 refclk = 100000; 918 919 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 920 921 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 922 923 if (frac_en) { 924 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 925 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 926 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 927 } 928 929 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 930 931 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 932 933 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 934 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 935 10 << (tx_clk_div + 16)); 936 } 937 938 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 939 struct intel_mpllb_state *pll_state) 940 { 941 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 942 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 943 944 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); 945 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); 946 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); 947 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); 948 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); 949 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); 950 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); 951 952 /* 953 * REF_CONTROL is under firmware control and never programmed by the 954 * driver; we read it only for sanity checking purposes. The bspec 955 * only tells us the expected value for one field in this register, 956 * so we'll only read out those specific bits here. 957 */ 958 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & 959 SNPS_PHY_REF_CONTROL_REF_RANGE; 960 961 /* 962 * MPLLB_DIV is programmed twice, once with the software-computed 963 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 964 * extra bit during readout so that we return the actual expected 965 * software state. 966 */ 967 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 968 } 969 970 int intel_snps_phy_check_hdmi_link_rate(int clock) 971 { 972 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; 973 int i; 974 975 for (i = 0; tables[i]; i++) { 976 if (clock == tables[i]->clock) 977 return MODE_OK; 978 } 979 980 return MODE_CLOCK_RANGE; 981 } 982