1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/util_macros.h> 7 8 #include "intel_ddi.h" 9 #include "intel_ddi_buf_trans.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_snps_phy.h" 13 14 /** 15 * DOC: Synopsis PHY support 16 * 17 * Synopsis PHYs are primarily programmed by looking up magic register values 18 * in tables rather than calculating the necessary values at runtime. 19 * 20 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 21 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 22 * platforms and must be programming directly during the modeset sequence 23 * since it is not handled by the shared DPLL framework as on other platforms. 24 */ 25 26 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv) 27 { 28 enum phy phy; 29 30 for_each_phy_masked(phy, ~0) { 31 if (!intel_phy_is_snps(dev_priv, phy)) 32 continue; 33 34 if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy), 35 DG2_PHY_DP_TX_ACK_MASK, 25)) 36 DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n", 37 phy); 38 } 39 } 40 41 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, 42 enum phy phy, bool enable) 43 { 44 u32 val; 45 46 if (!intel_phy_is_snps(dev_priv, phy)) 47 return; 48 49 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 50 enable ? 2 : 3); 51 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy), 52 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 53 } 54 55 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 56 const struct intel_crtc_state *crtc_state) 57 { 58 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 59 const struct intel_ddi_buf_trans *trans; 60 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 61 int n_entries, ln; 62 63 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 64 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 65 return; 66 67 for (ln = 0; ln < 4; ln++) { 68 int level = intel_ddi_level(encoder, crtc_state, ln); 69 u32 val = 0; 70 71 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 72 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 73 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 74 75 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 76 } 77 } 78 79 /* 80 * Basic DP link rates with 100 MHz reference clock. 81 */ 82 83 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 84 .clock = 162000, 85 .ref_control = 86 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 87 .mpllb_cp = 88 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 89 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 90 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 91 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 92 .mpllb_div = 93 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 94 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 95 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 96 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 97 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 98 .mpllb_div2 = 99 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 101 .mpllb_fracn1 = 102 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 105 .mpllb_fracn2 = 106 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 108 }; 109 110 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 111 .clock = 270000, 112 .ref_control = 113 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 114 .mpllb_cp = 115 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 117 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 118 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 119 .mpllb_div = 120 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 121 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 122 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 123 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 124 .mpllb_div2 = 125 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 127 .mpllb_fracn1 = 128 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 129 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 130 }; 131 132 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 133 .clock = 540000, 134 .ref_control = 135 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 136 .mpllb_cp = 137 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 139 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 140 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 141 .mpllb_div = 142 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 143 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 144 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 145 .mpllb_div2 = 146 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 148 .mpllb_fracn1 = 149 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 151 }; 152 153 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 154 .clock = 810000, 155 .ref_control = 156 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 157 .mpllb_cp = 158 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 162 .mpllb_div = 163 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 164 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 165 .mpllb_div2 = 166 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 167 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 168 .mpllb_fracn1 = 169 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 171 }; 172 173 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 174 .clock = 1000000, 175 .ref_control = 176 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 177 .mpllb_cp = 178 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 180 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 181 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 182 .mpllb_div = 183 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 184 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 185 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 186 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 187 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 190 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 191 .mpllb_div2 = 192 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 193 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 194 .mpllb_fracn1 = 195 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 196 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 197 198 /* 199 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 200 */ 201 .mpllb_sscen = 202 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 203 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 204 .mpllb_sscstep = 205 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 206 }; 207 208 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 209 .clock = 1350000, 210 .ref_control = 211 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 212 .mpllb_cp = 213 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 214 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 215 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 216 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 217 .mpllb_div = 218 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 219 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 220 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 221 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 222 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 224 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 225 .mpllb_div2 = 226 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 227 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 228 .mpllb_fracn1 = 229 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 230 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 231 232 /* 233 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 234 */ 235 .mpllb_sscen = 236 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 237 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 238 .mpllb_sscstep = 239 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 240 }; 241 242 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 243 &dg2_dp_rbr_100, 244 &dg2_dp_hbr1_100, 245 &dg2_dp_hbr2_100, 246 &dg2_dp_hbr3_100, 247 &dg2_dp_uhbr10_100, 248 &dg2_dp_uhbr13_100, 249 NULL, 250 }; 251 252 /* 253 * Basic DP link rates with 38.4 MHz reference clock. 254 */ 255 256 static const struct intel_mpllb_state dg2_dp_rbr_38_4 = { 257 .clock = 162000, 258 .ref_control = 259 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 260 .mpllb_cp = 261 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 262 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 263 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 264 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 265 .mpllb_div = 266 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 267 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 268 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 269 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 270 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 271 .mpllb_div2 = 272 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 273 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304), 274 .mpllb_fracn1 = 275 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 277 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 278 .mpllb_fracn2 = 279 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152), 280 }; 281 282 static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = { 283 .clock = 270000, 284 .ref_control = 285 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 286 .mpllb_cp = 287 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 288 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 289 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 290 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 291 .mpllb_div = 292 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 293 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 294 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 295 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 296 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 297 .mpllb_div2 = 298 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 299 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 300 .mpllb_fracn1 = 301 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 302 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 303 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 304 .mpllb_fracn2 = 305 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 306 }; 307 308 static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = { 309 .clock = 540000, 310 .ref_control = 311 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 312 .mpllb_cp = 313 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 314 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 315 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 316 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 317 .mpllb_div = 318 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 319 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 320 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 321 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 322 .mpllb_div2 = 323 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 324 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 325 .mpllb_fracn1 = 326 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 327 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 328 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 329 .mpllb_fracn2 = 330 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 331 }; 332 333 static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = { 334 .clock = 810000, 335 .ref_control = 336 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 337 .mpllb_cp = 338 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 341 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 342 .mpllb_div = 343 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 344 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 345 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 346 .mpllb_div2 = 347 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 348 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388), 349 .mpllb_fracn1 = 350 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 351 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 352 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 353 .mpllb_fracn2 = 354 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440), 355 }; 356 357 static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = { 358 .clock = 1000000, 359 .ref_control = 360 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 361 .mpllb_cp = 362 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 366 .mpllb_div = 367 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 368 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 369 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 372 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 373 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 374 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 375 .mpllb_div2 = 376 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 377 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488), 378 .mpllb_fracn1 = 379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 381 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3), 382 .mpllb_fracn2 = 383 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) | 384 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306), 385 386 /* 387 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 388 */ 389 .mpllb_sscen = 390 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 391 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800), 392 .mpllb_sscstep = 393 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024), 394 }; 395 396 static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = { 397 .clock = 1350000, 398 .ref_control = 399 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 400 .mpllb_cp = 401 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) | 403 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 404 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 405 .mpllb_div = 406 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 407 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 408 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 409 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 410 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 411 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 412 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 413 .mpllb_div2 = 414 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 415 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670), 416 .mpllb_fracn1 = 417 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 418 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 420 .mpllb_fracn2 = 421 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864), 422 423 /* 424 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 425 */ 426 .mpllb_sscen = 427 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 428 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680), 429 .mpllb_sscstep = 430 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182), 431 }; 432 433 static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = { 434 &dg2_dp_rbr_38_4, 435 &dg2_dp_hbr1_38_4, 436 &dg2_dp_hbr2_38_4, 437 &dg2_dp_hbr3_38_4, 438 &dg2_dp_uhbr10_38_4, 439 &dg2_dp_uhbr13_38_4, 440 NULL, 441 }; 442 443 /* 444 * eDP link rates with 100 MHz reference clock. 445 */ 446 447 static const struct intel_mpllb_state dg2_edp_r216 = { 448 .clock = 216000, 449 .ref_control = 450 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 451 .mpllb_cp = 452 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 453 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 454 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 455 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 456 .mpllb_div = 457 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 458 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 459 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 460 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 461 .mpllb_div2 = 462 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 463 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 464 .mpllb_fracn1 = 465 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 466 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 467 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 468 .mpllb_fracn2 = 469 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 471 .mpllb_sscen = 472 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 473 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 474 .mpllb_sscstep = 475 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 476 }; 477 478 static const struct intel_mpllb_state dg2_edp_r243 = { 479 .clock = 243000, 480 .ref_control = 481 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 482 .mpllb_cp = 483 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 484 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 485 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 486 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 487 .mpllb_div = 488 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 489 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 490 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 491 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 492 .mpllb_div2 = 493 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 494 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 495 .mpllb_fracn1 = 496 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 497 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 498 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 499 .mpllb_fracn2 = 500 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 501 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 502 .mpllb_sscen = 503 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 504 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 505 .mpllb_sscstep = 506 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 507 }; 508 509 static const struct intel_mpllb_state dg2_edp_r324 = { 510 .clock = 324000, 511 .ref_control = 512 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 513 .mpllb_cp = 514 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 515 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 516 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 517 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 518 .mpllb_div = 519 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 520 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 521 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 522 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 523 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 524 .mpllb_div2 = 525 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 526 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 527 .mpllb_fracn1 = 528 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 529 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 530 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 531 .mpllb_fracn2 = 532 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 534 .mpllb_sscen = 535 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 537 .mpllb_sscstep = 538 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 539 }; 540 541 static const struct intel_mpllb_state dg2_edp_r432 = { 542 .clock = 432000, 543 .ref_control = 544 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 545 .mpllb_cp = 546 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 547 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 548 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 549 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 550 .mpllb_div = 551 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 552 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 553 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 554 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 555 .mpllb_div2 = 556 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 557 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 558 .mpllb_fracn1 = 559 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 560 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 561 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 562 .mpllb_fracn2 = 563 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 564 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 565 .mpllb_sscen = 566 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 567 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 568 .mpllb_sscstep = 569 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 570 }; 571 572 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 573 &dg2_dp_rbr_100, 574 &dg2_edp_r216, 575 &dg2_edp_r243, 576 &dg2_dp_hbr1_100, 577 &dg2_edp_r324, 578 &dg2_edp_r432, 579 &dg2_dp_hbr2_100, 580 &dg2_dp_hbr3_100, 581 NULL, 582 }; 583 584 /* 585 * HDMI link rates with 100 MHz reference clock. 586 */ 587 588 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 589 .clock = 25175, 590 .ref_control = 591 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 592 .mpllb_cp = 593 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 594 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 595 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 596 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 597 .mpllb_div = 598 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 599 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 600 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 601 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 602 .mpllb_div2 = 603 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 604 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 605 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 606 .mpllb_fracn1 = 607 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 608 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 610 .mpllb_fracn2 = 611 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 612 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 613 .mpllb_sscen = 614 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 615 }; 616 617 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 618 .clock = 27000, 619 .ref_control = 620 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 621 .mpllb_cp = 622 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 623 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 624 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 625 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 626 .mpllb_div = 627 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 628 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 629 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 630 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 631 .mpllb_div2 = 632 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 633 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 634 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 635 .mpllb_fracn1 = 636 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 637 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 638 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 639 .mpllb_fracn2 = 640 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 641 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 642 .mpllb_sscen = 643 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 644 }; 645 646 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 647 .clock = 74250, 648 .ref_control = 649 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 650 .mpllb_cp = 651 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 653 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 654 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 655 .mpllb_div = 656 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 657 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 658 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 659 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 660 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 661 .mpllb_div2 = 662 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 663 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 664 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 665 .mpllb_fracn1 = 666 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 667 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 668 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 669 .mpllb_fracn2 = 670 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 671 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 672 .mpllb_sscen = 673 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 674 }; 675 676 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 677 .clock = 148500, 678 .ref_control = 679 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 680 .mpllb_cp = 681 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 683 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 684 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 685 .mpllb_div = 686 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 687 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 688 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 689 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 690 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 691 .mpllb_div2 = 692 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 693 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 694 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 695 .mpllb_fracn1 = 696 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 697 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 698 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 699 .mpllb_fracn2 = 700 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 701 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 702 .mpllb_sscen = 703 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 704 }; 705 706 static const struct intel_mpllb_state dg2_hdmi_594 = { 707 .clock = 594000, 708 .ref_control = 709 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 710 .mpllb_cp = 711 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 713 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 714 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 715 .mpllb_div = 716 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 717 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 718 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 719 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 720 .mpllb_div2 = 721 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 722 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 723 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 724 .mpllb_fracn1 = 725 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 726 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 727 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 728 .mpllb_fracn2 = 729 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 730 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 731 .mpllb_sscen = 732 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 733 }; 734 735 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 736 &dg2_hdmi_25_175, 737 &dg2_hdmi_27_0, 738 &dg2_hdmi_74_25, 739 &dg2_hdmi_148_5, 740 &dg2_hdmi_594, 741 NULL, 742 }; 743 744 static const struct intel_mpllb_state * const * 745 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 746 struct intel_encoder *encoder) 747 { 748 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 749 return dg2_edp_tables; 750 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 751 /* 752 * FIXME: Initially we're just enabling the "combo" outputs on 753 * port A-D. The MPLLB for those ports takes an input from the 754 * "Display Filter PLL" which always has an output frequency 755 * of 100 MHz, hence the use of the _100 tables below. 756 * 757 * Once we enable port TC1 it will either use the same 100 MHz 758 * "Display Filter PLL" (when strapped to support a native 759 * display connection) or different 38.4 MHz "Filter PLL" when 760 * strapped to support a USB connection, so we'll need to check 761 * that to determine which table to use. 762 */ 763 if (0) 764 return dg2_dp_38_4_tables; 765 else 766 return dg2_dp_100_tables; 767 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 768 return dg2_hdmi_tables; 769 } 770 771 MISSING_CASE(encoder->type); 772 return NULL; 773 } 774 775 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 776 struct intel_encoder *encoder) 777 { 778 const struct intel_mpllb_state * const *tables; 779 int i; 780 781 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 782 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) 783 != MODE_OK) { 784 /* 785 * FIXME: Can only support fixed HDMI frequencies 786 * until we have a proper algorithm under a valid 787 * license. 788 */ 789 DRM_DEBUG_KMS("Can't support HDMI link rate %d\n", 790 crtc_state->port_clock); 791 return -EINVAL; 792 } 793 } 794 795 tables = intel_mpllb_tables_get(crtc_state, encoder); 796 if (!tables) 797 return -EINVAL; 798 799 for (i = 0; tables[i]; i++) { 800 if (crtc_state->port_clock <= tables[i]->clock) { 801 crtc_state->mpllb_state = *tables[i]; 802 return 0; 803 } 804 } 805 806 return -EINVAL; 807 } 808 809 void intel_mpllb_enable(struct intel_encoder *encoder, 810 const struct intel_crtc_state *crtc_state) 811 { 812 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 813 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; 814 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 815 i915_reg_t enable_reg = (phy <= PHY_D ? 816 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 817 818 /* 819 * 3. Software programs the following PLL registers for the desired 820 * frequency. 821 */ 822 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 823 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 824 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 825 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 826 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 827 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 828 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 829 830 /* 831 * 4. If the frequency will result in a change to the voltage 832 * requirement, follow the Display Voltage Frequency Switching - 833 * Sequence Before Frequency Change. 834 * 835 * We handle this step in bxt_set_cdclk(). 836 */ 837 838 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 839 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE); 840 841 /* 842 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 843 * will keep the PLL running during the DDI lane programming and any 844 * typeC DP cable disconnect. Do not set the force before enabling the 845 * PLL because that will start the PLL before it has sampled the 846 * divider values. 847 */ 848 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), 849 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 850 851 /* 852 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 853 * is locked at new settings. This register bit is sampling PHY 854 * dp_mpllb_state interface signal. 855 */ 856 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) 857 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy)); 858 859 /* 860 * 11. If the frequency will result in a change to the voltage 861 * requirement, follow the Display Voltage Frequency Switching - 862 * Sequence After Frequency Change. 863 * 864 * We handle this step in bxt_set_cdclk(). 865 */ 866 } 867 868 void intel_mpllb_disable(struct intel_encoder *encoder) 869 { 870 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 871 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 872 i915_reg_t enable_reg = (phy <= PHY_D ? 873 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 874 875 /* 876 * 1. If the frequency will result in a change to the voltage 877 * requirement, follow the Display Voltage Frequency Switching - 878 * Sequence Before Frequency Change. 879 * 880 * We handle this step in bxt_set_cdclk(). 881 */ 882 883 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 884 intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0); 885 886 /* 887 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 888 * This will allow the PLL to stop running. 889 */ 890 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy), 891 SNPS_PHY_MPLLB_FORCE_EN, 0); 892 893 /* 894 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 895 * (dp_txX_ack) that the new transmitter setting request is completed. 896 */ 897 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5)) 898 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy)); 899 900 /* 901 * 6. If the frequency will result in a change to the voltage 902 * requirement, follow the Display Voltage Frequency Switching - 903 * Sequence After Frequency Change. 904 * 905 * We handle this step in bxt_set_cdclk(). 906 */ 907 } 908 909 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 910 const struct intel_mpllb_state *pll_state) 911 { 912 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 913 unsigned int multiplier, tx_clk_div, refclk; 914 bool frac_en; 915 916 if (0) 917 refclk = 38400; 918 else 919 refclk = 100000; 920 921 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 922 923 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 924 925 if (frac_en) { 926 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 927 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 928 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 929 } 930 931 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 932 933 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 934 935 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 936 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 937 10 << (tx_clk_div + 16)); 938 } 939 940 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 941 struct intel_mpllb_state *pll_state) 942 { 943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 944 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 945 946 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); 947 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); 948 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); 949 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); 950 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); 951 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); 952 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); 953 954 /* 955 * REF_CONTROL is under firmware control and never programmed by the 956 * driver; we read it only for sanity checking purposes. The bspec 957 * only tells us the expected value for one field in this register, 958 * so we'll only read out those specific bits here. 959 */ 960 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & 961 SNPS_PHY_REF_CONTROL_REF_RANGE; 962 963 /* 964 * MPLLB_DIV is programmed twice, once with the software-computed 965 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 966 * extra bit during readout so that we return the actual expected 967 * software state. 968 */ 969 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 970 } 971 972 int intel_snps_phy_check_hdmi_link_rate(int clock) 973 { 974 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; 975 int i; 976 977 for (i = 0; tables[i]; i++) { 978 if (clock == tables[i]->clock) 979 return MODE_OK; 980 } 981 982 return MODE_CLOCK_RANGE; 983 } 984