1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/util_macros.h> 7 8 #include "intel_ddi.h" 9 #include "intel_ddi_buf_trans.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_snps_phy.h" 13 #include "intel_snps_phy_regs.h" 14 15 /** 16 * DOC: Synopsis PHY support 17 * 18 * Synopsis PHYs are primarily programmed by looking up magic register values 19 * in tables rather than calculating the necessary values at runtime. 20 * 21 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as 22 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other 23 * platforms and must be programming directly during the modeset sequence 24 * since it is not handled by the shared DPLL framework as on other platforms. 25 */ 26 27 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) 28 { 29 enum phy phy; 30 31 for_each_phy_masked(phy, ~0) { 32 if (!intel_phy_is_snps(i915, phy)) 33 continue; 34 35 if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy), 36 DG2_PHY_DP_TX_ACK_MASK, 25)) 37 drm_err(&i915->drm, "SNPS PHY %c failed to calibrate after 25ms.\n", 38 phy); 39 } 40 } 41 42 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv, 43 enum phy phy, bool enable) 44 { 45 u32 val; 46 47 if (!intel_phy_is_snps(dev_priv, phy)) 48 return; 49 50 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, 51 enable ? 2 : 3); 52 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy), 53 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); 54 } 55 56 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, 57 const struct intel_crtc_state *crtc_state) 58 { 59 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 60 const struct intel_ddi_buf_trans *trans; 61 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 62 int n_entries, ln; 63 64 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 65 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 66 return; 67 68 for (ln = 0; ln < 4; ln++) { 69 int level = intel_ddi_level(encoder, crtc_state, ln); 70 u32 val = 0; 71 72 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); 73 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); 74 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); 75 76 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 77 } 78 } 79 80 /* 81 * Basic DP link rates with 100 MHz reference clock. 82 */ 83 84 static const struct intel_mpllb_state dg2_dp_rbr_100 = { 85 .clock = 162000, 86 .ref_control = 87 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 88 .mpllb_cp = 89 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 90 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 91 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 92 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 93 .mpllb_div = 94 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 95 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 96 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 97 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 98 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 99 .mpllb_div2 = 100 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 101 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 102 .mpllb_fracn1 = 103 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 104 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 105 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 106 .mpllb_fracn2 = 107 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 108 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 109 }; 110 111 static const struct intel_mpllb_state dg2_dp_hbr1_100 = { 112 .clock = 270000, 113 .ref_control = 114 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 115 .mpllb_cp = 116 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 117 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 118 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 119 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 120 .mpllb_div = 121 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 122 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 123 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 124 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 125 .mpllb_div2 = 126 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 127 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 128 .mpllb_fracn1 = 129 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 130 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 131 }; 132 133 static const struct intel_mpllb_state dg2_dp_hbr2_100 = { 134 .clock = 540000, 135 .ref_control = 136 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 137 .mpllb_cp = 138 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 139 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 140 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 141 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 142 .mpllb_div = 143 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 144 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 145 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 146 .mpllb_div2 = 147 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 148 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184), 149 .mpllb_fracn1 = 150 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 151 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 152 }; 153 154 static const struct intel_mpllb_state dg2_dp_hbr3_100 = { 155 .clock = 810000, 156 .ref_control = 157 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 158 .mpllb_cp = 159 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 160 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 161 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 162 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 163 .mpllb_div = 164 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 165 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 166 .mpllb_div2 = 167 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 168 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292), 169 .mpllb_fracn1 = 170 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 171 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 172 }; 173 174 static const struct intel_mpllb_state dg2_dp_uhbr10_100 = { 175 .clock = 1000000, 176 .ref_control = 177 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 178 .mpllb_cp = 179 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 180 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) | 181 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 182 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 183 .mpllb_div = 184 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 185 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 186 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 187 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 188 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 189 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 190 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 191 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 192 .mpllb_div2 = 193 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 194 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368), 195 .mpllb_fracn1 = 196 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 197 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 198 199 /* 200 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 201 */ 202 .mpllb_sscen = 203 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 204 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982), 205 .mpllb_sscstep = 206 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), 207 }; 208 209 static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { 210 .clock = 1350000, 211 .ref_control = 212 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 213 .mpllb_cp = 214 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 215 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | 216 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 217 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 218 .mpllb_div = 219 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 220 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 221 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 222 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 223 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 224 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 225 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 226 .mpllb_div2 = 227 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 228 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), 229 .mpllb_fracn1 = 230 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 231 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 232 233 /* 234 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 235 */ 236 .mpllb_sscen = 237 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 238 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), 239 .mpllb_sscstep = 240 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), 241 }; 242 243 static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { 244 &dg2_dp_rbr_100, 245 &dg2_dp_hbr1_100, 246 &dg2_dp_hbr2_100, 247 &dg2_dp_hbr3_100, 248 &dg2_dp_uhbr10_100, 249 &dg2_dp_uhbr13_100, 250 NULL, 251 }; 252 253 /* 254 * Basic DP link rates with 38.4 MHz reference clock. 255 */ 256 257 static const struct intel_mpllb_state dg2_dp_rbr_38_4 = { 258 .clock = 162000, 259 .ref_control = 260 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 261 .mpllb_cp = 262 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 263 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 264 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 265 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 266 .mpllb_div = 267 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 268 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 269 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 270 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 271 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 272 .mpllb_div2 = 273 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 274 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304), 275 .mpllb_fracn1 = 276 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 277 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 278 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 279 .mpllb_fracn2 = 280 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152), 281 }; 282 283 static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = { 284 .clock = 270000, 285 .ref_control = 286 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 287 .mpllb_cp = 288 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 289 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 290 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 291 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 292 .mpllb_div = 293 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 294 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 295 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 296 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 297 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 298 .mpllb_div2 = 299 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 300 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 301 .mpllb_fracn1 = 302 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 303 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 304 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 305 .mpllb_fracn2 = 306 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 307 }; 308 309 static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = { 310 .clock = 540000, 311 .ref_control = 312 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 313 .mpllb_cp = 314 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 315 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) | 316 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 317 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 318 .mpllb_div = 319 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 320 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 321 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 322 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 323 .mpllb_div2 = 324 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 325 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248), 326 .mpllb_fracn1 = 327 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 328 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 329 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 330 .mpllb_fracn2 = 331 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960), 332 }; 333 334 static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = { 335 .clock = 810000, 336 .ref_control = 337 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 338 .mpllb_cp = 339 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 340 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 341 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 342 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 343 .mpllb_div = 344 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 345 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 346 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 347 .mpllb_div2 = 348 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 349 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388), 350 .mpllb_fracn1 = 351 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 352 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 353 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 354 .mpllb_fracn2 = 355 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440), 356 }; 357 358 static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = { 359 .clock = 1000000, 360 .ref_control = 361 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 362 .mpllb_cp = 363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) | 365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 366 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 367 .mpllb_div = 368 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 369 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 370 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 371 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 372 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 373 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 374 REG_FIELD_PREP(SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL, 1) | 375 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 376 .mpllb_div2 = 377 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 378 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488), 379 .mpllb_fracn1 = 380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 381 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 382 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3), 383 .mpllb_fracn2 = 384 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) | 385 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306), 386 387 /* 388 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 389 */ 390 .mpllb_sscen = 391 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 392 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800), 393 .mpllb_sscstep = 394 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024), 395 }; 396 397 static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = { 398 .clock = 1350000, 399 .ref_control = 400 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1), 401 .mpllb_cp = 402 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | 403 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) | 404 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 405 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 406 .mpllb_div = 407 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 408 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | 409 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | 410 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 411 REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | 412 REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | 413 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), 414 .mpllb_div2 = 415 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 416 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670), 417 .mpllb_fracn1 = 418 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 419 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 420 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), 421 .mpllb_fracn2 = 422 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864), 423 424 /* 425 * SSC will be enabled, DP UHBR has a minimum SSC requirement. 426 */ 427 .mpllb_sscen = 428 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 429 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680), 430 .mpllb_sscstep = 431 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182), 432 }; 433 434 static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = { 435 &dg2_dp_rbr_38_4, 436 &dg2_dp_hbr1_38_4, 437 &dg2_dp_hbr2_38_4, 438 &dg2_dp_hbr3_38_4, 439 &dg2_dp_uhbr10_38_4, 440 &dg2_dp_uhbr13_38_4, 441 NULL, 442 }; 443 444 /* 445 * eDP link rates with 100 MHz reference clock. 446 */ 447 448 static const struct intel_mpllb_state dg2_edp_r216 = { 449 .clock = 216000, 450 .ref_control = 451 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 452 .mpllb_cp = 453 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 454 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 455 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 456 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 457 .mpllb_div = 458 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 459 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 460 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 461 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 462 .mpllb_div2 = 463 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 464 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 465 .mpllb_fracn1 = 466 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 467 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 468 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 469 .mpllb_fracn2 = 470 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 471 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 472 .mpllb_sscen = 473 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 474 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 475 .mpllb_sscstep = 476 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 477 }; 478 479 static const struct intel_mpllb_state dg2_edp_r243 = { 480 .clock = 243000, 481 .ref_control = 482 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 483 .mpllb_cp = 484 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 485 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 486 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 487 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 488 .mpllb_div = 489 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 490 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 491 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 492 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 493 .mpllb_div2 = 494 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 495 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356), 496 .mpllb_fracn1 = 497 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 498 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 499 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 500 .mpllb_fracn2 = 501 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 502 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 503 .mpllb_sscen = 504 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 505 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331), 506 .mpllb_sscstep = 507 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971), 508 }; 509 510 static const struct intel_mpllb_state dg2_edp_r324 = { 511 .clock = 324000, 512 .ref_control = 513 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 514 .mpllb_cp = 515 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 516 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) | 517 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 518 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 519 .mpllb_div = 520 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 521 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 522 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 523 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 524 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), 525 .mpllb_div2 = 526 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 527 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226), 528 .mpllb_fracn1 = 529 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 530 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 531 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 532 .mpllb_fracn2 = 533 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | 534 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3), 535 .mpllb_sscen = 536 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 537 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221), 538 .mpllb_sscstep = 539 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314), 540 }; 541 542 static const struct intel_mpllb_state dg2_edp_r432 = { 543 .clock = 432000, 544 .ref_control = 545 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 546 .mpllb_cp = 547 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 548 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) | 549 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | 550 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), 551 .mpllb_div = 552 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 553 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | 554 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 555 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 556 .mpllb_div2 = 557 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | 558 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312), 559 .mpllb_fracn1 = 560 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 561 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 562 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 563 .mpllb_fracn2 = 564 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | 565 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4), 566 .mpllb_sscen = 567 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | 568 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961), 569 .mpllb_sscstep = 570 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752), 571 }; 572 573 static const struct intel_mpllb_state * const dg2_edp_tables[] = { 574 &dg2_dp_rbr_100, 575 &dg2_edp_r216, 576 &dg2_edp_r243, 577 &dg2_dp_hbr1_100, 578 &dg2_edp_r324, 579 &dg2_edp_r432, 580 &dg2_dp_hbr2_100, 581 &dg2_dp_hbr3_100, 582 NULL, 583 }; 584 585 /* 586 * HDMI link rates with 100 MHz reference clock. 587 */ 588 589 static const struct intel_mpllb_state dg2_hdmi_25_175 = { 590 .clock = 25175, 591 .ref_control = 592 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 593 .mpllb_cp = 594 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 595 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 596 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 597 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 598 .mpllb_div = 599 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 600 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 601 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 602 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 603 .mpllb_div2 = 604 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 605 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | 606 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 607 .mpllb_fracn1 = 608 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 610 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143), 611 .mpllb_fracn2 = 612 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) | 613 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71), 614 .mpllb_sscen = 615 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 616 }; 617 618 static const struct intel_mpllb_state dg2_hdmi_27_0 = { 619 .clock = 27000, 620 .ref_control = 621 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 622 .mpllb_cp = 623 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | 624 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 625 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 626 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 627 .mpllb_div = 628 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 629 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | 630 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 631 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2), 632 .mpllb_div2 = 633 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 634 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | 635 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 636 .mpllb_fracn1 = 637 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 638 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 639 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 640 .mpllb_fracn2 = 641 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 642 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 643 .mpllb_sscen = 644 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 645 }; 646 647 static const struct intel_mpllb_state dg2_hdmi_74_25 = { 648 .clock = 74250, 649 .ref_control = 650 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 651 .mpllb_cp = 652 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 653 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 654 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 655 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 656 .mpllb_div = 657 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 658 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | 659 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 660 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 661 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 662 .mpllb_div2 = 663 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 664 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 665 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 666 .mpllb_fracn1 = 667 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 668 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 669 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 670 .mpllb_fracn2 = 671 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 672 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 673 .mpllb_sscen = 674 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 675 }; 676 677 static const struct intel_mpllb_state dg2_hdmi_148_5 = { 678 .clock = 148500, 679 .ref_control = 680 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 681 .mpllb_cp = 682 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 683 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 684 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 685 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 686 .mpllb_div = 687 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 688 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | 689 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 690 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 691 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 692 .mpllb_div2 = 693 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 694 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 695 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 696 .mpllb_fracn1 = 697 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 698 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 699 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 700 .mpllb_fracn2 = 701 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 702 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 703 .mpllb_sscen = 704 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 705 }; 706 707 static const struct intel_mpllb_state dg2_hdmi_594 = { 708 .clock = 594000, 709 .ref_control = 710 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), 711 .mpllb_cp = 712 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) | 713 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | 714 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | 715 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), 716 .mpllb_div = 717 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | 718 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | 719 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | 720 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), 721 .mpllb_div2 = 722 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | 723 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | 724 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), 725 .mpllb_fracn1 = 726 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | 727 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | 728 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5), 729 .mpllb_fracn2 = 730 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | 731 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2), 732 .mpllb_sscen = 733 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), 734 }; 735 736 static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { 737 &dg2_hdmi_25_175, 738 &dg2_hdmi_27_0, 739 &dg2_hdmi_74_25, 740 &dg2_hdmi_148_5, 741 &dg2_hdmi_594, 742 NULL, 743 }; 744 745 static const struct intel_mpllb_state * const * 746 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, 747 struct intel_encoder *encoder) 748 { 749 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 750 return dg2_edp_tables; 751 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 752 /* 753 * FIXME: Initially we're just enabling the "combo" outputs on 754 * port A-D. The MPLLB for those ports takes an input from the 755 * "Display Filter PLL" which always has an output frequency 756 * of 100 MHz, hence the use of the _100 tables below. 757 * 758 * Once we enable port TC1 it will either use the same 100 MHz 759 * "Display Filter PLL" (when strapped to support a native 760 * display connection) or different 38.4 MHz "Filter PLL" when 761 * strapped to support a USB connection, so we'll need to check 762 * that to determine which table to use. 763 */ 764 if (0) 765 return dg2_dp_38_4_tables; 766 else 767 return dg2_dp_100_tables; 768 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 769 return dg2_hdmi_tables; 770 } 771 772 MISSING_CASE(encoder->type); 773 return NULL; 774 } 775 776 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 777 struct intel_encoder *encoder) 778 { 779 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 780 const struct intel_mpllb_state * const *tables; 781 int i; 782 783 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 784 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) 785 != MODE_OK) { 786 /* 787 * FIXME: Can only support fixed HDMI frequencies 788 * until we have a proper algorithm under a valid 789 * license. 790 */ 791 drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n", 792 crtc_state->port_clock); 793 return -EINVAL; 794 } 795 } 796 797 tables = intel_mpllb_tables_get(crtc_state, encoder); 798 if (!tables) 799 return -EINVAL; 800 801 for (i = 0; tables[i]; i++) { 802 if (crtc_state->port_clock <= tables[i]->clock) { 803 crtc_state->mpllb_state = *tables[i]; 804 return 0; 805 } 806 } 807 808 return -EINVAL; 809 } 810 811 void intel_mpllb_enable(struct intel_encoder *encoder, 812 const struct intel_crtc_state *crtc_state) 813 { 814 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 815 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state; 816 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 817 i915_reg_t enable_reg = (phy <= PHY_D ? 818 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 819 820 /* 821 * 3. Software programs the following PLL registers for the desired 822 * frequency. 823 */ 824 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 825 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 826 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 827 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 828 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 829 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 830 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 831 832 /* 833 * 4. If the frequency will result in a change to the voltage 834 * requirement, follow the Display Voltage Frequency Switching - 835 * Sequence Before Frequency Change. 836 * 837 * We handle this step in bxt_set_cdclk(). 838 */ 839 840 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ 841 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE); 842 843 /* 844 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This 845 * will keep the PLL running during the DDI lane programming and any 846 * typeC DP cable disconnect. Do not set the force before enabling the 847 * PLL because that will start the PLL before it has sampled the 848 * divider values. 849 */ 850 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), 851 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); 852 853 /* 854 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL 855 * is locked at new settings. This register bit is sampling PHY 856 * dp_mpllb_state interface signal. 857 */ 858 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) 859 drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy)); 860 861 /* 862 * 11. If the frequency will result in a change to the voltage 863 * requirement, follow the Display Voltage Frequency Switching - 864 * Sequence After Frequency Change. 865 * 866 * We handle this step in bxt_set_cdclk(). 867 */ 868 } 869 870 void intel_mpllb_disable(struct intel_encoder *encoder) 871 { 872 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 873 enum phy phy = intel_port_to_phy(i915, encoder->port); 874 i915_reg_t enable_reg = (phy <= PHY_D ? 875 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); 876 877 /* 878 * 1. If the frequency will result in a change to the voltage 879 * requirement, follow the Display Voltage Frequency Switching - 880 * Sequence Before Frequency Change. 881 * 882 * We handle this step in bxt_set_cdclk(). 883 */ 884 885 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ 886 intel_uncore_rmw(&i915->uncore, enable_reg, PLL_ENABLE, 0); 887 888 /* 889 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". 890 * This will allow the PLL to stop running. 891 */ 892 intel_uncore_rmw(&i915->uncore, SNPS_PHY_MPLLB_DIV(phy), 893 SNPS_PHY_MPLLB_FORCE_EN, 0); 894 895 /* 896 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment 897 * (dp_txX_ack) that the new transmitter setting request is completed. 898 */ 899 if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5)) 900 drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy)); 901 902 /* 903 * 6. If the frequency will result in a change to the voltage 904 * requirement, follow the Display Voltage Frequency Switching - 905 * Sequence After Frequency Change. 906 * 907 * We handle this step in bxt_set_cdclk(). 908 */ 909 } 910 911 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, 912 const struct intel_mpllb_state *pll_state) 913 { 914 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 915 unsigned int multiplier, tx_clk_div, refclk; 916 bool frac_en; 917 918 if (0) 919 refclk = 38400; 920 else 921 refclk = 100000; 922 923 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1; 924 925 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1); 926 927 if (frac_en) { 928 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2); 929 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2); 930 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1); 931 } 932 933 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16; 934 935 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div); 936 937 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 938 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 939 10 << (tx_clk_div + 16)); 940 } 941 942 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, 943 struct intel_mpllb_state *pll_state) 944 { 945 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 946 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 947 948 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); 949 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); 950 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); 951 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); 952 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); 953 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); 954 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); 955 956 /* 957 * REF_CONTROL is under firmware control and never programmed by the 958 * driver; we read it only for sanity checking purposes. The bspec 959 * only tells us the expected value for one field in this register, 960 * so we'll only read out those specific bits here. 961 */ 962 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & 963 SNPS_PHY_REF_CONTROL_REF_RANGE; 964 965 /* 966 * MPLLB_DIV is programmed twice, once with the software-computed 967 * state, then again with the MPLLB_FORCE_EN bit added. Drop that 968 * extra bit during readout so that we return the actual expected 969 * software state. 970 */ 971 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; 972 } 973 974 int intel_snps_phy_check_hdmi_link_rate(int clock) 975 { 976 const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; 977 int i; 978 979 for (i = 0; tables[i]; i++) { 980 if (clock == tables[i]->clock) 981 return MODE_OK; 982 } 983 984 return MODE_CLOCK_RANGE; 985 } 986