1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "intel_atomic.h" 43 #include "intel_connector.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_gmbus.h" 47 #include "intel_lvds.h" 48 #include "intel_panel.h" 49 50 /* Private structure for the integrated LVDS support */ 51 struct intel_lvds_pps { 52 /* 100us units */ 53 int t1_t2; 54 int t3; 55 int t4; 56 int t5; 57 int tx; 58 59 int divider; 60 61 int port; 62 bool powerdown_on_reset; 63 }; 64 65 struct intel_lvds_encoder { 66 struct intel_encoder base; 67 68 bool is_dual_link; 69 i915_reg_t reg; 70 u32 a3_power; 71 72 struct intel_lvds_pps init_pps; 73 u32 init_lvds_val; 74 75 struct intel_connector *attached_connector; 76 }; 77 78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 79 { 80 return container_of(encoder, struct intel_lvds_encoder, base.base); 81 } 82 83 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 84 i915_reg_t lvds_reg, enum pipe *pipe) 85 { 86 u32 val; 87 88 val = intel_de_read(dev_priv, lvds_reg); 89 90 /* asserts want to know the pipe even if the port is disabled */ 91 if (HAS_PCH_CPT(dev_priv)) 92 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 93 else 94 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 95 96 return val & LVDS_PORT_EN; 97 } 98 99 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 100 enum pipe *pipe) 101 { 102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 103 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 104 intel_wakeref_t wakeref; 105 bool ret; 106 107 wakeref = intel_display_power_get_if_enabled(dev_priv, 108 encoder->power_domain); 109 if (!wakeref) 110 return false; 111 112 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 113 114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 115 116 return ret; 117 } 118 119 static void intel_lvds_get_config(struct intel_encoder *encoder, 120 struct intel_crtc_state *pipe_config) 121 { 122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 123 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 124 u32 tmp, flags = 0; 125 126 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 127 128 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 129 if (tmp & LVDS_HSYNC_POLARITY) 130 flags |= DRM_MODE_FLAG_NHSYNC; 131 else 132 flags |= DRM_MODE_FLAG_PHSYNC; 133 if (tmp & LVDS_VSYNC_POLARITY) 134 flags |= DRM_MODE_FLAG_NVSYNC; 135 else 136 flags |= DRM_MODE_FLAG_PVSYNC; 137 138 pipe_config->hw.adjusted_mode.flags |= flags; 139 140 if (DISPLAY_VER(dev_priv) < 5) 141 pipe_config->gmch_pfit.lvds_border_bits = 142 tmp & LVDS_BORDER_ENABLE; 143 144 /* gen2/3 store dither state in pfit control, needs to match */ 145 if (DISPLAY_VER(dev_priv) < 4) { 146 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 147 148 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 149 } 150 151 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 152 } 153 154 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 155 struct intel_lvds_pps *pps) 156 { 157 u32 val; 158 159 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 160 161 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 162 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 163 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 164 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 165 166 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 167 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 168 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 169 170 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 171 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 172 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 173 /* 174 * Remove the BSpec specified +1 (100ms) offset that accounts for a 175 * too short power-cycle delay due to the asynchronous programming of 176 * the register. 177 */ 178 if (val) 179 val--; 180 /* Convert from 100ms to 100us units */ 181 pps->t4 = val * 1000; 182 183 if (DISPLAY_VER(dev_priv) <= 4 && 184 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 185 drm_dbg_kms(&dev_priv->drm, 186 "Panel power timings uninitialized, " 187 "setting defaults\n"); 188 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 189 pps->t1_t2 = 40 * 10; 190 pps->t5 = 200 * 10; 191 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 192 pps->t3 = 35 * 10; 193 pps->tx = 200 * 10; 194 } 195 196 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 197 "divider %d port %d powerdown_on_reset %d\n", 198 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 199 pps->divider, pps->port, pps->powerdown_on_reset); 200 } 201 202 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 203 struct intel_lvds_pps *pps) 204 { 205 u32 val; 206 207 val = intel_de_read(dev_priv, PP_CONTROL(0)); 208 drm_WARN_ON(&dev_priv->drm, 209 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 210 if (pps->powerdown_on_reset) 211 val |= PANEL_POWER_RESET; 212 intel_de_write(dev_priv, PP_CONTROL(0), val); 213 214 intel_de_write(dev_priv, PP_ON_DELAYS(0), 215 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 216 217 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 218 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 219 220 intel_de_write(dev_priv, PP_DIVISOR(0), 221 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 222 } 223 224 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 225 struct intel_encoder *encoder, 226 const struct intel_crtc_state *pipe_config, 227 const struct drm_connector_state *conn_state) 228 { 229 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 230 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 231 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 232 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 233 enum pipe pipe = crtc->pipe; 234 u32 temp; 235 236 if (HAS_PCH_SPLIT(dev_priv)) { 237 assert_fdi_rx_pll_disabled(dev_priv, pipe); 238 assert_shared_dpll_disabled(dev_priv, 239 pipe_config->shared_dpll); 240 } else { 241 assert_pll_disabled(dev_priv, pipe); 242 } 243 244 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 245 246 temp = lvds_encoder->init_lvds_val; 247 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 248 249 if (HAS_PCH_CPT(dev_priv)) { 250 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 251 temp |= LVDS_PIPE_SEL_CPT(pipe); 252 } else { 253 temp &= ~LVDS_PIPE_SEL_MASK; 254 temp |= LVDS_PIPE_SEL(pipe); 255 } 256 257 /* set the corresponsding LVDS_BORDER bit */ 258 temp &= ~LVDS_BORDER_ENABLE; 259 temp |= pipe_config->gmch_pfit.lvds_border_bits; 260 261 /* 262 * Set the B0-B3 data pairs corresponding to whether we're going to 263 * set the DPLLs for dual-channel mode or not. 264 */ 265 if (lvds_encoder->is_dual_link) 266 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 267 else 268 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 269 270 /* 271 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 272 * appropriately here, but we need to look more thoroughly into how 273 * panels behave in the two modes. For now, let's just maintain the 274 * value we got from the BIOS. 275 */ 276 temp &= ~LVDS_A3_POWER_MASK; 277 temp |= lvds_encoder->a3_power; 278 279 /* 280 * Set the dithering flag on LVDS as needed, note that there is no 281 * special lvds dither control bit on pch-split platforms, dithering is 282 * only controlled through the PIPECONF reg. 283 */ 284 if (DISPLAY_VER(dev_priv) == 4) { 285 /* 286 * Bspec wording suggests that LVDS port dithering only exists 287 * for 18bpp panels. 288 */ 289 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 290 temp |= LVDS_ENABLE_DITHER; 291 else 292 temp &= ~LVDS_ENABLE_DITHER; 293 } 294 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 295 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 296 temp |= LVDS_HSYNC_POLARITY; 297 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 298 temp |= LVDS_VSYNC_POLARITY; 299 300 intel_de_write(dev_priv, lvds_encoder->reg, temp); 301 } 302 303 /* 304 * Sets the power state for the panel. 305 */ 306 static void intel_enable_lvds(struct intel_atomic_state *state, 307 struct intel_encoder *encoder, 308 const struct intel_crtc_state *pipe_config, 309 const struct drm_connector_state *conn_state) 310 { 311 struct drm_device *dev = encoder->base.dev; 312 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 313 struct drm_i915_private *dev_priv = to_i915(dev); 314 315 intel_de_write(dev_priv, lvds_encoder->reg, 316 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 317 318 intel_de_write(dev_priv, PP_CONTROL(0), 319 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 320 intel_de_posting_read(dev_priv, lvds_encoder->reg); 321 322 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 323 drm_err(&dev_priv->drm, 324 "timed out waiting for panel to power on\n"); 325 326 intel_panel_enable_backlight(pipe_config, conn_state); 327 } 328 329 static void intel_disable_lvds(struct intel_atomic_state *state, 330 struct intel_encoder *encoder, 331 const struct intel_crtc_state *old_crtc_state, 332 const struct drm_connector_state *old_conn_state) 333 { 334 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 336 337 intel_de_write(dev_priv, PP_CONTROL(0), 338 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 339 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 340 drm_err(&dev_priv->drm, 341 "timed out waiting for panel to power off\n"); 342 343 intel_de_write(dev_priv, lvds_encoder->reg, 344 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 345 intel_de_posting_read(dev_priv, lvds_encoder->reg); 346 } 347 348 static void gmch_disable_lvds(struct intel_atomic_state *state, 349 struct intel_encoder *encoder, 350 const struct intel_crtc_state *old_crtc_state, 351 const struct drm_connector_state *old_conn_state) 352 353 { 354 intel_panel_disable_backlight(old_conn_state); 355 356 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 357 } 358 359 static void pch_disable_lvds(struct intel_atomic_state *state, 360 struct intel_encoder *encoder, 361 const struct intel_crtc_state *old_crtc_state, 362 const struct drm_connector_state *old_conn_state) 363 { 364 intel_panel_disable_backlight(old_conn_state); 365 } 366 367 static void pch_post_disable_lvds(struct intel_atomic_state *state, 368 struct intel_encoder *encoder, 369 const struct intel_crtc_state *old_crtc_state, 370 const struct drm_connector_state *old_conn_state) 371 { 372 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 373 } 374 375 static void intel_lvds_shutdown(struct intel_encoder *encoder) 376 { 377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 378 379 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 380 drm_err(&dev_priv->drm, 381 "timed out waiting for panel power cycle delay\n"); 382 } 383 384 static enum drm_mode_status 385 intel_lvds_mode_valid(struct drm_connector *connector, 386 struct drm_display_mode *mode) 387 { 388 struct intel_connector *intel_connector = to_intel_connector(connector); 389 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 390 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 391 392 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 393 return MODE_NO_DBLESCAN; 394 if (mode->hdisplay > fixed_mode->hdisplay) 395 return MODE_PANEL; 396 if (mode->vdisplay > fixed_mode->vdisplay) 397 return MODE_PANEL; 398 if (fixed_mode->clock > max_pixclk) 399 return MODE_CLOCK_HIGH; 400 401 return MODE_OK; 402 } 403 404 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 405 struct intel_crtc_state *pipe_config, 406 struct drm_connector_state *conn_state) 407 { 408 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 409 struct intel_lvds_encoder *lvds_encoder = 410 to_lvds_encoder(&intel_encoder->base); 411 struct intel_connector *intel_connector = 412 lvds_encoder->attached_connector; 413 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 414 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 415 unsigned int lvds_bpp; 416 int ret; 417 418 /* Should never happen!! */ 419 if (DISPLAY_VER(dev_priv) < 4 && intel_crtc->pipe == 0) { 420 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); 421 return -EINVAL; 422 } 423 424 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 425 lvds_bpp = 8*3; 426 else 427 lvds_bpp = 6*3; 428 429 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 430 drm_dbg_kms(&dev_priv->drm, 431 "forcing display bpp (was %d) to LVDS (%d)\n", 432 pipe_config->pipe_bpp, lvds_bpp); 433 pipe_config->pipe_bpp = lvds_bpp; 434 } 435 436 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 437 438 /* 439 * We have timings from the BIOS for the panel, put them in 440 * to the adjusted mode. The CRTC will be set up for this mode, 441 * with the panel scaling set up to source from the H/VDisplay 442 * of the original mode. 443 */ 444 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 445 adjusted_mode); 446 447 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 448 return -EINVAL; 449 450 if (HAS_PCH_SPLIT(dev_priv)) 451 pipe_config->has_pch_encoder = true; 452 453 if (HAS_GMCH(dev_priv)) 454 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 455 else 456 ret = intel_pch_panel_fitting(pipe_config, conn_state); 457 if (ret) 458 return ret; 459 460 /* 461 * XXX: It would be nice to support lower refresh rates on the 462 * panels to reduce power consumption, and perhaps match the 463 * user's requested refresh rate. 464 */ 465 466 return 0; 467 } 468 469 /* 470 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 471 */ 472 static int intel_lvds_get_modes(struct drm_connector *connector) 473 { 474 struct intel_connector *intel_connector = to_intel_connector(connector); 475 struct drm_device *dev = connector->dev; 476 struct drm_display_mode *mode; 477 478 /* use cached edid if we have one */ 479 if (!IS_ERR_OR_NULL(intel_connector->edid)) 480 return drm_add_edid_modes(connector, intel_connector->edid); 481 482 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); 483 if (mode == NULL) 484 return 0; 485 486 drm_mode_probed_add(connector, mode); 487 return 1; 488 } 489 490 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 491 .get_modes = intel_lvds_get_modes, 492 .mode_valid = intel_lvds_mode_valid, 493 .atomic_check = intel_digital_connector_atomic_check, 494 }; 495 496 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 497 .detect = intel_panel_detect, 498 .fill_modes = drm_helper_probe_single_connector_modes, 499 .atomic_get_property = intel_digital_connector_atomic_get_property, 500 .atomic_set_property = intel_digital_connector_atomic_set_property, 501 .late_register = intel_connector_register, 502 .early_unregister = intel_connector_unregister, 503 .destroy = intel_connector_destroy, 504 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 505 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 506 }; 507 508 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 509 .destroy = intel_encoder_destroy, 510 }; 511 512 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 513 { 514 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 515 return 1; 516 } 517 518 /* These systems claim to have LVDS, but really don't */ 519 static const struct dmi_system_id intel_no_lvds[] = { 520 { 521 .callback = intel_no_lvds_dmi_callback, 522 .ident = "Apple Mac Mini (Core series)", 523 .matches = { 524 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 525 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 526 }, 527 }, 528 { 529 .callback = intel_no_lvds_dmi_callback, 530 .ident = "Apple Mac Mini (Core 2 series)", 531 .matches = { 532 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 533 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 534 }, 535 }, 536 { 537 .callback = intel_no_lvds_dmi_callback, 538 .ident = "MSI IM-945GSE-A", 539 .matches = { 540 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 541 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 542 }, 543 }, 544 { 545 .callback = intel_no_lvds_dmi_callback, 546 .ident = "Dell Studio Hybrid", 547 .matches = { 548 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 549 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 550 }, 551 }, 552 { 553 .callback = intel_no_lvds_dmi_callback, 554 .ident = "Dell OptiPlex FX170", 555 .matches = { 556 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 557 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 558 }, 559 }, 560 { 561 .callback = intel_no_lvds_dmi_callback, 562 .ident = "AOpen Mini PC", 563 .matches = { 564 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 565 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 566 }, 567 }, 568 { 569 .callback = intel_no_lvds_dmi_callback, 570 .ident = "AOpen Mini PC MP915", 571 .matches = { 572 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 573 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 574 }, 575 }, 576 { 577 .callback = intel_no_lvds_dmi_callback, 578 .ident = "AOpen i915GMm-HFS", 579 .matches = { 580 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 581 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 582 }, 583 }, 584 { 585 .callback = intel_no_lvds_dmi_callback, 586 .ident = "AOpen i45GMx-I", 587 .matches = { 588 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 589 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 590 }, 591 }, 592 { 593 .callback = intel_no_lvds_dmi_callback, 594 .ident = "Aopen i945GTt-VFA", 595 .matches = { 596 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 597 }, 598 }, 599 { 600 .callback = intel_no_lvds_dmi_callback, 601 .ident = "Clientron U800", 602 .matches = { 603 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 604 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 605 }, 606 }, 607 { 608 .callback = intel_no_lvds_dmi_callback, 609 .ident = "Clientron E830", 610 .matches = { 611 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 612 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 613 }, 614 }, 615 { 616 .callback = intel_no_lvds_dmi_callback, 617 .ident = "Asus EeeBox PC EB1007", 618 .matches = { 619 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 620 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 621 }, 622 }, 623 { 624 .callback = intel_no_lvds_dmi_callback, 625 .ident = "Asus AT5NM10T-I", 626 .matches = { 627 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 628 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 629 }, 630 }, 631 { 632 .callback = intel_no_lvds_dmi_callback, 633 .ident = "Hewlett-Packard HP t5740", 634 .matches = { 635 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 636 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 637 }, 638 }, 639 { 640 .callback = intel_no_lvds_dmi_callback, 641 .ident = "Hewlett-Packard t5745", 642 .matches = { 643 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 644 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 645 }, 646 }, 647 { 648 .callback = intel_no_lvds_dmi_callback, 649 .ident = "Hewlett-Packard st5747", 650 .matches = { 651 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 652 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 653 }, 654 }, 655 { 656 .callback = intel_no_lvds_dmi_callback, 657 .ident = "MSI Wind Box DC500", 658 .matches = { 659 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 660 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 661 }, 662 }, 663 { 664 .callback = intel_no_lvds_dmi_callback, 665 .ident = "Gigabyte GA-D525TUD", 666 .matches = { 667 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 668 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 669 }, 670 }, 671 { 672 .callback = intel_no_lvds_dmi_callback, 673 .ident = "Supermicro X7SPA-H", 674 .matches = { 675 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 676 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 677 }, 678 }, 679 { 680 .callback = intel_no_lvds_dmi_callback, 681 .ident = "Fujitsu Esprimo Q900", 682 .matches = { 683 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 684 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 685 }, 686 }, 687 { 688 .callback = intel_no_lvds_dmi_callback, 689 .ident = "Intel D410PT", 690 .matches = { 691 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 692 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 693 }, 694 }, 695 { 696 .callback = intel_no_lvds_dmi_callback, 697 .ident = "Intel D425KT", 698 .matches = { 699 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 700 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 701 }, 702 }, 703 { 704 .callback = intel_no_lvds_dmi_callback, 705 .ident = "Intel D510MO", 706 .matches = { 707 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 708 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 709 }, 710 }, 711 { 712 .callback = intel_no_lvds_dmi_callback, 713 .ident = "Intel D525MW", 714 .matches = { 715 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 716 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 717 }, 718 }, 719 { 720 .callback = intel_no_lvds_dmi_callback, 721 .ident = "Radiant P845", 722 .matches = { 723 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 724 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 725 }, 726 }, 727 728 { } /* terminating entry */ 729 }; 730 731 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 732 { 733 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 734 return 1; 735 } 736 737 static const struct dmi_system_id intel_dual_link_lvds[] = { 738 { 739 .callback = intel_dual_link_lvds_callback, 740 .ident = "Apple MacBook Pro 15\" (2010)", 741 .matches = { 742 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 743 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 744 }, 745 }, 746 { 747 .callback = intel_dual_link_lvds_callback, 748 .ident = "Apple MacBook Pro 15\" (2011)", 749 .matches = { 750 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 751 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 752 }, 753 }, 754 { 755 .callback = intel_dual_link_lvds_callback, 756 .ident = "Apple MacBook Pro 15\" (2012)", 757 .matches = { 758 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 759 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 760 }, 761 }, 762 { } /* terminating entry */ 763 }; 764 765 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 766 { 767 struct intel_encoder *encoder; 768 769 for_each_intel_encoder(&dev_priv->drm, encoder) { 770 if (encoder->type == INTEL_OUTPUT_LVDS) 771 return encoder; 772 } 773 774 return NULL; 775 } 776 777 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 778 { 779 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 780 781 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 782 } 783 784 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 785 { 786 struct drm_device *dev = lvds_encoder->base.base.dev; 787 unsigned int val; 788 struct drm_i915_private *dev_priv = to_i915(dev); 789 790 /* use the module option value if specified */ 791 if (dev_priv->params.lvds_channel_mode > 0) 792 return dev_priv->params.lvds_channel_mode == 2; 793 794 /* single channel LVDS is limited to 112 MHz */ 795 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) 796 return true; 797 798 if (dmi_check_system(intel_dual_link_lvds)) 799 return true; 800 801 /* 802 * BIOS should set the proper LVDS register value at boot, but 803 * in reality, it doesn't set the value when the lid is closed; 804 * we need to check "the value to be set" in VBT when LVDS 805 * register is uninitialized. 806 */ 807 val = intel_de_read(dev_priv, lvds_encoder->reg); 808 if (HAS_PCH_CPT(dev_priv)) 809 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 810 else 811 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 812 if (val == 0) 813 val = dev_priv->vbt.bios_lvds_val; 814 815 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 816 } 817 818 /** 819 * intel_lvds_init - setup LVDS connectors on this device 820 * @dev_priv: i915 device 821 * 822 * Create the connector, register the LVDS DDC bus, and try to figure out what 823 * modes we can display on the LVDS panel (if present). 824 */ 825 void intel_lvds_init(struct drm_i915_private *dev_priv) 826 { 827 struct drm_device *dev = &dev_priv->drm; 828 struct intel_lvds_encoder *lvds_encoder; 829 struct intel_encoder *intel_encoder; 830 struct intel_connector *intel_connector; 831 struct drm_connector *connector; 832 struct drm_encoder *encoder; 833 struct drm_display_mode *fixed_mode = NULL; 834 struct drm_display_mode *downclock_mode = NULL; 835 struct edid *edid; 836 i915_reg_t lvds_reg; 837 u32 lvds; 838 u8 pin; 839 u32 allowed_scalers; 840 841 /* Skip init on machines we know falsely report LVDS */ 842 if (dmi_check_system(intel_no_lvds)) { 843 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, 844 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 845 return; 846 } 847 848 if (!dev_priv->vbt.int_lvds_support) { 849 drm_dbg_kms(&dev_priv->drm, 850 "Internal LVDS support disabled by VBT\n"); 851 return; 852 } 853 854 if (HAS_PCH_SPLIT(dev_priv)) 855 lvds_reg = PCH_LVDS; 856 else 857 lvds_reg = LVDS; 858 859 lvds = intel_de_read(dev_priv, lvds_reg); 860 861 if (HAS_PCH_SPLIT(dev_priv)) { 862 if ((lvds & LVDS_DETECTED) == 0) 863 return; 864 } 865 866 pin = GMBUS_PIN_PANEL; 867 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 868 if ((lvds & LVDS_PORT_EN) == 0) { 869 drm_dbg_kms(&dev_priv->drm, 870 "LVDS is not present in VBT\n"); 871 return; 872 } 873 drm_dbg_kms(&dev_priv->drm, 874 "LVDS is not present in VBT, but enabled anyway\n"); 875 } 876 877 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 878 if (!lvds_encoder) 879 return; 880 881 intel_connector = intel_connector_alloc(); 882 if (!intel_connector) { 883 kfree(lvds_encoder); 884 return; 885 } 886 887 lvds_encoder->attached_connector = intel_connector; 888 889 intel_encoder = &lvds_encoder->base; 890 encoder = &intel_encoder->base; 891 connector = &intel_connector->base; 892 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 893 DRM_MODE_CONNECTOR_LVDS); 894 895 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 896 DRM_MODE_ENCODER_LVDS, "LVDS"); 897 898 intel_encoder->enable = intel_enable_lvds; 899 intel_encoder->pre_enable = intel_pre_enable_lvds; 900 intel_encoder->compute_config = intel_lvds_compute_config; 901 if (HAS_PCH_SPLIT(dev_priv)) { 902 intel_encoder->disable = pch_disable_lvds; 903 intel_encoder->post_disable = pch_post_disable_lvds; 904 } else { 905 intel_encoder->disable = gmch_disable_lvds; 906 } 907 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 908 intel_encoder->get_config = intel_lvds_get_config; 909 intel_encoder->update_pipe = intel_panel_update_backlight; 910 intel_encoder->shutdown = intel_lvds_shutdown; 911 intel_connector->get_hw_state = intel_connector_get_hw_state; 912 913 intel_connector_attach_encoder(intel_connector, intel_encoder); 914 915 intel_encoder->type = INTEL_OUTPUT_LVDS; 916 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 917 intel_encoder->port = PORT_NONE; 918 intel_encoder->cloneable = 0; 919 if (DISPLAY_VER(dev_priv) < 4) 920 intel_encoder->pipe_mask = BIT(PIPE_B); 921 else 922 intel_encoder->pipe_mask = ~0; 923 924 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 925 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 926 connector->interlace_allowed = false; 927 connector->doublescan_allowed = false; 928 929 lvds_encoder->reg = lvds_reg; 930 931 /* create the scaling mode property */ 932 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); 933 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); 934 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 935 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 936 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 937 938 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 939 lvds_encoder->init_lvds_val = lvds; 940 941 /* 942 * LVDS discovery: 943 * 1) check for EDID on DDC 944 * 2) check for VBT data 945 * 3) check to see if LVDS is already on 946 * if none of the above, no panel 947 */ 948 949 /* 950 * Attempt to get the fixed panel mode from DDC. Assume that the 951 * preferred mode is the right one. 952 */ 953 mutex_lock(&dev->mode_config.mutex); 954 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 955 edid = drm_get_edid_switcheroo(connector, 956 intel_gmbus_get_adapter(dev_priv, pin)); 957 else 958 edid = drm_get_edid(connector, 959 intel_gmbus_get_adapter(dev_priv, pin)); 960 if (edid) { 961 if (drm_add_edid_modes(connector, edid)) { 962 drm_connector_update_edid_property(connector, 963 edid); 964 } else { 965 kfree(edid); 966 edid = ERR_PTR(-EINVAL); 967 } 968 } else { 969 edid = ERR_PTR(-ENOENT); 970 } 971 intel_connector->edid = edid; 972 973 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 974 if (fixed_mode) 975 goto out; 976 977 /* Failed to get EDID, what about VBT? */ 978 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 979 if (fixed_mode) 980 goto out; 981 982 /* 983 * If we didn't get EDID, try checking if the panel is already turned 984 * on. If so, assume that whatever is currently programmed is the 985 * correct mode. 986 */ 987 fixed_mode = intel_encoder_current_mode(intel_encoder); 988 if (fixed_mode) { 989 drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: "); 990 drm_mode_debug_printmodeline(fixed_mode); 991 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 992 } 993 994 /* If we still don't have a mode after all that, give up. */ 995 if (!fixed_mode) 996 goto failed; 997 998 out: 999 mutex_unlock(&dev->mode_config.mutex); 1000 1001 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1002 intel_panel_setup_backlight(connector, INVALID_PIPE); 1003 1004 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1005 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", 1006 lvds_encoder->is_dual_link ? "dual" : "single"); 1007 1008 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1009 1010 return; 1011 1012 failed: 1013 mutex_unlock(&dev->mode_config.mutex); 1014 1015 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); 1016 drm_connector_cleanup(connector); 1017 drm_encoder_cleanup(encoder); 1018 kfree(lvds_encoder); 1019 intel_connector_free(intel_connector); 1020 return; 1021 } 1022