1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "intel_atomic.h" 43 #include "intel_connector.h" 44 #include "intel_display_types.h" 45 #include "intel_gmbus.h" 46 #include "intel_lvds.h" 47 #include "intel_panel.h" 48 49 /* Private structure for the integrated LVDS support */ 50 struct intel_lvds_pps { 51 /* 100us units */ 52 int t1_t2; 53 int t3; 54 int t4; 55 int t5; 56 int tx; 57 58 int divider; 59 60 int port; 61 bool powerdown_on_reset; 62 }; 63 64 struct intel_lvds_encoder { 65 struct intel_encoder base; 66 67 bool is_dual_link; 68 i915_reg_t reg; 69 u32 a3_power; 70 71 struct intel_lvds_pps init_pps; 72 u32 init_lvds_val; 73 74 struct intel_connector *attached_connector; 75 }; 76 77 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 78 { 79 return container_of(encoder, struct intel_lvds_encoder, base.base); 80 } 81 82 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 83 i915_reg_t lvds_reg, enum pipe *pipe) 84 { 85 u32 val; 86 87 val = intel_de_read(dev_priv, lvds_reg); 88 89 /* asserts want to know the pipe even if the port is disabled */ 90 if (HAS_PCH_CPT(dev_priv)) 91 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 92 else 93 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 94 95 return val & LVDS_PORT_EN; 96 } 97 98 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 99 enum pipe *pipe) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 103 intel_wakeref_t wakeref; 104 bool ret; 105 106 wakeref = intel_display_power_get_if_enabled(dev_priv, 107 encoder->power_domain); 108 if (!wakeref) 109 return false; 110 111 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 112 113 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 114 115 return ret; 116 } 117 118 static void intel_lvds_get_config(struct intel_encoder *encoder, 119 struct intel_crtc_state *pipe_config) 120 { 121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 122 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 123 u32 tmp, flags = 0; 124 125 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 126 127 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 128 if (tmp & LVDS_HSYNC_POLARITY) 129 flags |= DRM_MODE_FLAG_NHSYNC; 130 else 131 flags |= DRM_MODE_FLAG_PHSYNC; 132 if (tmp & LVDS_VSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NVSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PVSYNC; 136 137 pipe_config->hw.adjusted_mode.flags |= flags; 138 139 if (INTEL_GEN(dev_priv) < 5) 140 pipe_config->gmch_pfit.lvds_border_bits = 141 tmp & LVDS_BORDER_ENABLE; 142 143 /* gen2/3 store dither state in pfit control, needs to match */ 144 if (INTEL_GEN(dev_priv) < 4) { 145 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 146 147 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 148 } 149 150 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 151 } 152 153 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 154 struct intel_lvds_pps *pps) 155 { 156 u32 val; 157 158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 159 160 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 161 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 162 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 163 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 164 165 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 166 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 167 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 168 169 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 170 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 171 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 172 /* 173 * Remove the BSpec specified +1 (100ms) offset that accounts for a 174 * too short power-cycle delay due to the asynchronous programming of 175 * the register. 176 */ 177 if (val) 178 val--; 179 /* Convert from 100ms to 100us units */ 180 pps->t4 = val * 1000; 181 182 if (INTEL_GEN(dev_priv) <= 4 && 183 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 184 drm_dbg_kms(&dev_priv->drm, 185 "Panel power timings uninitialized, " 186 "setting defaults\n"); 187 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 188 pps->t1_t2 = 40 * 10; 189 pps->t5 = 200 * 10; 190 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 191 pps->t3 = 35 * 10; 192 pps->tx = 200 * 10; 193 } 194 195 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 196 "divider %d port %d powerdown_on_reset %d\n", 197 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 198 pps->divider, pps->port, pps->powerdown_on_reset); 199 } 200 201 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 202 struct intel_lvds_pps *pps) 203 { 204 u32 val; 205 206 val = intel_de_read(dev_priv, PP_CONTROL(0)); 207 drm_WARN_ON(&dev_priv->drm, 208 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 209 if (pps->powerdown_on_reset) 210 val |= PANEL_POWER_RESET; 211 intel_de_write(dev_priv, PP_CONTROL(0), val); 212 213 intel_de_write(dev_priv, PP_ON_DELAYS(0), 214 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 215 216 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 217 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 218 219 intel_de_write(dev_priv, PP_DIVISOR(0), 220 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 221 } 222 223 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 224 struct intel_encoder *encoder, 225 const struct intel_crtc_state *pipe_config, 226 const struct drm_connector_state *conn_state) 227 { 228 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 229 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 230 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 231 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 232 enum pipe pipe = crtc->pipe; 233 u32 temp; 234 235 if (HAS_PCH_SPLIT(dev_priv)) { 236 assert_fdi_rx_pll_disabled(dev_priv, pipe); 237 assert_shared_dpll_disabled(dev_priv, 238 pipe_config->shared_dpll); 239 } else { 240 assert_pll_disabled(dev_priv, pipe); 241 } 242 243 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 244 245 temp = lvds_encoder->init_lvds_val; 246 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 247 248 if (HAS_PCH_CPT(dev_priv)) { 249 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 250 temp |= LVDS_PIPE_SEL_CPT(pipe); 251 } else { 252 temp &= ~LVDS_PIPE_SEL_MASK; 253 temp |= LVDS_PIPE_SEL(pipe); 254 } 255 256 /* set the corresponsding LVDS_BORDER bit */ 257 temp &= ~LVDS_BORDER_ENABLE; 258 temp |= pipe_config->gmch_pfit.lvds_border_bits; 259 260 /* 261 * Set the B0-B3 data pairs corresponding to whether we're going to 262 * set the DPLLs for dual-channel mode or not. 263 */ 264 if (lvds_encoder->is_dual_link) 265 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 266 else 267 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 268 269 /* 270 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 271 * appropriately here, but we need to look more thoroughly into how 272 * panels behave in the two modes. For now, let's just maintain the 273 * value we got from the BIOS. 274 */ 275 temp &= ~LVDS_A3_POWER_MASK; 276 temp |= lvds_encoder->a3_power; 277 278 /* 279 * Set the dithering flag on LVDS as needed, note that there is no 280 * special lvds dither control bit on pch-split platforms, dithering is 281 * only controlled through the PIPECONF reg. 282 */ 283 if (IS_GEN(dev_priv, 4)) { 284 /* 285 * Bspec wording suggests that LVDS port dithering only exists 286 * for 18bpp panels. 287 */ 288 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 289 temp |= LVDS_ENABLE_DITHER; 290 else 291 temp &= ~LVDS_ENABLE_DITHER; 292 } 293 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 294 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 295 temp |= LVDS_HSYNC_POLARITY; 296 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 297 temp |= LVDS_VSYNC_POLARITY; 298 299 intel_de_write(dev_priv, lvds_encoder->reg, temp); 300 } 301 302 /* 303 * Sets the power state for the panel. 304 */ 305 static void intel_enable_lvds(struct intel_atomic_state *state, 306 struct intel_encoder *encoder, 307 const struct intel_crtc_state *pipe_config, 308 const struct drm_connector_state *conn_state) 309 { 310 struct drm_device *dev = encoder->base.dev; 311 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 312 struct drm_i915_private *dev_priv = to_i915(dev); 313 314 intel_de_write(dev_priv, lvds_encoder->reg, 315 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 316 317 intel_de_write(dev_priv, PP_CONTROL(0), 318 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 319 intel_de_posting_read(dev_priv, lvds_encoder->reg); 320 321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 322 drm_err(&dev_priv->drm, 323 "timed out waiting for panel to power on\n"); 324 325 intel_panel_enable_backlight(pipe_config, conn_state); 326 } 327 328 static void intel_disable_lvds(struct intel_atomic_state *state, 329 struct intel_encoder *encoder, 330 const struct intel_crtc_state *old_crtc_state, 331 const struct drm_connector_state *old_conn_state) 332 { 333 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 334 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 335 336 intel_de_write(dev_priv, PP_CONTROL(0), 337 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 338 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 339 drm_err(&dev_priv->drm, 340 "timed out waiting for panel to power off\n"); 341 342 intel_de_write(dev_priv, lvds_encoder->reg, 343 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 344 intel_de_posting_read(dev_priv, lvds_encoder->reg); 345 } 346 347 static void gmch_disable_lvds(struct intel_atomic_state *state, 348 struct intel_encoder *encoder, 349 const struct intel_crtc_state *old_crtc_state, 350 const struct drm_connector_state *old_conn_state) 351 352 { 353 intel_panel_disable_backlight(old_conn_state); 354 355 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 356 } 357 358 static void pch_disable_lvds(struct intel_atomic_state *state, 359 struct intel_encoder *encoder, 360 const struct intel_crtc_state *old_crtc_state, 361 const struct drm_connector_state *old_conn_state) 362 { 363 intel_panel_disable_backlight(old_conn_state); 364 } 365 366 static void pch_post_disable_lvds(struct intel_atomic_state *state, 367 struct intel_encoder *encoder, 368 const struct intel_crtc_state *old_crtc_state, 369 const struct drm_connector_state *old_conn_state) 370 { 371 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 372 } 373 374 static void intel_lvds_shutdown(struct intel_encoder *encoder) 375 { 376 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 377 378 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 379 drm_err(&dev_priv->drm, 380 "timed out waiting for panel power cycle delay\n"); 381 } 382 383 static enum drm_mode_status 384 intel_lvds_mode_valid(struct drm_connector *connector, 385 struct drm_display_mode *mode) 386 { 387 struct intel_connector *intel_connector = to_intel_connector(connector); 388 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 389 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 390 391 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 392 return MODE_NO_DBLESCAN; 393 if (mode->hdisplay > fixed_mode->hdisplay) 394 return MODE_PANEL; 395 if (mode->vdisplay > fixed_mode->vdisplay) 396 return MODE_PANEL; 397 if (fixed_mode->clock > max_pixclk) 398 return MODE_CLOCK_HIGH; 399 400 return MODE_OK; 401 } 402 403 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 404 struct intel_crtc_state *pipe_config, 405 struct drm_connector_state *conn_state) 406 { 407 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 408 struct intel_lvds_encoder *lvds_encoder = 409 to_lvds_encoder(&intel_encoder->base); 410 struct intel_connector *intel_connector = 411 lvds_encoder->attached_connector; 412 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 413 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 414 unsigned int lvds_bpp; 415 int ret; 416 417 /* Should never happen!! */ 418 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { 419 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); 420 return -EINVAL; 421 } 422 423 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 424 lvds_bpp = 8*3; 425 else 426 lvds_bpp = 6*3; 427 428 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 429 drm_dbg_kms(&dev_priv->drm, 430 "forcing display bpp (was %d) to LVDS (%d)\n", 431 pipe_config->pipe_bpp, lvds_bpp); 432 pipe_config->pipe_bpp = lvds_bpp; 433 } 434 435 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 436 437 /* 438 * We have timings from the BIOS for the panel, put them in 439 * to the adjusted mode. The CRTC will be set up for this mode, 440 * with the panel scaling set up to source from the H/VDisplay 441 * of the original mode. 442 */ 443 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 444 adjusted_mode); 445 446 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 447 return -EINVAL; 448 449 if (HAS_PCH_SPLIT(dev_priv)) 450 pipe_config->has_pch_encoder = true; 451 452 if (HAS_GMCH(dev_priv)) 453 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 454 else 455 ret = intel_pch_panel_fitting(pipe_config, conn_state); 456 if (ret) 457 return ret; 458 459 /* 460 * XXX: It would be nice to support lower refresh rates on the 461 * panels to reduce power consumption, and perhaps match the 462 * user's requested refresh rate. 463 */ 464 465 return 0; 466 } 467 468 /* 469 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 470 */ 471 static int intel_lvds_get_modes(struct drm_connector *connector) 472 { 473 struct intel_connector *intel_connector = to_intel_connector(connector); 474 struct drm_device *dev = connector->dev; 475 struct drm_display_mode *mode; 476 477 /* use cached edid if we have one */ 478 if (!IS_ERR_OR_NULL(intel_connector->edid)) 479 return drm_add_edid_modes(connector, intel_connector->edid); 480 481 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); 482 if (mode == NULL) 483 return 0; 484 485 drm_mode_probed_add(connector, mode); 486 return 1; 487 } 488 489 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 490 .get_modes = intel_lvds_get_modes, 491 .mode_valid = intel_lvds_mode_valid, 492 .atomic_check = intel_digital_connector_atomic_check, 493 }; 494 495 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 496 .detect = intel_panel_detect, 497 .fill_modes = drm_helper_probe_single_connector_modes, 498 .atomic_get_property = intel_digital_connector_atomic_get_property, 499 .atomic_set_property = intel_digital_connector_atomic_set_property, 500 .late_register = intel_connector_register, 501 .early_unregister = intel_connector_unregister, 502 .destroy = intel_connector_destroy, 503 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 504 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 505 }; 506 507 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 508 .destroy = intel_encoder_destroy, 509 }; 510 511 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 512 { 513 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 514 return 1; 515 } 516 517 /* These systems claim to have LVDS, but really don't */ 518 static const struct dmi_system_id intel_no_lvds[] = { 519 { 520 .callback = intel_no_lvds_dmi_callback, 521 .ident = "Apple Mac Mini (Core series)", 522 .matches = { 523 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 524 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 525 }, 526 }, 527 { 528 .callback = intel_no_lvds_dmi_callback, 529 .ident = "Apple Mac Mini (Core 2 series)", 530 .matches = { 531 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 532 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 533 }, 534 }, 535 { 536 .callback = intel_no_lvds_dmi_callback, 537 .ident = "MSI IM-945GSE-A", 538 .matches = { 539 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 540 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 541 }, 542 }, 543 { 544 .callback = intel_no_lvds_dmi_callback, 545 .ident = "Dell Studio Hybrid", 546 .matches = { 547 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 548 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 549 }, 550 }, 551 { 552 .callback = intel_no_lvds_dmi_callback, 553 .ident = "Dell OptiPlex FX170", 554 .matches = { 555 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 556 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 557 }, 558 }, 559 { 560 .callback = intel_no_lvds_dmi_callback, 561 .ident = "AOpen Mini PC", 562 .matches = { 563 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 564 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 565 }, 566 }, 567 { 568 .callback = intel_no_lvds_dmi_callback, 569 .ident = "AOpen Mini PC MP915", 570 .matches = { 571 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 572 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 573 }, 574 }, 575 { 576 .callback = intel_no_lvds_dmi_callback, 577 .ident = "AOpen i915GMm-HFS", 578 .matches = { 579 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 580 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 581 }, 582 }, 583 { 584 .callback = intel_no_lvds_dmi_callback, 585 .ident = "AOpen i45GMx-I", 586 .matches = { 587 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 588 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 589 }, 590 }, 591 { 592 .callback = intel_no_lvds_dmi_callback, 593 .ident = "Aopen i945GTt-VFA", 594 .matches = { 595 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 596 }, 597 }, 598 { 599 .callback = intel_no_lvds_dmi_callback, 600 .ident = "Clientron U800", 601 .matches = { 602 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 603 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 604 }, 605 }, 606 { 607 .callback = intel_no_lvds_dmi_callback, 608 .ident = "Clientron E830", 609 .matches = { 610 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 611 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 612 }, 613 }, 614 { 615 .callback = intel_no_lvds_dmi_callback, 616 .ident = "Asus EeeBox PC EB1007", 617 .matches = { 618 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 619 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 620 }, 621 }, 622 { 623 .callback = intel_no_lvds_dmi_callback, 624 .ident = "Asus AT5NM10T-I", 625 .matches = { 626 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 627 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 628 }, 629 }, 630 { 631 .callback = intel_no_lvds_dmi_callback, 632 .ident = "Hewlett-Packard HP t5740", 633 .matches = { 634 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 635 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 636 }, 637 }, 638 { 639 .callback = intel_no_lvds_dmi_callback, 640 .ident = "Hewlett-Packard t5745", 641 .matches = { 642 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 643 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 644 }, 645 }, 646 { 647 .callback = intel_no_lvds_dmi_callback, 648 .ident = "Hewlett-Packard st5747", 649 .matches = { 650 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 651 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 652 }, 653 }, 654 { 655 .callback = intel_no_lvds_dmi_callback, 656 .ident = "MSI Wind Box DC500", 657 .matches = { 658 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 659 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 660 }, 661 }, 662 { 663 .callback = intel_no_lvds_dmi_callback, 664 .ident = "Gigabyte GA-D525TUD", 665 .matches = { 666 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 667 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 668 }, 669 }, 670 { 671 .callback = intel_no_lvds_dmi_callback, 672 .ident = "Supermicro X7SPA-H", 673 .matches = { 674 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 675 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 676 }, 677 }, 678 { 679 .callback = intel_no_lvds_dmi_callback, 680 .ident = "Fujitsu Esprimo Q900", 681 .matches = { 682 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 683 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 684 }, 685 }, 686 { 687 .callback = intel_no_lvds_dmi_callback, 688 .ident = "Intel D410PT", 689 .matches = { 690 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 691 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 692 }, 693 }, 694 { 695 .callback = intel_no_lvds_dmi_callback, 696 .ident = "Intel D425KT", 697 .matches = { 698 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 699 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 700 }, 701 }, 702 { 703 .callback = intel_no_lvds_dmi_callback, 704 .ident = "Intel D510MO", 705 .matches = { 706 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 707 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 708 }, 709 }, 710 { 711 .callback = intel_no_lvds_dmi_callback, 712 .ident = "Intel D525MW", 713 .matches = { 714 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 715 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 716 }, 717 }, 718 { 719 .callback = intel_no_lvds_dmi_callback, 720 .ident = "Radiant P845", 721 .matches = { 722 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 723 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 724 }, 725 }, 726 727 { } /* terminating entry */ 728 }; 729 730 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 731 { 732 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 733 return 1; 734 } 735 736 static const struct dmi_system_id intel_dual_link_lvds[] = { 737 { 738 .callback = intel_dual_link_lvds_callback, 739 .ident = "Apple MacBook Pro 15\" (2010)", 740 .matches = { 741 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 742 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 743 }, 744 }, 745 { 746 .callback = intel_dual_link_lvds_callback, 747 .ident = "Apple MacBook Pro 15\" (2011)", 748 .matches = { 749 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 750 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 751 }, 752 }, 753 { 754 .callback = intel_dual_link_lvds_callback, 755 .ident = "Apple MacBook Pro 15\" (2012)", 756 .matches = { 757 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 758 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 759 }, 760 }, 761 { } /* terminating entry */ 762 }; 763 764 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 765 { 766 struct intel_encoder *encoder; 767 768 for_each_intel_encoder(&dev_priv->drm, encoder) { 769 if (encoder->type == INTEL_OUTPUT_LVDS) 770 return encoder; 771 } 772 773 return NULL; 774 } 775 776 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 777 { 778 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 779 780 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 781 } 782 783 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 784 { 785 struct drm_device *dev = lvds_encoder->base.base.dev; 786 unsigned int val; 787 struct drm_i915_private *dev_priv = to_i915(dev); 788 789 /* use the module option value if specified */ 790 if (dev_priv->params.lvds_channel_mode > 0) 791 return dev_priv->params.lvds_channel_mode == 2; 792 793 /* single channel LVDS is limited to 112 MHz */ 794 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) 795 return true; 796 797 if (dmi_check_system(intel_dual_link_lvds)) 798 return true; 799 800 /* 801 * BIOS should set the proper LVDS register value at boot, but 802 * in reality, it doesn't set the value when the lid is closed; 803 * we need to check "the value to be set" in VBT when LVDS 804 * register is uninitialized. 805 */ 806 val = intel_de_read(dev_priv, lvds_encoder->reg); 807 if (HAS_PCH_CPT(dev_priv)) 808 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 809 else 810 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 811 if (val == 0) 812 val = dev_priv->vbt.bios_lvds_val; 813 814 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 815 } 816 817 /** 818 * intel_lvds_init - setup LVDS connectors on this device 819 * @dev_priv: i915 device 820 * 821 * Create the connector, register the LVDS DDC bus, and try to figure out what 822 * modes we can display on the LVDS panel (if present). 823 */ 824 void intel_lvds_init(struct drm_i915_private *dev_priv) 825 { 826 struct drm_device *dev = &dev_priv->drm; 827 struct intel_lvds_encoder *lvds_encoder; 828 struct intel_encoder *intel_encoder; 829 struct intel_connector *intel_connector; 830 struct drm_connector *connector; 831 struct drm_encoder *encoder; 832 struct drm_display_mode *fixed_mode = NULL; 833 struct drm_display_mode *downclock_mode = NULL; 834 struct edid *edid; 835 i915_reg_t lvds_reg; 836 u32 lvds; 837 u8 pin; 838 u32 allowed_scalers; 839 840 /* Skip init on machines we know falsely report LVDS */ 841 if (dmi_check_system(intel_no_lvds)) { 842 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, 843 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 844 return; 845 } 846 847 if (!dev_priv->vbt.int_lvds_support) { 848 drm_dbg_kms(&dev_priv->drm, 849 "Internal LVDS support disabled by VBT\n"); 850 return; 851 } 852 853 if (HAS_PCH_SPLIT(dev_priv)) 854 lvds_reg = PCH_LVDS; 855 else 856 lvds_reg = LVDS; 857 858 lvds = intel_de_read(dev_priv, lvds_reg); 859 860 if (HAS_PCH_SPLIT(dev_priv)) { 861 if ((lvds & LVDS_DETECTED) == 0) 862 return; 863 } 864 865 pin = GMBUS_PIN_PANEL; 866 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 867 if ((lvds & LVDS_PORT_EN) == 0) { 868 drm_dbg_kms(&dev_priv->drm, 869 "LVDS is not present in VBT\n"); 870 return; 871 } 872 drm_dbg_kms(&dev_priv->drm, 873 "LVDS is not present in VBT, but enabled anyway\n"); 874 } 875 876 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 877 if (!lvds_encoder) 878 return; 879 880 intel_connector = intel_connector_alloc(); 881 if (!intel_connector) { 882 kfree(lvds_encoder); 883 return; 884 } 885 886 lvds_encoder->attached_connector = intel_connector; 887 888 intel_encoder = &lvds_encoder->base; 889 encoder = &intel_encoder->base; 890 connector = &intel_connector->base; 891 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 892 DRM_MODE_CONNECTOR_LVDS); 893 894 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 895 DRM_MODE_ENCODER_LVDS, "LVDS"); 896 897 intel_encoder->enable = intel_enable_lvds; 898 intel_encoder->pre_enable = intel_pre_enable_lvds; 899 intel_encoder->compute_config = intel_lvds_compute_config; 900 if (HAS_PCH_SPLIT(dev_priv)) { 901 intel_encoder->disable = pch_disable_lvds; 902 intel_encoder->post_disable = pch_post_disable_lvds; 903 } else { 904 intel_encoder->disable = gmch_disable_lvds; 905 } 906 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 907 intel_encoder->get_config = intel_lvds_get_config; 908 intel_encoder->update_pipe = intel_panel_update_backlight; 909 intel_encoder->shutdown = intel_lvds_shutdown; 910 intel_connector->get_hw_state = intel_connector_get_hw_state; 911 912 intel_connector_attach_encoder(intel_connector, intel_encoder); 913 914 intel_encoder->type = INTEL_OUTPUT_LVDS; 915 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 916 intel_encoder->port = PORT_NONE; 917 intel_encoder->cloneable = 0; 918 if (INTEL_GEN(dev_priv) < 4) 919 intel_encoder->pipe_mask = BIT(PIPE_B); 920 else 921 intel_encoder->pipe_mask = ~0; 922 923 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 924 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 925 connector->interlace_allowed = false; 926 connector->doublescan_allowed = false; 927 928 lvds_encoder->reg = lvds_reg; 929 930 /* create the scaling mode property */ 931 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); 932 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); 933 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 934 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 935 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 936 937 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 938 lvds_encoder->init_lvds_val = lvds; 939 940 /* 941 * LVDS discovery: 942 * 1) check for EDID on DDC 943 * 2) check for VBT data 944 * 3) check to see if LVDS is already on 945 * if none of the above, no panel 946 */ 947 948 /* 949 * Attempt to get the fixed panel mode from DDC. Assume that the 950 * preferred mode is the right one. 951 */ 952 mutex_lock(&dev->mode_config.mutex); 953 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 954 edid = drm_get_edid_switcheroo(connector, 955 intel_gmbus_get_adapter(dev_priv, pin)); 956 else 957 edid = drm_get_edid(connector, 958 intel_gmbus_get_adapter(dev_priv, pin)); 959 if (edid) { 960 if (drm_add_edid_modes(connector, edid)) { 961 drm_connector_update_edid_property(connector, 962 edid); 963 } else { 964 kfree(edid); 965 edid = ERR_PTR(-EINVAL); 966 } 967 } else { 968 edid = ERR_PTR(-ENOENT); 969 } 970 intel_connector->edid = edid; 971 972 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 973 if (fixed_mode) 974 goto out; 975 976 /* Failed to get EDID, what about VBT? */ 977 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 978 if (fixed_mode) 979 goto out; 980 981 /* 982 * If we didn't get EDID, try checking if the panel is already turned 983 * on. If so, assume that whatever is currently programmed is the 984 * correct mode. 985 */ 986 fixed_mode = intel_encoder_current_mode(intel_encoder); 987 if (fixed_mode) { 988 drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: "); 989 drm_mode_debug_printmodeline(fixed_mode); 990 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 991 } 992 993 /* If we still don't have a mode after all that, give up. */ 994 if (!fixed_mode) 995 goto failed; 996 997 out: 998 mutex_unlock(&dev->mode_config.mutex); 999 1000 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1001 intel_panel_setup_backlight(connector, INVALID_PIPE); 1002 1003 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1004 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", 1005 lvds_encoder->is_dual_link ? "dual" : "single"); 1006 1007 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1008 1009 return; 1010 1011 failed: 1012 mutex_unlock(&dev->mode_config.mutex); 1013 1014 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); 1015 drm_connector_cleanup(connector); 1016 drm_encoder_cleanup(encoder); 1017 kfree(lvds_encoder); 1018 intel_connector_free(intel_connector); 1019 return; 1020 } 1021