1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "i915_reg.h" 43 #include "intel_atomic.h" 44 #include "intel_backlight.h" 45 #include "intel_connector.h" 46 #include "intel_de.h" 47 #include "intel_display_types.h" 48 #include "intel_dpll.h" 49 #include "intel_fdi.h" 50 #include "intel_gmbus.h" 51 #include "intel_lvds.h" 52 #include "intel_panel.h" 53 54 /* Private structure for the integrated LVDS support */ 55 struct intel_lvds_pps { 56 /* 100us units */ 57 int t1_t2; 58 int t3; 59 int t4; 60 int t5; 61 int tx; 62 63 int divider; 64 65 int port; 66 bool powerdown_on_reset; 67 }; 68 69 struct intel_lvds_encoder { 70 struct intel_encoder base; 71 72 bool is_dual_link; 73 i915_reg_t reg; 74 u32 a3_power; 75 76 struct intel_lvds_pps init_pps; 77 u32 init_lvds_val; 78 79 struct intel_connector *attached_connector; 80 }; 81 82 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) 83 { 84 return container_of(encoder, struct intel_lvds_encoder, base); 85 } 86 87 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 88 i915_reg_t lvds_reg, enum pipe *pipe) 89 { 90 u32 val; 91 92 val = intel_de_read(dev_priv, lvds_reg); 93 94 /* asserts want to know the pipe even if the port is disabled */ 95 if (HAS_PCH_CPT(dev_priv)) 96 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 97 else 98 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 99 100 return val & LVDS_PORT_EN; 101 } 102 103 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 104 enum pipe *pipe) 105 { 106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 107 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 108 intel_wakeref_t wakeref; 109 bool ret; 110 111 wakeref = intel_display_power_get_if_enabled(dev_priv, 112 encoder->power_domain); 113 if (!wakeref) 114 return false; 115 116 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 117 118 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 119 120 return ret; 121 } 122 123 static void intel_lvds_get_config(struct intel_encoder *encoder, 124 struct intel_crtc_state *pipe_config) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 128 u32 tmp, flags = 0; 129 130 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 131 132 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 133 if (tmp & LVDS_HSYNC_POLARITY) 134 flags |= DRM_MODE_FLAG_NHSYNC; 135 else 136 flags |= DRM_MODE_FLAG_PHSYNC; 137 if (tmp & LVDS_VSYNC_POLARITY) 138 flags |= DRM_MODE_FLAG_NVSYNC; 139 else 140 flags |= DRM_MODE_FLAG_PVSYNC; 141 142 pipe_config->hw.adjusted_mode.flags |= flags; 143 144 if (DISPLAY_VER(dev_priv) < 5) 145 pipe_config->gmch_pfit.lvds_border_bits = 146 tmp & LVDS_BORDER_ENABLE; 147 148 /* gen2/3 store dither state in pfit control, needs to match */ 149 if (DISPLAY_VER(dev_priv) < 4) { 150 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 151 152 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 153 } 154 155 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 156 } 157 158 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 159 struct intel_lvds_pps *pps) 160 { 161 u32 val; 162 163 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 164 165 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 167 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 168 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 169 170 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 171 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 172 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 173 174 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 176 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 177 /* 178 * Remove the BSpec specified +1 (100ms) offset that accounts for a 179 * too short power-cycle delay due to the asynchronous programming of 180 * the register. 181 */ 182 if (val) 183 val--; 184 /* Convert from 100ms to 100us units */ 185 pps->t4 = val * 1000; 186 187 if (DISPLAY_VER(dev_priv) <= 4 && 188 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 189 drm_dbg_kms(&dev_priv->drm, 190 "Panel power timings uninitialized, " 191 "setting defaults\n"); 192 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 193 pps->t1_t2 = 40 * 10; 194 pps->t5 = 200 * 10; 195 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 196 pps->t3 = 35 * 10; 197 pps->tx = 200 * 10; 198 } 199 200 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 201 "divider %d port %d powerdown_on_reset %d\n", 202 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 203 pps->divider, pps->port, pps->powerdown_on_reset); 204 } 205 206 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 207 struct intel_lvds_pps *pps) 208 { 209 u32 val; 210 211 val = intel_de_read(dev_priv, PP_CONTROL(0)); 212 drm_WARN_ON(&dev_priv->drm, 213 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 214 if (pps->powerdown_on_reset) 215 val |= PANEL_POWER_RESET; 216 intel_de_write(dev_priv, PP_CONTROL(0), val); 217 218 intel_de_write(dev_priv, PP_ON_DELAYS(0), 219 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 220 221 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 222 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 223 224 intel_de_write(dev_priv, PP_DIVISOR(0), 225 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 226 } 227 228 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 229 struct intel_encoder *encoder, 230 const struct intel_crtc_state *pipe_config, 231 const struct drm_connector_state *conn_state) 232 { 233 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 234 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 235 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 236 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 237 enum pipe pipe = crtc->pipe; 238 u32 temp; 239 240 if (HAS_PCH_SPLIT(dev_priv)) { 241 assert_fdi_rx_pll_disabled(dev_priv, pipe); 242 assert_shared_dpll_disabled(dev_priv, 243 pipe_config->shared_dpll); 244 } else { 245 assert_pll_disabled(dev_priv, pipe); 246 } 247 248 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 249 250 temp = lvds_encoder->init_lvds_val; 251 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 252 253 if (HAS_PCH_CPT(dev_priv)) { 254 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 255 temp |= LVDS_PIPE_SEL_CPT(pipe); 256 } else { 257 temp &= ~LVDS_PIPE_SEL_MASK; 258 temp |= LVDS_PIPE_SEL(pipe); 259 } 260 261 /* set the corresponsding LVDS_BORDER bit */ 262 temp &= ~LVDS_BORDER_ENABLE; 263 temp |= pipe_config->gmch_pfit.lvds_border_bits; 264 265 /* 266 * Set the B0-B3 data pairs corresponding to whether we're going to 267 * set the DPLLs for dual-channel mode or not. 268 */ 269 if (lvds_encoder->is_dual_link) 270 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 271 else 272 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 273 274 /* 275 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 276 * appropriately here, but we need to look more thoroughly into how 277 * panels behave in the two modes. For now, let's just maintain the 278 * value we got from the BIOS. 279 */ 280 temp &= ~LVDS_A3_POWER_MASK; 281 temp |= lvds_encoder->a3_power; 282 283 /* 284 * Set the dithering flag on LVDS as needed, note that there is no 285 * special lvds dither control bit on pch-split platforms, dithering is 286 * only controlled through the PIPECONF reg. 287 */ 288 if (DISPLAY_VER(dev_priv) == 4) { 289 /* 290 * Bspec wording suggests that LVDS port dithering only exists 291 * for 18bpp panels. 292 */ 293 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 294 temp |= LVDS_ENABLE_DITHER; 295 else 296 temp &= ~LVDS_ENABLE_DITHER; 297 } 298 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 299 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 300 temp |= LVDS_HSYNC_POLARITY; 301 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 302 temp |= LVDS_VSYNC_POLARITY; 303 304 intel_de_write(dev_priv, lvds_encoder->reg, temp); 305 } 306 307 /* 308 * Sets the power state for the panel. 309 */ 310 static void intel_enable_lvds(struct intel_atomic_state *state, 311 struct intel_encoder *encoder, 312 const struct intel_crtc_state *pipe_config, 313 const struct drm_connector_state *conn_state) 314 { 315 struct drm_device *dev = encoder->base.dev; 316 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 317 struct drm_i915_private *dev_priv = to_i915(dev); 318 319 intel_de_write(dev_priv, lvds_encoder->reg, 320 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 321 322 intel_de_write(dev_priv, PP_CONTROL(0), 323 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 324 intel_de_posting_read(dev_priv, lvds_encoder->reg); 325 326 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 327 drm_err(&dev_priv->drm, 328 "timed out waiting for panel to power on\n"); 329 330 intel_backlight_enable(pipe_config, conn_state); 331 } 332 333 static void intel_disable_lvds(struct intel_atomic_state *state, 334 struct intel_encoder *encoder, 335 const struct intel_crtc_state *old_crtc_state, 336 const struct drm_connector_state *old_conn_state) 337 { 338 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 339 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 340 341 intel_de_write(dev_priv, PP_CONTROL(0), 342 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 343 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 344 drm_err(&dev_priv->drm, 345 "timed out waiting for panel to power off\n"); 346 347 intel_de_write(dev_priv, lvds_encoder->reg, 348 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 349 intel_de_posting_read(dev_priv, lvds_encoder->reg); 350 } 351 352 static void gmch_disable_lvds(struct intel_atomic_state *state, 353 struct intel_encoder *encoder, 354 const struct intel_crtc_state *old_crtc_state, 355 const struct drm_connector_state *old_conn_state) 356 357 { 358 intel_backlight_disable(old_conn_state); 359 360 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 361 } 362 363 static void pch_disable_lvds(struct intel_atomic_state *state, 364 struct intel_encoder *encoder, 365 const struct intel_crtc_state *old_crtc_state, 366 const struct drm_connector_state *old_conn_state) 367 { 368 intel_backlight_disable(old_conn_state); 369 } 370 371 static void pch_post_disable_lvds(struct intel_atomic_state *state, 372 struct intel_encoder *encoder, 373 const struct intel_crtc_state *old_crtc_state, 374 const struct drm_connector_state *old_conn_state) 375 { 376 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 377 } 378 379 static void intel_lvds_shutdown(struct intel_encoder *encoder) 380 { 381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 382 383 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 384 drm_err(&dev_priv->drm, 385 "timed out waiting for panel power cycle delay\n"); 386 } 387 388 static enum drm_mode_status 389 intel_lvds_mode_valid(struct drm_connector *connector, 390 struct drm_display_mode *mode) 391 { 392 struct intel_connector *intel_connector = to_intel_connector(connector); 393 const struct drm_display_mode *fixed_mode = 394 intel_panel_fixed_mode(intel_connector, mode); 395 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 396 enum drm_mode_status status; 397 398 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 399 return MODE_NO_DBLESCAN; 400 401 status = intel_panel_mode_valid(intel_connector, mode); 402 if (status != MODE_OK) 403 return status; 404 405 if (fixed_mode->clock > max_pixclk) 406 return MODE_CLOCK_HIGH; 407 408 return MODE_OK; 409 } 410 411 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 412 struct intel_crtc_state *pipe_config, 413 struct drm_connector_state *conn_state) 414 { 415 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 416 struct intel_lvds_encoder *lvds_encoder = 417 to_lvds_encoder(intel_encoder); 418 struct intel_connector *intel_connector = 419 lvds_encoder->attached_connector; 420 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 421 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 422 unsigned int lvds_bpp; 423 int ret; 424 425 /* Should never happen!! */ 426 if (DISPLAY_VER(dev_priv) < 4 && crtc->pipe == 0) { 427 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); 428 return -EINVAL; 429 } 430 431 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 432 lvds_bpp = 8*3; 433 else 434 lvds_bpp = 6*3; 435 436 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 437 drm_dbg_kms(&dev_priv->drm, 438 "forcing display bpp (was %d) to LVDS (%d)\n", 439 pipe_config->pipe_bpp, lvds_bpp); 440 pipe_config->pipe_bpp = lvds_bpp; 441 } 442 443 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 444 445 /* 446 * We have timings from the BIOS for the panel, put them in 447 * to the adjusted mode. The CRTC will be set up for this mode, 448 * with the panel scaling set up to source from the H/VDisplay 449 * of the original mode. 450 */ 451 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 452 if (ret) 453 return ret; 454 455 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 456 return -EINVAL; 457 458 if (HAS_PCH_SPLIT(dev_priv)) 459 pipe_config->has_pch_encoder = true; 460 461 ret = intel_panel_fitting(pipe_config, conn_state); 462 if (ret) 463 return ret; 464 465 /* 466 * XXX: It would be nice to support lower refresh rates on the 467 * panels to reduce power consumption, and perhaps match the 468 * user's requested refresh rate. 469 */ 470 471 return 0; 472 } 473 474 /* 475 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 476 */ 477 static int intel_lvds_get_modes(struct drm_connector *connector) 478 { 479 struct intel_connector *intel_connector = to_intel_connector(connector); 480 481 /* use cached edid if we have one */ 482 if (!IS_ERR_OR_NULL(intel_connector->edid)) { 483 drm_edid_connector_update(connector, intel_connector->edid); 484 485 return drm_edid_connector_add_modes(connector); 486 } 487 488 return intel_panel_get_modes(intel_connector); 489 } 490 491 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 492 .get_modes = intel_lvds_get_modes, 493 .mode_valid = intel_lvds_mode_valid, 494 .atomic_check = intel_digital_connector_atomic_check, 495 }; 496 497 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 498 .detect = intel_panel_detect, 499 .fill_modes = drm_helper_probe_single_connector_modes, 500 .atomic_get_property = intel_digital_connector_atomic_get_property, 501 .atomic_set_property = intel_digital_connector_atomic_set_property, 502 .late_register = intel_connector_register, 503 .early_unregister = intel_connector_unregister, 504 .destroy = intel_connector_destroy, 505 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 506 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 507 }; 508 509 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 510 .destroy = intel_encoder_destroy, 511 }; 512 513 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 514 { 515 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 516 return 1; 517 } 518 519 /* These systems claim to have LVDS, but really don't */ 520 static const struct dmi_system_id intel_no_lvds[] = { 521 { 522 .callback = intel_no_lvds_dmi_callback, 523 .ident = "Apple Mac Mini (Core series)", 524 .matches = { 525 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 526 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 527 }, 528 }, 529 { 530 .callback = intel_no_lvds_dmi_callback, 531 .ident = "Apple Mac Mini (Core 2 series)", 532 .matches = { 533 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 534 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 535 }, 536 }, 537 { 538 .callback = intel_no_lvds_dmi_callback, 539 .ident = "MSI IM-945GSE-A", 540 .matches = { 541 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 542 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 543 }, 544 }, 545 { 546 .callback = intel_no_lvds_dmi_callback, 547 .ident = "Dell Studio Hybrid", 548 .matches = { 549 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 550 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 551 }, 552 }, 553 { 554 .callback = intel_no_lvds_dmi_callback, 555 .ident = "Dell OptiPlex FX170", 556 .matches = { 557 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 558 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 559 }, 560 }, 561 { 562 .callback = intel_no_lvds_dmi_callback, 563 .ident = "AOpen Mini PC", 564 .matches = { 565 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 566 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 567 }, 568 }, 569 { 570 .callback = intel_no_lvds_dmi_callback, 571 .ident = "AOpen Mini PC MP915", 572 .matches = { 573 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 574 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 575 }, 576 }, 577 { 578 .callback = intel_no_lvds_dmi_callback, 579 .ident = "AOpen i915GMm-HFS", 580 .matches = { 581 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 582 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 583 }, 584 }, 585 { 586 .callback = intel_no_lvds_dmi_callback, 587 .ident = "AOpen i45GMx-I", 588 .matches = { 589 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 590 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 591 }, 592 }, 593 { 594 .callback = intel_no_lvds_dmi_callback, 595 .ident = "Aopen i945GTt-VFA", 596 .matches = { 597 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 598 }, 599 }, 600 { 601 .callback = intel_no_lvds_dmi_callback, 602 .ident = "Clientron U800", 603 .matches = { 604 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 605 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 606 }, 607 }, 608 { 609 .callback = intel_no_lvds_dmi_callback, 610 .ident = "Clientron E830", 611 .matches = { 612 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 613 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 614 }, 615 }, 616 { 617 .callback = intel_no_lvds_dmi_callback, 618 .ident = "Asus EeeBox PC EB1007", 619 .matches = { 620 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 621 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 622 }, 623 }, 624 { 625 .callback = intel_no_lvds_dmi_callback, 626 .ident = "Asus AT5NM10T-I", 627 .matches = { 628 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 629 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 630 }, 631 }, 632 { 633 .callback = intel_no_lvds_dmi_callback, 634 .ident = "Hewlett-Packard HP t5740", 635 .matches = { 636 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 637 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 638 }, 639 }, 640 { 641 .callback = intel_no_lvds_dmi_callback, 642 .ident = "Hewlett-Packard t5745", 643 .matches = { 644 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 645 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 646 }, 647 }, 648 { 649 .callback = intel_no_lvds_dmi_callback, 650 .ident = "Hewlett-Packard st5747", 651 .matches = { 652 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 653 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 654 }, 655 }, 656 { 657 .callback = intel_no_lvds_dmi_callback, 658 .ident = "MSI Wind Box DC500", 659 .matches = { 660 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 661 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 662 }, 663 }, 664 { 665 .callback = intel_no_lvds_dmi_callback, 666 .ident = "Gigabyte GA-D525TUD", 667 .matches = { 668 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 669 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 670 }, 671 }, 672 { 673 .callback = intel_no_lvds_dmi_callback, 674 .ident = "Supermicro X7SPA-H", 675 .matches = { 676 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 677 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 678 }, 679 }, 680 { 681 .callback = intel_no_lvds_dmi_callback, 682 .ident = "Fujitsu Esprimo Q900", 683 .matches = { 684 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 685 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 686 }, 687 }, 688 { 689 .callback = intel_no_lvds_dmi_callback, 690 .ident = "Intel D410PT", 691 .matches = { 692 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 693 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 694 }, 695 }, 696 { 697 .callback = intel_no_lvds_dmi_callback, 698 .ident = "Intel D425KT", 699 .matches = { 700 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 701 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 702 }, 703 }, 704 { 705 .callback = intel_no_lvds_dmi_callback, 706 .ident = "Intel D510MO", 707 .matches = { 708 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 709 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 710 }, 711 }, 712 { 713 .callback = intel_no_lvds_dmi_callback, 714 .ident = "Intel D525MW", 715 .matches = { 716 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 717 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 718 }, 719 }, 720 { 721 .callback = intel_no_lvds_dmi_callback, 722 .ident = "Radiant P845", 723 .matches = { 724 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 725 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 726 }, 727 }, 728 729 { } /* terminating entry */ 730 }; 731 732 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 733 { 734 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 735 return 1; 736 } 737 738 static const struct dmi_system_id intel_dual_link_lvds[] = { 739 { 740 .callback = intel_dual_link_lvds_callback, 741 .ident = "Apple MacBook Pro 15\" (2010)", 742 .matches = { 743 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 744 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 745 }, 746 }, 747 { 748 .callback = intel_dual_link_lvds_callback, 749 .ident = "Apple MacBook Pro 15\" (2011)", 750 .matches = { 751 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 752 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 753 }, 754 }, 755 { 756 .callback = intel_dual_link_lvds_callback, 757 .ident = "Apple MacBook Pro 15\" (2012)", 758 .matches = { 759 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 760 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 761 }, 762 }, 763 { } /* terminating entry */ 764 }; 765 766 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 767 { 768 struct intel_encoder *encoder; 769 770 for_each_intel_encoder(&dev_priv->drm, encoder) { 771 if (encoder->type == INTEL_OUTPUT_LVDS) 772 return encoder; 773 } 774 775 return NULL; 776 } 777 778 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 779 { 780 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 781 782 return encoder && to_lvds_encoder(encoder)->is_dual_link; 783 } 784 785 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 786 { 787 struct drm_i915_private *dev_priv = to_i915(lvds_encoder->base.base.dev); 788 struct intel_connector *connector = lvds_encoder->attached_connector; 789 const struct drm_display_mode *fixed_mode = 790 intel_panel_preferred_fixed_mode(connector); 791 unsigned int val; 792 793 /* use the module option value if specified */ 794 if (dev_priv->params.lvds_channel_mode > 0) 795 return dev_priv->params.lvds_channel_mode == 2; 796 797 /* single channel LVDS is limited to 112 MHz */ 798 if (fixed_mode->clock > 112999) 799 return true; 800 801 if (dmi_check_system(intel_dual_link_lvds)) 802 return true; 803 804 /* 805 * BIOS should set the proper LVDS register value at boot, but 806 * in reality, it doesn't set the value when the lid is closed; 807 * we need to check "the value to be set" in VBT when LVDS 808 * register is uninitialized. 809 */ 810 val = intel_de_read(dev_priv, lvds_encoder->reg); 811 if (HAS_PCH_CPT(dev_priv)) 812 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 813 else 814 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 815 if (val == 0) 816 val = connector->panel.vbt.bios_lvds_val; 817 818 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 819 } 820 821 static void intel_lvds_add_properties(struct drm_connector *connector) 822 { 823 intel_attach_scaling_mode_property(connector); 824 } 825 826 /** 827 * intel_lvds_init - setup LVDS connectors on this device 828 * @dev_priv: i915 device 829 * 830 * Create the connector, register the LVDS DDC bus, and try to figure out what 831 * modes we can display on the LVDS panel (if present). 832 */ 833 void intel_lvds_init(struct drm_i915_private *dev_priv) 834 { 835 struct intel_lvds_encoder *lvds_encoder; 836 struct intel_encoder *intel_encoder; 837 struct intel_connector *intel_connector; 838 struct drm_connector *connector; 839 struct drm_encoder *encoder; 840 const struct drm_edid *drm_edid; 841 i915_reg_t lvds_reg; 842 u32 lvds; 843 u8 pin; 844 845 /* Skip init on machines we know falsely report LVDS */ 846 if (dmi_check_system(intel_no_lvds)) { 847 drm_WARN(&dev_priv->drm, !dev_priv->display.vbt.int_lvds_support, 848 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 849 return; 850 } 851 852 if (!dev_priv->display.vbt.int_lvds_support) { 853 drm_dbg_kms(&dev_priv->drm, 854 "Internal LVDS support disabled by VBT\n"); 855 return; 856 } 857 858 if (HAS_PCH_SPLIT(dev_priv)) 859 lvds_reg = PCH_LVDS; 860 else 861 lvds_reg = LVDS; 862 863 lvds = intel_de_read(dev_priv, lvds_reg); 864 865 if (HAS_PCH_SPLIT(dev_priv)) { 866 if ((lvds & LVDS_DETECTED) == 0) 867 return; 868 } 869 870 pin = GMBUS_PIN_PANEL; 871 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 872 if ((lvds & LVDS_PORT_EN) == 0) { 873 drm_dbg_kms(&dev_priv->drm, 874 "LVDS is not present in VBT\n"); 875 return; 876 } 877 drm_dbg_kms(&dev_priv->drm, 878 "LVDS is not present in VBT, but enabled anyway\n"); 879 } 880 881 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 882 if (!lvds_encoder) 883 return; 884 885 intel_connector = intel_connector_alloc(); 886 if (!intel_connector) { 887 kfree(lvds_encoder); 888 return; 889 } 890 891 lvds_encoder->attached_connector = intel_connector; 892 893 intel_encoder = &lvds_encoder->base; 894 encoder = &intel_encoder->base; 895 connector = &intel_connector->base; 896 drm_connector_init(&dev_priv->drm, &intel_connector->base, &intel_lvds_connector_funcs, 897 DRM_MODE_CONNECTOR_LVDS); 898 899 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_lvds_enc_funcs, 900 DRM_MODE_ENCODER_LVDS, "LVDS"); 901 902 intel_encoder->enable = intel_enable_lvds; 903 intel_encoder->pre_enable = intel_pre_enable_lvds; 904 intel_encoder->compute_config = intel_lvds_compute_config; 905 if (HAS_PCH_SPLIT(dev_priv)) { 906 intel_encoder->disable = pch_disable_lvds; 907 intel_encoder->post_disable = pch_post_disable_lvds; 908 } else { 909 intel_encoder->disable = gmch_disable_lvds; 910 } 911 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 912 intel_encoder->get_config = intel_lvds_get_config; 913 intel_encoder->update_pipe = intel_backlight_update; 914 intel_encoder->shutdown = intel_lvds_shutdown; 915 intel_connector->get_hw_state = intel_connector_get_hw_state; 916 917 intel_connector_attach_encoder(intel_connector, intel_encoder); 918 919 intel_encoder->type = INTEL_OUTPUT_LVDS; 920 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 921 intel_encoder->port = PORT_NONE; 922 intel_encoder->cloneable = 0; 923 if (DISPLAY_VER(dev_priv) < 4) 924 intel_encoder->pipe_mask = BIT(PIPE_B); 925 else 926 intel_encoder->pipe_mask = ~0; 927 928 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 929 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 930 931 lvds_encoder->reg = lvds_reg; 932 933 intel_lvds_add_properties(connector); 934 935 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 936 lvds_encoder->init_lvds_val = lvds; 937 938 /* 939 * LVDS discovery: 940 * 1) check for EDID on DDC 941 * 2) check for VBT data 942 * 3) check to see if LVDS is already on 943 * if none of the above, no panel 944 */ 945 946 /* 947 * Attempt to get the fixed panel mode from DDC. Assume that the 948 * preferred mode is the right one. 949 */ 950 mutex_lock(&dev_priv->drm.mode_config.mutex); 951 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) { 952 const struct edid *edid; 953 954 /* FIXME: Make drm_get_edid_switcheroo() return drm_edid */ 955 edid = drm_get_edid_switcheroo(connector, 956 intel_gmbus_get_adapter(dev_priv, pin)); 957 if (edid) { 958 drm_edid = drm_edid_alloc(edid, (edid->extensions + 1) * EDID_LENGTH); 959 kfree(edid); 960 } else { 961 drm_edid = NULL; 962 } 963 } else { 964 drm_edid = drm_edid_read_ddc(connector, 965 intel_gmbus_get_adapter(dev_priv, pin)); 966 } 967 if (drm_edid) { 968 if (drm_edid_connector_update(connector, drm_edid) || 969 !drm_edid_connector_add_modes(connector)) { 970 drm_edid_connector_update(connector, NULL); 971 drm_edid_free(drm_edid); 972 drm_edid = ERR_PTR(-EINVAL); 973 } 974 } else { 975 drm_edid = ERR_PTR(-ENOENT); 976 } 977 intel_connector->edid = drm_edid; 978 979 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL, 980 IS_ERR(drm_edid) ? NULL : drm_edid); 981 982 /* Try EDID first */ 983 intel_panel_add_edid_fixed_modes(intel_connector, true); 984 985 /* Failed to get EDID, what about VBT? */ 986 if (!intel_panel_preferred_fixed_mode(intel_connector)) 987 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 988 989 /* 990 * If we didn't get a fixed mode from EDID or VBT, try checking 991 * if the panel is already turned on. If so, assume that 992 * whatever is currently programmed is the correct mode. 993 */ 994 if (!intel_panel_preferred_fixed_mode(intel_connector)) 995 intel_panel_add_encoder_fixed_mode(intel_connector, intel_encoder); 996 997 mutex_unlock(&dev_priv->drm.mode_config.mutex); 998 999 /* If we still don't have a mode after all that, give up. */ 1000 if (!intel_panel_preferred_fixed_mode(intel_connector)) 1001 goto failed; 1002 1003 intel_panel_init(intel_connector); 1004 1005 intel_backlight_setup(intel_connector, INVALID_PIPE); 1006 1007 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1008 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", 1009 lvds_encoder->is_dual_link ? "dual" : "single"); 1010 1011 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1012 1013 return; 1014 1015 failed: 1016 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); 1017 drm_connector_cleanup(connector); 1018 drm_encoder_cleanup(encoder); 1019 kfree(lvds_encoder); 1020 intel_connector_free(intel_connector); 1021 return; 1022 } 1023