1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "intel_atomic.h" 43 #include "intel_backlight.h" 44 #include "intel_connector.h" 45 #include "intel_de.h" 46 #include "intel_display_types.h" 47 #include "intel_dpll.h" 48 #include "intel_fdi.h" 49 #include "intel_gmbus.h" 50 #include "intel_lvds.h" 51 #include "intel_panel.h" 52 53 /* Private structure for the integrated LVDS support */ 54 struct intel_lvds_pps { 55 /* 100us units */ 56 int t1_t2; 57 int t3; 58 int t4; 59 int t5; 60 int tx; 61 62 int divider; 63 64 int port; 65 bool powerdown_on_reset; 66 }; 67 68 struct intel_lvds_encoder { 69 struct intel_encoder base; 70 71 bool is_dual_link; 72 i915_reg_t reg; 73 u32 a3_power; 74 75 struct intel_lvds_pps init_pps; 76 u32 init_lvds_val; 77 78 struct intel_connector *attached_connector; 79 }; 80 81 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 82 { 83 return container_of(encoder, struct intel_lvds_encoder, base.base); 84 } 85 86 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 87 i915_reg_t lvds_reg, enum pipe *pipe) 88 { 89 u32 val; 90 91 val = intel_de_read(dev_priv, lvds_reg); 92 93 /* asserts want to know the pipe even if the port is disabled */ 94 if (HAS_PCH_CPT(dev_priv)) 95 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 96 else 97 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 98 99 return val & LVDS_PORT_EN; 100 } 101 102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 103 enum pipe *pipe) 104 { 105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 106 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 107 intel_wakeref_t wakeref; 108 bool ret; 109 110 wakeref = intel_display_power_get_if_enabled(dev_priv, 111 encoder->power_domain); 112 if (!wakeref) 113 return false; 114 115 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 116 117 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 118 119 return ret; 120 } 121 122 static void intel_lvds_get_config(struct intel_encoder *encoder, 123 struct intel_crtc_state *pipe_config) 124 { 125 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 126 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 127 u32 tmp, flags = 0; 128 129 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 130 131 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 132 if (tmp & LVDS_HSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NHSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PHSYNC; 136 if (tmp & LVDS_VSYNC_POLARITY) 137 flags |= DRM_MODE_FLAG_NVSYNC; 138 else 139 flags |= DRM_MODE_FLAG_PVSYNC; 140 141 pipe_config->hw.adjusted_mode.flags |= flags; 142 143 if (DISPLAY_VER(dev_priv) < 5) 144 pipe_config->gmch_pfit.lvds_border_bits = 145 tmp & LVDS_BORDER_ENABLE; 146 147 /* gen2/3 store dither state in pfit control, needs to match */ 148 if (DISPLAY_VER(dev_priv) < 4) { 149 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 150 151 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 152 } 153 154 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 155 } 156 157 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 158 struct intel_lvds_pps *pps) 159 { 160 u32 val; 161 162 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 163 164 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 165 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 166 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 167 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 168 169 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 170 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 171 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 172 173 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 174 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 175 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 176 /* 177 * Remove the BSpec specified +1 (100ms) offset that accounts for a 178 * too short power-cycle delay due to the asynchronous programming of 179 * the register. 180 */ 181 if (val) 182 val--; 183 /* Convert from 100ms to 100us units */ 184 pps->t4 = val * 1000; 185 186 if (DISPLAY_VER(dev_priv) <= 4 && 187 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 188 drm_dbg_kms(&dev_priv->drm, 189 "Panel power timings uninitialized, " 190 "setting defaults\n"); 191 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 192 pps->t1_t2 = 40 * 10; 193 pps->t5 = 200 * 10; 194 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 195 pps->t3 = 35 * 10; 196 pps->tx = 200 * 10; 197 } 198 199 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 200 "divider %d port %d powerdown_on_reset %d\n", 201 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 202 pps->divider, pps->port, pps->powerdown_on_reset); 203 } 204 205 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 206 struct intel_lvds_pps *pps) 207 { 208 u32 val; 209 210 val = intel_de_read(dev_priv, PP_CONTROL(0)); 211 drm_WARN_ON(&dev_priv->drm, 212 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 213 if (pps->powerdown_on_reset) 214 val |= PANEL_POWER_RESET; 215 intel_de_write(dev_priv, PP_CONTROL(0), val); 216 217 intel_de_write(dev_priv, PP_ON_DELAYS(0), 218 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 219 220 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 221 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 222 223 intel_de_write(dev_priv, PP_DIVISOR(0), 224 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 225 } 226 227 static void intel_pre_enable_lvds(struct intel_atomic_state *state, 228 struct intel_encoder *encoder, 229 const struct intel_crtc_state *pipe_config, 230 const struct drm_connector_state *conn_state) 231 { 232 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 234 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 235 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 236 enum pipe pipe = crtc->pipe; 237 u32 temp; 238 239 if (HAS_PCH_SPLIT(dev_priv)) { 240 assert_fdi_rx_pll_disabled(dev_priv, pipe); 241 assert_shared_dpll_disabled(dev_priv, 242 pipe_config->shared_dpll); 243 } else { 244 assert_pll_disabled(dev_priv, pipe); 245 } 246 247 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 248 249 temp = lvds_encoder->init_lvds_val; 250 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 251 252 if (HAS_PCH_CPT(dev_priv)) { 253 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 254 temp |= LVDS_PIPE_SEL_CPT(pipe); 255 } else { 256 temp &= ~LVDS_PIPE_SEL_MASK; 257 temp |= LVDS_PIPE_SEL(pipe); 258 } 259 260 /* set the corresponsding LVDS_BORDER bit */ 261 temp &= ~LVDS_BORDER_ENABLE; 262 temp |= pipe_config->gmch_pfit.lvds_border_bits; 263 264 /* 265 * Set the B0-B3 data pairs corresponding to whether we're going to 266 * set the DPLLs for dual-channel mode or not. 267 */ 268 if (lvds_encoder->is_dual_link) 269 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 270 else 271 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 272 273 /* 274 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 275 * appropriately here, but we need to look more thoroughly into how 276 * panels behave in the two modes. For now, let's just maintain the 277 * value we got from the BIOS. 278 */ 279 temp &= ~LVDS_A3_POWER_MASK; 280 temp |= lvds_encoder->a3_power; 281 282 /* 283 * Set the dithering flag on LVDS as needed, note that there is no 284 * special lvds dither control bit on pch-split platforms, dithering is 285 * only controlled through the PIPECONF reg. 286 */ 287 if (DISPLAY_VER(dev_priv) == 4) { 288 /* 289 * Bspec wording suggests that LVDS port dithering only exists 290 * for 18bpp panels. 291 */ 292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 293 temp |= LVDS_ENABLE_DITHER; 294 else 295 temp &= ~LVDS_ENABLE_DITHER; 296 } 297 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 298 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 299 temp |= LVDS_HSYNC_POLARITY; 300 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 301 temp |= LVDS_VSYNC_POLARITY; 302 303 intel_de_write(dev_priv, lvds_encoder->reg, temp); 304 } 305 306 /* 307 * Sets the power state for the panel. 308 */ 309 static void intel_enable_lvds(struct intel_atomic_state *state, 310 struct intel_encoder *encoder, 311 const struct intel_crtc_state *pipe_config, 312 const struct drm_connector_state *conn_state) 313 { 314 struct drm_device *dev = encoder->base.dev; 315 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 316 struct drm_i915_private *dev_priv = to_i915(dev); 317 318 intel_de_write(dev_priv, lvds_encoder->reg, 319 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 320 321 intel_de_write(dev_priv, PP_CONTROL(0), 322 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 323 intel_de_posting_read(dev_priv, lvds_encoder->reg); 324 325 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 326 drm_err(&dev_priv->drm, 327 "timed out waiting for panel to power on\n"); 328 329 intel_backlight_enable(pipe_config, conn_state); 330 } 331 332 static void intel_disable_lvds(struct intel_atomic_state *state, 333 struct intel_encoder *encoder, 334 const struct intel_crtc_state *old_crtc_state, 335 const struct drm_connector_state *old_conn_state) 336 { 337 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 338 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 339 340 intel_de_write(dev_priv, PP_CONTROL(0), 341 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 342 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 343 drm_err(&dev_priv->drm, 344 "timed out waiting for panel to power off\n"); 345 346 intel_de_write(dev_priv, lvds_encoder->reg, 347 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 348 intel_de_posting_read(dev_priv, lvds_encoder->reg); 349 } 350 351 static void gmch_disable_lvds(struct intel_atomic_state *state, 352 struct intel_encoder *encoder, 353 const struct intel_crtc_state *old_crtc_state, 354 const struct drm_connector_state *old_conn_state) 355 356 { 357 intel_backlight_disable(old_conn_state); 358 359 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 360 } 361 362 static void pch_disable_lvds(struct intel_atomic_state *state, 363 struct intel_encoder *encoder, 364 const struct intel_crtc_state *old_crtc_state, 365 const struct drm_connector_state *old_conn_state) 366 { 367 intel_backlight_disable(old_conn_state); 368 } 369 370 static void pch_post_disable_lvds(struct intel_atomic_state *state, 371 struct intel_encoder *encoder, 372 const struct intel_crtc_state *old_crtc_state, 373 const struct drm_connector_state *old_conn_state) 374 { 375 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state); 376 } 377 378 static void intel_lvds_shutdown(struct intel_encoder *encoder) 379 { 380 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 381 382 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) 383 drm_err(&dev_priv->drm, 384 "timed out waiting for panel power cycle delay\n"); 385 } 386 387 static enum drm_mode_status 388 intel_lvds_mode_valid(struct drm_connector *connector, 389 struct drm_display_mode *mode) 390 { 391 struct intel_connector *intel_connector = to_intel_connector(connector); 392 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 393 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 394 enum drm_mode_status status; 395 396 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 397 return MODE_NO_DBLESCAN; 398 399 status = intel_panel_mode_valid(intel_connector, mode); 400 if (status != MODE_OK) 401 return status; 402 403 if (fixed_mode->clock > max_pixclk) 404 return MODE_CLOCK_HIGH; 405 406 return MODE_OK; 407 } 408 409 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 410 struct intel_crtc_state *pipe_config, 411 struct drm_connector_state *conn_state) 412 { 413 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 414 struct intel_lvds_encoder *lvds_encoder = 415 to_lvds_encoder(&intel_encoder->base); 416 struct intel_connector *intel_connector = 417 lvds_encoder->attached_connector; 418 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 419 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 420 unsigned int lvds_bpp; 421 int ret; 422 423 /* Should never happen!! */ 424 if (DISPLAY_VER(dev_priv) < 4 && crtc->pipe == 0) { 425 drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); 426 return -EINVAL; 427 } 428 429 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 430 lvds_bpp = 8*3; 431 else 432 lvds_bpp = 6*3; 433 434 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 435 drm_dbg_kms(&dev_priv->drm, 436 "forcing display bpp (was %d) to LVDS (%d)\n", 437 pipe_config->pipe_bpp, lvds_bpp); 438 pipe_config->pipe_bpp = lvds_bpp; 439 } 440 441 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 442 443 /* 444 * We have timings from the BIOS for the panel, put them in 445 * to the adjusted mode. The CRTC will be set up for this mode, 446 * with the panel scaling set up to source from the H/VDisplay 447 * of the original mode. 448 */ 449 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 450 if (ret) 451 return ret; 452 453 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 454 return -EINVAL; 455 456 if (HAS_PCH_SPLIT(dev_priv)) 457 pipe_config->has_pch_encoder = true; 458 459 ret = intel_panel_fitting(pipe_config, conn_state); 460 if (ret) 461 return ret; 462 463 /* 464 * XXX: It would be nice to support lower refresh rates on the 465 * panels to reduce power consumption, and perhaps match the 466 * user's requested refresh rate. 467 */ 468 469 return 0; 470 } 471 472 /* 473 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 474 */ 475 static int intel_lvds_get_modes(struct drm_connector *connector) 476 { 477 struct intel_connector *intel_connector = to_intel_connector(connector); 478 struct drm_device *dev = connector->dev; 479 struct drm_display_mode *mode; 480 481 /* use cached edid if we have one */ 482 if (!IS_ERR_OR_NULL(intel_connector->edid)) 483 return drm_add_edid_modes(connector, intel_connector->edid); 484 485 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); 486 if (mode == NULL) 487 return 0; 488 489 drm_mode_probed_add(connector, mode); 490 return 1; 491 } 492 493 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 494 .get_modes = intel_lvds_get_modes, 495 .mode_valid = intel_lvds_mode_valid, 496 .atomic_check = intel_digital_connector_atomic_check, 497 }; 498 499 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 500 .detect = intel_panel_detect, 501 .fill_modes = drm_helper_probe_single_connector_modes, 502 .atomic_get_property = intel_digital_connector_atomic_get_property, 503 .atomic_set_property = intel_digital_connector_atomic_set_property, 504 .late_register = intel_connector_register, 505 .early_unregister = intel_connector_unregister, 506 .destroy = intel_connector_destroy, 507 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 508 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 509 }; 510 511 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 512 .destroy = intel_encoder_destroy, 513 }; 514 515 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 516 { 517 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 518 return 1; 519 } 520 521 /* These systems claim to have LVDS, but really don't */ 522 static const struct dmi_system_id intel_no_lvds[] = { 523 { 524 .callback = intel_no_lvds_dmi_callback, 525 .ident = "Apple Mac Mini (Core series)", 526 .matches = { 527 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 528 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 529 }, 530 }, 531 { 532 .callback = intel_no_lvds_dmi_callback, 533 .ident = "Apple Mac Mini (Core 2 series)", 534 .matches = { 535 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 536 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 537 }, 538 }, 539 { 540 .callback = intel_no_lvds_dmi_callback, 541 .ident = "MSI IM-945GSE-A", 542 .matches = { 543 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 544 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 545 }, 546 }, 547 { 548 .callback = intel_no_lvds_dmi_callback, 549 .ident = "Dell Studio Hybrid", 550 .matches = { 551 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 552 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 553 }, 554 }, 555 { 556 .callback = intel_no_lvds_dmi_callback, 557 .ident = "Dell OptiPlex FX170", 558 .matches = { 559 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 560 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 561 }, 562 }, 563 { 564 .callback = intel_no_lvds_dmi_callback, 565 .ident = "AOpen Mini PC", 566 .matches = { 567 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 568 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 569 }, 570 }, 571 { 572 .callback = intel_no_lvds_dmi_callback, 573 .ident = "AOpen Mini PC MP915", 574 .matches = { 575 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 576 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 577 }, 578 }, 579 { 580 .callback = intel_no_lvds_dmi_callback, 581 .ident = "AOpen i915GMm-HFS", 582 .matches = { 583 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 584 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 585 }, 586 }, 587 { 588 .callback = intel_no_lvds_dmi_callback, 589 .ident = "AOpen i45GMx-I", 590 .matches = { 591 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 592 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 593 }, 594 }, 595 { 596 .callback = intel_no_lvds_dmi_callback, 597 .ident = "Aopen i945GTt-VFA", 598 .matches = { 599 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 600 }, 601 }, 602 { 603 .callback = intel_no_lvds_dmi_callback, 604 .ident = "Clientron U800", 605 .matches = { 606 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 607 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 608 }, 609 }, 610 { 611 .callback = intel_no_lvds_dmi_callback, 612 .ident = "Clientron E830", 613 .matches = { 614 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 615 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 616 }, 617 }, 618 { 619 .callback = intel_no_lvds_dmi_callback, 620 .ident = "Asus EeeBox PC EB1007", 621 .matches = { 622 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 623 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 624 }, 625 }, 626 { 627 .callback = intel_no_lvds_dmi_callback, 628 .ident = "Asus AT5NM10T-I", 629 .matches = { 630 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 631 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 632 }, 633 }, 634 { 635 .callback = intel_no_lvds_dmi_callback, 636 .ident = "Hewlett-Packard HP t5740", 637 .matches = { 638 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 639 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 640 }, 641 }, 642 { 643 .callback = intel_no_lvds_dmi_callback, 644 .ident = "Hewlett-Packard t5745", 645 .matches = { 646 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 647 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 648 }, 649 }, 650 { 651 .callback = intel_no_lvds_dmi_callback, 652 .ident = "Hewlett-Packard st5747", 653 .matches = { 654 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 655 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 656 }, 657 }, 658 { 659 .callback = intel_no_lvds_dmi_callback, 660 .ident = "MSI Wind Box DC500", 661 .matches = { 662 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 663 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 664 }, 665 }, 666 { 667 .callback = intel_no_lvds_dmi_callback, 668 .ident = "Gigabyte GA-D525TUD", 669 .matches = { 670 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 671 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 672 }, 673 }, 674 { 675 .callback = intel_no_lvds_dmi_callback, 676 .ident = "Supermicro X7SPA-H", 677 .matches = { 678 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 679 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 680 }, 681 }, 682 { 683 .callback = intel_no_lvds_dmi_callback, 684 .ident = "Fujitsu Esprimo Q900", 685 .matches = { 686 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 687 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 688 }, 689 }, 690 { 691 .callback = intel_no_lvds_dmi_callback, 692 .ident = "Intel D410PT", 693 .matches = { 694 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 695 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 696 }, 697 }, 698 { 699 .callback = intel_no_lvds_dmi_callback, 700 .ident = "Intel D425KT", 701 .matches = { 702 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 703 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 704 }, 705 }, 706 { 707 .callback = intel_no_lvds_dmi_callback, 708 .ident = "Intel D510MO", 709 .matches = { 710 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 711 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 712 }, 713 }, 714 { 715 .callback = intel_no_lvds_dmi_callback, 716 .ident = "Intel D525MW", 717 .matches = { 718 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 719 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 720 }, 721 }, 722 { 723 .callback = intel_no_lvds_dmi_callback, 724 .ident = "Radiant P845", 725 .matches = { 726 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 727 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 728 }, 729 }, 730 731 { } /* terminating entry */ 732 }; 733 734 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 735 { 736 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 737 return 1; 738 } 739 740 static const struct dmi_system_id intel_dual_link_lvds[] = { 741 { 742 .callback = intel_dual_link_lvds_callback, 743 .ident = "Apple MacBook Pro 15\" (2010)", 744 .matches = { 745 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 746 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 747 }, 748 }, 749 { 750 .callback = intel_dual_link_lvds_callback, 751 .ident = "Apple MacBook Pro 15\" (2011)", 752 .matches = { 753 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 754 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 755 }, 756 }, 757 { 758 .callback = intel_dual_link_lvds_callback, 759 .ident = "Apple MacBook Pro 15\" (2012)", 760 .matches = { 761 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 762 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 763 }, 764 }, 765 { } /* terminating entry */ 766 }; 767 768 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 769 { 770 struct intel_encoder *encoder; 771 772 for_each_intel_encoder(&dev_priv->drm, encoder) { 773 if (encoder->type == INTEL_OUTPUT_LVDS) 774 return encoder; 775 } 776 777 return NULL; 778 } 779 780 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 781 { 782 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 783 784 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 785 } 786 787 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 788 { 789 struct drm_device *dev = lvds_encoder->base.base.dev; 790 unsigned int val; 791 struct drm_i915_private *dev_priv = to_i915(dev); 792 793 /* use the module option value if specified */ 794 if (dev_priv->params.lvds_channel_mode > 0) 795 return dev_priv->params.lvds_channel_mode == 2; 796 797 /* single channel LVDS is limited to 112 MHz */ 798 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) 799 return true; 800 801 if (dmi_check_system(intel_dual_link_lvds)) 802 return true; 803 804 /* 805 * BIOS should set the proper LVDS register value at boot, but 806 * in reality, it doesn't set the value when the lid is closed; 807 * we need to check "the value to be set" in VBT when LVDS 808 * register is uninitialized. 809 */ 810 val = intel_de_read(dev_priv, lvds_encoder->reg); 811 if (HAS_PCH_CPT(dev_priv)) 812 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 813 else 814 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 815 if (val == 0) 816 val = dev_priv->vbt.bios_lvds_val; 817 818 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 819 } 820 821 /** 822 * intel_lvds_init - setup LVDS connectors on this device 823 * @dev_priv: i915 device 824 * 825 * Create the connector, register the LVDS DDC bus, and try to figure out what 826 * modes we can display on the LVDS panel (if present). 827 */ 828 void intel_lvds_init(struct drm_i915_private *dev_priv) 829 { 830 struct drm_device *dev = &dev_priv->drm; 831 struct intel_lvds_encoder *lvds_encoder; 832 struct intel_encoder *intel_encoder; 833 struct intel_connector *intel_connector; 834 struct drm_connector *connector; 835 struct drm_encoder *encoder; 836 struct drm_display_mode *fixed_mode = NULL; 837 struct drm_display_mode *downclock_mode = NULL; 838 struct edid *edid; 839 i915_reg_t lvds_reg; 840 u32 lvds; 841 u8 pin; 842 u32 allowed_scalers; 843 844 /* Skip init on machines we know falsely report LVDS */ 845 if (dmi_check_system(intel_no_lvds)) { 846 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, 847 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 848 return; 849 } 850 851 if (!dev_priv->vbt.int_lvds_support) { 852 drm_dbg_kms(&dev_priv->drm, 853 "Internal LVDS support disabled by VBT\n"); 854 return; 855 } 856 857 if (HAS_PCH_SPLIT(dev_priv)) 858 lvds_reg = PCH_LVDS; 859 else 860 lvds_reg = LVDS; 861 862 lvds = intel_de_read(dev_priv, lvds_reg); 863 864 if (HAS_PCH_SPLIT(dev_priv)) { 865 if ((lvds & LVDS_DETECTED) == 0) 866 return; 867 } 868 869 pin = GMBUS_PIN_PANEL; 870 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 871 if ((lvds & LVDS_PORT_EN) == 0) { 872 drm_dbg_kms(&dev_priv->drm, 873 "LVDS is not present in VBT\n"); 874 return; 875 } 876 drm_dbg_kms(&dev_priv->drm, 877 "LVDS is not present in VBT, but enabled anyway\n"); 878 } 879 880 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 881 if (!lvds_encoder) 882 return; 883 884 intel_connector = intel_connector_alloc(); 885 if (!intel_connector) { 886 kfree(lvds_encoder); 887 return; 888 } 889 890 lvds_encoder->attached_connector = intel_connector; 891 892 intel_encoder = &lvds_encoder->base; 893 encoder = &intel_encoder->base; 894 connector = &intel_connector->base; 895 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 896 DRM_MODE_CONNECTOR_LVDS); 897 898 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 899 DRM_MODE_ENCODER_LVDS, "LVDS"); 900 901 intel_encoder->enable = intel_enable_lvds; 902 intel_encoder->pre_enable = intel_pre_enable_lvds; 903 intel_encoder->compute_config = intel_lvds_compute_config; 904 if (HAS_PCH_SPLIT(dev_priv)) { 905 intel_encoder->disable = pch_disable_lvds; 906 intel_encoder->post_disable = pch_post_disable_lvds; 907 } else { 908 intel_encoder->disable = gmch_disable_lvds; 909 } 910 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 911 intel_encoder->get_config = intel_lvds_get_config; 912 intel_encoder->update_pipe = intel_backlight_update; 913 intel_encoder->shutdown = intel_lvds_shutdown; 914 intel_connector->get_hw_state = intel_connector_get_hw_state; 915 916 intel_connector_attach_encoder(intel_connector, intel_encoder); 917 918 intel_encoder->type = INTEL_OUTPUT_LVDS; 919 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 920 intel_encoder->port = PORT_NONE; 921 intel_encoder->cloneable = 0; 922 if (DISPLAY_VER(dev_priv) < 4) 923 intel_encoder->pipe_mask = BIT(PIPE_B); 924 else 925 intel_encoder->pipe_mask = ~0; 926 927 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 928 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 929 connector->interlace_allowed = false; 930 connector->doublescan_allowed = false; 931 932 lvds_encoder->reg = lvds_reg; 933 934 /* create the scaling mode property */ 935 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); 936 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); 937 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 938 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 939 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 940 941 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 942 lvds_encoder->init_lvds_val = lvds; 943 944 /* 945 * LVDS discovery: 946 * 1) check for EDID on DDC 947 * 2) check for VBT data 948 * 3) check to see if LVDS is already on 949 * if none of the above, no panel 950 */ 951 952 /* 953 * Attempt to get the fixed panel mode from DDC. Assume that the 954 * preferred mode is the right one. 955 */ 956 mutex_lock(&dev->mode_config.mutex); 957 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 958 edid = drm_get_edid_switcheroo(connector, 959 intel_gmbus_get_adapter(dev_priv, pin)); 960 else 961 edid = drm_get_edid(connector, 962 intel_gmbus_get_adapter(dev_priv, pin)); 963 if (edid) { 964 if (drm_add_edid_modes(connector, edid)) { 965 drm_connector_update_edid_property(connector, 966 edid); 967 } else { 968 kfree(edid); 969 edid = ERR_PTR(-EINVAL); 970 } 971 } else { 972 edid = ERR_PTR(-ENOENT); 973 } 974 intel_connector->edid = edid; 975 976 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 977 if (fixed_mode) 978 goto out; 979 980 /* Failed to get EDID, what about VBT? */ 981 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 982 if (fixed_mode) 983 goto out; 984 985 /* 986 * If we didn't get EDID, try checking if the panel is already turned 987 * on. If so, assume that whatever is currently programmed is the 988 * correct mode. 989 */ 990 fixed_mode = intel_encoder_current_mode(intel_encoder); 991 if (fixed_mode) { 992 drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: "); 993 drm_mode_debug_printmodeline(fixed_mode); 994 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 995 } 996 997 /* If we still don't have a mode after all that, give up. */ 998 if (!fixed_mode) 999 goto failed; 1000 1001 out: 1002 mutex_unlock(&dev->mode_config.mutex); 1003 1004 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1005 intel_backlight_setup(intel_connector, INVALID_PIPE); 1006 1007 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1008 drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", 1009 lvds_encoder->is_dual_link ? "dual" : "single"); 1010 1011 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1012 1013 return; 1014 1015 failed: 1016 mutex_unlock(&dev->mode_config.mutex); 1017 1018 drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); 1019 drm_connector_cleanup(connector); 1020 drm_encoder_cleanup(encoder); 1021 kfree(lvds_encoder); 1022 intel_connector_free(intel_connector); 1023 return; 1024 } 1025