1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <acpi/button.h> 31 #include <linux/acpi.h> 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 41 #include "i915_drv.h" 42 #include "intel_atomic.h" 43 #include "intel_connector.h" 44 #include "intel_display_types.h" 45 #include "intel_gmbus.h" 46 #include "intel_lvds.h" 47 #include "intel_panel.h" 48 49 /* Private structure for the integrated LVDS support */ 50 struct intel_lvds_pps { 51 /* 100us units */ 52 int t1_t2; 53 int t3; 54 int t4; 55 int t5; 56 int tx; 57 58 int divider; 59 60 int port; 61 bool powerdown_on_reset; 62 }; 63 64 struct intel_lvds_encoder { 65 struct intel_encoder base; 66 67 bool is_dual_link; 68 i915_reg_t reg; 69 u32 a3_power; 70 71 struct intel_lvds_pps init_pps; 72 u32 init_lvds_val; 73 74 struct intel_connector *attached_connector; 75 }; 76 77 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 78 { 79 return container_of(encoder, struct intel_lvds_encoder, base.base); 80 } 81 82 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, 83 i915_reg_t lvds_reg, enum pipe *pipe) 84 { 85 u32 val; 86 87 val = intel_de_read(dev_priv, lvds_reg); 88 89 /* asserts want to know the pipe even if the port is disabled */ 90 if (HAS_PCH_CPT(dev_priv)) 91 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT; 92 else 93 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT; 94 95 return val & LVDS_PORT_EN; 96 } 97 98 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 99 enum pipe *pipe) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 103 intel_wakeref_t wakeref; 104 bool ret; 105 106 wakeref = intel_display_power_get_if_enabled(dev_priv, 107 encoder->power_domain); 108 if (!wakeref) 109 return false; 110 111 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); 112 113 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 114 115 return ret; 116 } 117 118 static void intel_lvds_get_config(struct intel_encoder *encoder, 119 struct intel_crtc_state *pipe_config) 120 { 121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 122 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 123 u32 tmp, flags = 0; 124 125 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); 126 127 tmp = intel_de_read(dev_priv, lvds_encoder->reg); 128 if (tmp & LVDS_HSYNC_POLARITY) 129 flags |= DRM_MODE_FLAG_NHSYNC; 130 else 131 flags |= DRM_MODE_FLAG_PHSYNC; 132 if (tmp & LVDS_VSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NVSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PVSYNC; 136 137 pipe_config->hw.adjusted_mode.flags |= flags; 138 139 if (INTEL_GEN(dev_priv) < 5) 140 pipe_config->gmch_pfit.lvds_border_bits = 141 tmp & LVDS_BORDER_ENABLE; 142 143 /* gen2/3 store dither state in pfit control, needs to match */ 144 if (INTEL_GEN(dev_priv) < 4) { 145 tmp = intel_de_read(dev_priv, PFIT_CONTROL); 146 147 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 148 } 149 150 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 151 } 152 153 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 154 struct intel_lvds_pps *pps) 155 { 156 u32 val; 157 158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; 159 160 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); 161 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 162 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 163 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 164 165 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); 166 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 167 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 168 169 val = intel_de_read(dev_priv, PP_DIVISOR(0)); 170 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); 171 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); 172 /* 173 * Remove the BSpec specified +1 (100ms) offset that accounts for a 174 * too short power-cycle delay due to the asynchronous programming of 175 * the register. 176 */ 177 if (val) 178 val--; 179 /* Convert from 100ms to 100us units */ 180 pps->t4 = val * 1000; 181 182 if (INTEL_GEN(dev_priv) <= 4 && 183 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 184 DRM_DEBUG_KMS("Panel power timings uninitialized, " 185 "setting defaults\n"); 186 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 187 pps->t1_t2 = 40 * 10; 188 pps->t5 = 200 * 10; 189 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 190 pps->t3 = 35 * 10; 191 pps->tx = 200 * 10; 192 } 193 194 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 195 "divider %d port %d powerdown_on_reset %d\n", 196 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 197 pps->divider, pps->port, pps->powerdown_on_reset); 198 } 199 200 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 201 struct intel_lvds_pps *pps) 202 { 203 u32 val; 204 205 val = intel_de_read(dev_priv, PP_CONTROL(0)); 206 drm_WARN_ON(&dev_priv->drm, 207 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 208 if (pps->powerdown_on_reset) 209 val |= PANEL_POWER_RESET; 210 intel_de_write(dev_priv, PP_CONTROL(0), val); 211 212 intel_de_write(dev_priv, PP_ON_DELAYS(0), 213 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 214 215 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 216 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 217 218 intel_de_write(dev_priv, PP_DIVISOR(0), 219 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 220 } 221 222 static void intel_pre_enable_lvds(struct intel_encoder *encoder, 223 const struct intel_crtc_state *pipe_config, 224 const struct drm_connector_state *conn_state) 225 { 226 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 228 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 229 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 230 enum pipe pipe = crtc->pipe; 231 u32 temp; 232 233 if (HAS_PCH_SPLIT(dev_priv)) { 234 assert_fdi_rx_pll_disabled(dev_priv, pipe); 235 assert_shared_dpll_disabled(dev_priv, 236 pipe_config->shared_dpll); 237 } else { 238 assert_pll_disabled(dev_priv, pipe); 239 } 240 241 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 242 243 temp = lvds_encoder->init_lvds_val; 244 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 245 246 if (HAS_PCH_CPT(dev_priv)) { 247 temp &= ~LVDS_PIPE_SEL_MASK_CPT; 248 temp |= LVDS_PIPE_SEL_CPT(pipe); 249 } else { 250 temp &= ~LVDS_PIPE_SEL_MASK; 251 temp |= LVDS_PIPE_SEL(pipe); 252 } 253 254 /* set the corresponsding LVDS_BORDER bit */ 255 temp &= ~LVDS_BORDER_ENABLE; 256 temp |= pipe_config->gmch_pfit.lvds_border_bits; 257 258 /* 259 * Set the B0-B3 data pairs corresponding to whether we're going to 260 * set the DPLLs for dual-channel mode or not. 261 */ 262 if (lvds_encoder->is_dual_link) 263 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 264 else 265 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 266 267 /* 268 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 269 * appropriately here, but we need to look more thoroughly into how 270 * panels behave in the two modes. For now, let's just maintain the 271 * value we got from the BIOS. 272 */ 273 temp &= ~LVDS_A3_POWER_MASK; 274 temp |= lvds_encoder->a3_power; 275 276 /* 277 * Set the dithering flag on LVDS as needed, note that there is no 278 * special lvds dither control bit on pch-split platforms, dithering is 279 * only controlled through the PIPECONF reg. 280 */ 281 if (IS_GEN(dev_priv, 4)) { 282 /* 283 * Bspec wording suggests that LVDS port dithering only exists 284 * for 18bpp panels. 285 */ 286 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 287 temp |= LVDS_ENABLE_DITHER; 288 else 289 temp &= ~LVDS_ENABLE_DITHER; 290 } 291 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 292 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 293 temp |= LVDS_HSYNC_POLARITY; 294 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 295 temp |= LVDS_VSYNC_POLARITY; 296 297 intel_de_write(dev_priv, lvds_encoder->reg, temp); 298 } 299 300 /* 301 * Sets the power state for the panel. 302 */ 303 static void intel_enable_lvds(struct intel_encoder *encoder, 304 const struct intel_crtc_state *pipe_config, 305 const struct drm_connector_state *conn_state) 306 { 307 struct drm_device *dev = encoder->base.dev; 308 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 309 struct drm_i915_private *dev_priv = to_i915(dev); 310 311 intel_de_write(dev_priv, lvds_encoder->reg, 312 intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); 313 314 intel_de_write(dev_priv, PP_CONTROL(0), 315 intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); 316 intel_de_posting_read(dev_priv, lvds_encoder->reg); 317 318 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) 319 DRM_ERROR("timed out waiting for panel to power on\n"); 320 321 intel_panel_enable_backlight(pipe_config, conn_state); 322 } 323 324 static void intel_disable_lvds(struct intel_encoder *encoder, 325 const struct intel_crtc_state *old_crtc_state, 326 const struct drm_connector_state *old_conn_state) 327 { 328 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 331 intel_de_write(dev_priv, PP_CONTROL(0), 332 intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); 333 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) 334 DRM_ERROR("timed out waiting for panel to power off\n"); 335 336 intel_de_write(dev_priv, lvds_encoder->reg, 337 intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); 338 intel_de_posting_read(dev_priv, lvds_encoder->reg); 339 } 340 341 static void gmch_disable_lvds(struct intel_encoder *encoder, 342 const struct intel_crtc_state *old_crtc_state, 343 const struct drm_connector_state *old_conn_state) 344 345 { 346 intel_panel_disable_backlight(old_conn_state); 347 348 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 349 } 350 351 static void pch_disable_lvds(struct intel_encoder *encoder, 352 const struct intel_crtc_state *old_crtc_state, 353 const struct drm_connector_state *old_conn_state) 354 { 355 intel_panel_disable_backlight(old_conn_state); 356 } 357 358 static void pch_post_disable_lvds(struct intel_encoder *encoder, 359 const struct intel_crtc_state *old_crtc_state, 360 const struct drm_connector_state *old_conn_state) 361 { 362 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 363 } 364 365 static enum drm_mode_status 366 intel_lvds_mode_valid(struct drm_connector *connector, 367 struct drm_display_mode *mode) 368 { 369 struct intel_connector *intel_connector = to_intel_connector(connector); 370 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 371 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 372 373 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 374 return MODE_NO_DBLESCAN; 375 if (mode->hdisplay > fixed_mode->hdisplay) 376 return MODE_PANEL; 377 if (mode->vdisplay > fixed_mode->vdisplay) 378 return MODE_PANEL; 379 if (fixed_mode->clock > max_pixclk) 380 return MODE_CLOCK_HIGH; 381 382 return MODE_OK; 383 } 384 385 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, 386 struct intel_crtc_state *pipe_config, 387 struct drm_connector_state *conn_state) 388 { 389 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 390 struct intel_lvds_encoder *lvds_encoder = 391 to_lvds_encoder(&intel_encoder->base); 392 struct intel_connector *intel_connector = 393 lvds_encoder->attached_connector; 394 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 395 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 396 unsigned int lvds_bpp; 397 398 /* Should never happen!! */ 399 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { 400 DRM_ERROR("Can't support LVDS on pipe A\n"); 401 return -EINVAL; 402 } 403 404 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 405 lvds_bpp = 8*3; 406 else 407 lvds_bpp = 6*3; 408 409 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 410 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 411 pipe_config->pipe_bpp, lvds_bpp); 412 pipe_config->pipe_bpp = lvds_bpp; 413 } 414 415 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 416 417 /* 418 * We have timings from the BIOS for the panel, put them in 419 * to the adjusted mode. The CRTC will be set up for this mode, 420 * with the panel scaling set up to source from the H/VDisplay 421 * of the original mode. 422 */ 423 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 424 adjusted_mode); 425 426 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 427 return -EINVAL; 428 429 if (HAS_PCH_SPLIT(dev_priv)) { 430 pipe_config->has_pch_encoder = true; 431 432 intel_pch_panel_fitting(intel_crtc, pipe_config, 433 conn_state->scaling_mode); 434 } else { 435 intel_gmch_panel_fitting(intel_crtc, pipe_config, 436 conn_state->scaling_mode); 437 438 } 439 440 /* 441 * XXX: It would be nice to support lower refresh rates on the 442 * panels to reduce power consumption, and perhaps match the 443 * user's requested refresh rate. 444 */ 445 446 return 0; 447 } 448 449 static enum drm_connector_status 450 intel_lvds_detect(struct drm_connector *connector, bool force) 451 { 452 return connector_status_connected; 453 } 454 455 /* 456 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 457 */ 458 static int intel_lvds_get_modes(struct drm_connector *connector) 459 { 460 struct intel_connector *intel_connector = to_intel_connector(connector); 461 struct drm_device *dev = connector->dev; 462 struct drm_display_mode *mode; 463 464 /* use cached edid if we have one */ 465 if (!IS_ERR_OR_NULL(intel_connector->edid)) 466 return drm_add_edid_modes(connector, intel_connector->edid); 467 468 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); 469 if (mode == NULL) 470 return 0; 471 472 drm_mode_probed_add(connector, mode); 473 return 1; 474 } 475 476 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 477 .get_modes = intel_lvds_get_modes, 478 .mode_valid = intel_lvds_mode_valid, 479 .atomic_check = intel_digital_connector_atomic_check, 480 }; 481 482 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 483 .detect = intel_lvds_detect, 484 .fill_modes = drm_helper_probe_single_connector_modes, 485 .atomic_get_property = intel_digital_connector_atomic_get_property, 486 .atomic_set_property = intel_digital_connector_atomic_set_property, 487 .late_register = intel_connector_register, 488 .early_unregister = intel_connector_unregister, 489 .destroy = intel_connector_destroy, 490 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 491 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 492 }; 493 494 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 495 .destroy = intel_encoder_destroy, 496 }; 497 498 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 499 { 500 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 501 return 1; 502 } 503 504 /* These systems claim to have LVDS, but really don't */ 505 static const struct dmi_system_id intel_no_lvds[] = { 506 { 507 .callback = intel_no_lvds_dmi_callback, 508 .ident = "Apple Mac Mini (Core series)", 509 .matches = { 510 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 511 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 512 }, 513 }, 514 { 515 .callback = intel_no_lvds_dmi_callback, 516 .ident = "Apple Mac Mini (Core 2 series)", 517 .matches = { 518 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 519 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 520 }, 521 }, 522 { 523 .callback = intel_no_lvds_dmi_callback, 524 .ident = "MSI IM-945GSE-A", 525 .matches = { 526 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 527 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 528 }, 529 }, 530 { 531 .callback = intel_no_lvds_dmi_callback, 532 .ident = "Dell Studio Hybrid", 533 .matches = { 534 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 535 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 536 }, 537 }, 538 { 539 .callback = intel_no_lvds_dmi_callback, 540 .ident = "Dell OptiPlex FX170", 541 .matches = { 542 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 543 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 544 }, 545 }, 546 { 547 .callback = intel_no_lvds_dmi_callback, 548 .ident = "AOpen Mini PC", 549 .matches = { 550 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 551 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 552 }, 553 }, 554 { 555 .callback = intel_no_lvds_dmi_callback, 556 .ident = "AOpen Mini PC MP915", 557 .matches = { 558 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 559 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 560 }, 561 }, 562 { 563 .callback = intel_no_lvds_dmi_callback, 564 .ident = "AOpen i915GMm-HFS", 565 .matches = { 566 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 567 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 568 }, 569 }, 570 { 571 .callback = intel_no_lvds_dmi_callback, 572 .ident = "AOpen i45GMx-I", 573 .matches = { 574 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 575 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 576 }, 577 }, 578 { 579 .callback = intel_no_lvds_dmi_callback, 580 .ident = "Aopen i945GTt-VFA", 581 .matches = { 582 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 583 }, 584 }, 585 { 586 .callback = intel_no_lvds_dmi_callback, 587 .ident = "Clientron U800", 588 .matches = { 589 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 590 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 591 }, 592 }, 593 { 594 .callback = intel_no_lvds_dmi_callback, 595 .ident = "Clientron E830", 596 .matches = { 597 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 598 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 599 }, 600 }, 601 { 602 .callback = intel_no_lvds_dmi_callback, 603 .ident = "Asus EeeBox PC EB1007", 604 .matches = { 605 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 606 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 607 }, 608 }, 609 { 610 .callback = intel_no_lvds_dmi_callback, 611 .ident = "Asus AT5NM10T-I", 612 .matches = { 613 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 614 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 615 }, 616 }, 617 { 618 .callback = intel_no_lvds_dmi_callback, 619 .ident = "Hewlett-Packard HP t5740", 620 .matches = { 621 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 622 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 623 }, 624 }, 625 { 626 .callback = intel_no_lvds_dmi_callback, 627 .ident = "Hewlett-Packard t5745", 628 .matches = { 629 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 630 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 631 }, 632 }, 633 { 634 .callback = intel_no_lvds_dmi_callback, 635 .ident = "Hewlett-Packard st5747", 636 .matches = { 637 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 638 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 639 }, 640 }, 641 { 642 .callback = intel_no_lvds_dmi_callback, 643 .ident = "MSI Wind Box DC500", 644 .matches = { 645 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 646 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 647 }, 648 }, 649 { 650 .callback = intel_no_lvds_dmi_callback, 651 .ident = "Gigabyte GA-D525TUD", 652 .matches = { 653 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 654 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 655 }, 656 }, 657 { 658 .callback = intel_no_lvds_dmi_callback, 659 .ident = "Supermicro X7SPA-H", 660 .matches = { 661 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 662 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 663 }, 664 }, 665 { 666 .callback = intel_no_lvds_dmi_callback, 667 .ident = "Fujitsu Esprimo Q900", 668 .matches = { 669 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 670 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 671 }, 672 }, 673 { 674 .callback = intel_no_lvds_dmi_callback, 675 .ident = "Intel D410PT", 676 .matches = { 677 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 678 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 679 }, 680 }, 681 { 682 .callback = intel_no_lvds_dmi_callback, 683 .ident = "Intel D425KT", 684 .matches = { 685 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 686 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 687 }, 688 }, 689 { 690 .callback = intel_no_lvds_dmi_callback, 691 .ident = "Intel D510MO", 692 .matches = { 693 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 694 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 695 }, 696 }, 697 { 698 .callback = intel_no_lvds_dmi_callback, 699 .ident = "Intel D525MW", 700 .matches = { 701 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 702 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 703 }, 704 }, 705 { 706 .callback = intel_no_lvds_dmi_callback, 707 .ident = "Radiant P845", 708 .matches = { 709 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"), 710 DMI_MATCH(DMI_PRODUCT_NAME, "P845"), 711 }, 712 }, 713 714 { } /* terminating entry */ 715 }; 716 717 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 718 { 719 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 720 return 1; 721 } 722 723 static const struct dmi_system_id intel_dual_link_lvds[] = { 724 { 725 .callback = intel_dual_link_lvds_callback, 726 .ident = "Apple MacBook Pro 15\" (2010)", 727 .matches = { 728 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 729 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 730 }, 731 }, 732 { 733 .callback = intel_dual_link_lvds_callback, 734 .ident = "Apple MacBook Pro 15\" (2011)", 735 .matches = { 736 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 737 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 738 }, 739 }, 740 { 741 .callback = intel_dual_link_lvds_callback, 742 .ident = "Apple MacBook Pro 15\" (2012)", 743 .matches = { 744 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 745 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 746 }, 747 }, 748 { } /* terminating entry */ 749 }; 750 751 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv) 752 { 753 struct intel_encoder *encoder; 754 755 for_each_intel_encoder(&dev_priv->drm, encoder) { 756 if (encoder->type == INTEL_OUTPUT_LVDS) 757 return encoder; 758 } 759 760 return NULL; 761 } 762 763 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv) 764 { 765 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv); 766 767 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 768 } 769 770 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 771 { 772 struct drm_device *dev = lvds_encoder->base.base.dev; 773 unsigned int val; 774 struct drm_i915_private *dev_priv = to_i915(dev); 775 776 /* use the module option value if specified */ 777 if (i915_modparams.lvds_channel_mode > 0) 778 return i915_modparams.lvds_channel_mode == 2; 779 780 /* single channel LVDS is limited to 112 MHz */ 781 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) 782 return true; 783 784 if (dmi_check_system(intel_dual_link_lvds)) 785 return true; 786 787 /* 788 * BIOS should set the proper LVDS register value at boot, but 789 * in reality, it doesn't set the value when the lid is closed; 790 * we need to check "the value to be set" in VBT when LVDS 791 * register is uninitialized. 792 */ 793 val = intel_de_read(dev_priv, lvds_encoder->reg); 794 if (HAS_PCH_CPT(dev_priv)) 795 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); 796 else 797 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK); 798 if (val == 0) 799 val = dev_priv->vbt.bios_lvds_val; 800 801 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 802 } 803 804 /** 805 * intel_lvds_init - setup LVDS connectors on this device 806 * @dev_priv: i915 device 807 * 808 * Create the connector, register the LVDS DDC bus, and try to figure out what 809 * modes we can display on the LVDS panel (if present). 810 */ 811 void intel_lvds_init(struct drm_i915_private *dev_priv) 812 { 813 struct drm_device *dev = &dev_priv->drm; 814 struct intel_lvds_encoder *lvds_encoder; 815 struct intel_encoder *intel_encoder; 816 struct intel_connector *intel_connector; 817 struct drm_connector *connector; 818 struct drm_encoder *encoder; 819 struct drm_display_mode *fixed_mode = NULL; 820 struct drm_display_mode *downclock_mode = NULL; 821 struct edid *edid; 822 i915_reg_t lvds_reg; 823 u32 lvds; 824 u8 pin; 825 u32 allowed_scalers; 826 827 /* Skip init on machines we know falsely report LVDS */ 828 if (dmi_check_system(intel_no_lvds)) { 829 drm_WARN(dev, !dev_priv->vbt.int_lvds_support, 830 "Useless DMI match. Internal LVDS support disabled by VBT\n"); 831 return; 832 } 833 834 if (!dev_priv->vbt.int_lvds_support) { 835 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n"); 836 return; 837 } 838 839 if (HAS_PCH_SPLIT(dev_priv)) 840 lvds_reg = PCH_LVDS; 841 else 842 lvds_reg = LVDS; 843 844 lvds = intel_de_read(dev_priv, lvds_reg); 845 846 if (HAS_PCH_SPLIT(dev_priv)) { 847 if ((lvds & LVDS_DETECTED) == 0) 848 return; 849 } 850 851 pin = GMBUS_PIN_PANEL; 852 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 853 if ((lvds & LVDS_PORT_EN) == 0) { 854 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 855 return; 856 } 857 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 858 } 859 860 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 861 if (!lvds_encoder) 862 return; 863 864 intel_connector = intel_connector_alloc(); 865 if (!intel_connector) { 866 kfree(lvds_encoder); 867 return; 868 } 869 870 lvds_encoder->attached_connector = intel_connector; 871 872 intel_encoder = &lvds_encoder->base; 873 encoder = &intel_encoder->base; 874 connector = &intel_connector->base; 875 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 876 DRM_MODE_CONNECTOR_LVDS); 877 878 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 879 DRM_MODE_ENCODER_LVDS, "LVDS"); 880 881 intel_encoder->enable = intel_enable_lvds; 882 intel_encoder->pre_enable = intel_pre_enable_lvds; 883 intel_encoder->compute_config = intel_lvds_compute_config; 884 if (HAS_PCH_SPLIT(dev_priv)) { 885 intel_encoder->disable = pch_disable_lvds; 886 intel_encoder->post_disable = pch_post_disable_lvds; 887 } else { 888 intel_encoder->disable = gmch_disable_lvds; 889 } 890 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 891 intel_encoder->get_config = intel_lvds_get_config; 892 intel_encoder->update_pipe = intel_panel_update_backlight; 893 intel_connector->get_hw_state = intel_connector_get_hw_state; 894 895 intel_connector_attach_encoder(intel_connector, intel_encoder); 896 897 intel_encoder->type = INTEL_OUTPUT_LVDS; 898 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; 899 intel_encoder->port = PORT_NONE; 900 intel_encoder->cloneable = 0; 901 if (INTEL_GEN(dev_priv) < 4) 902 intel_encoder->pipe_mask = BIT(PIPE_B); 903 else 904 intel_encoder->pipe_mask = ~0; 905 906 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 907 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 908 connector->interlace_allowed = false; 909 connector->doublescan_allowed = false; 910 911 lvds_encoder->reg = lvds_reg; 912 913 /* create the scaling mode property */ 914 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); 915 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); 916 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 917 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 918 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 919 920 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 921 lvds_encoder->init_lvds_val = lvds; 922 923 /* 924 * LVDS discovery: 925 * 1) check for EDID on DDC 926 * 2) check for VBT data 927 * 3) check to see if LVDS is already on 928 * if none of the above, no panel 929 */ 930 931 /* 932 * Attempt to get the fixed panel mode from DDC. Assume that the 933 * preferred mode is the right one. 934 */ 935 mutex_lock(&dev->mode_config.mutex); 936 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 937 edid = drm_get_edid_switcheroo(connector, 938 intel_gmbus_get_adapter(dev_priv, pin)); 939 else 940 edid = drm_get_edid(connector, 941 intel_gmbus_get_adapter(dev_priv, pin)); 942 if (edid) { 943 if (drm_add_edid_modes(connector, edid)) { 944 drm_connector_update_edid_property(connector, 945 edid); 946 } else { 947 kfree(edid); 948 edid = ERR_PTR(-EINVAL); 949 } 950 } else { 951 edid = ERR_PTR(-ENOENT); 952 } 953 intel_connector->edid = edid; 954 955 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 956 if (fixed_mode) 957 goto out; 958 959 /* Failed to get EDID, what about VBT? */ 960 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 961 if (fixed_mode) 962 goto out; 963 964 /* 965 * If we didn't get EDID, try checking if the panel is already turned 966 * on. If so, assume that whatever is currently programmed is the 967 * correct mode. 968 */ 969 fixed_mode = intel_encoder_current_mode(intel_encoder); 970 if (fixed_mode) { 971 DRM_DEBUG_KMS("using current (BIOS) mode: "); 972 drm_mode_debug_printmodeline(fixed_mode); 973 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 974 } 975 976 /* If we still don't have a mode after all that, give up. */ 977 if (!fixed_mode) 978 goto failed; 979 980 out: 981 mutex_unlock(&dev->mode_config.mutex); 982 983 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 984 intel_panel_setup_backlight(connector, INVALID_PIPE); 985 986 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 987 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 988 lvds_encoder->is_dual_link ? "dual" : "single"); 989 990 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 991 992 return; 993 994 failed: 995 mutex_unlock(&dev->mode_config.mutex); 996 997 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 998 drm_connector_cleanup(connector); 999 drm_encoder_cleanup(encoder); 1000 kfree(lvds_encoder); 1001 intel_connector_free(intel_connector); 1002 return; 1003 } 1004