1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *	Eric Anholt <eric@anholt.net>
26  *      Dave Airlie <airlied@linux.ie>
27  *      Jesse Barnes <jesse.barnes@intel.com>
28  */
29 
30 #include <acpi/button.h>
31 #include <linux/acpi.h>
32 #include <linux/dmi.h>
33 #include <linux/i2c.h>
34 #include <linux/slab.h>
35 #include <linux/vga_switcheroo.h>
36 
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_edid.h>
40 #include <drm/i915_drm.h>
41 
42 #include "i915_drv.h"
43 #include "intel_atomic.h"
44 #include "intel_connector.h"
45 #include "intel_drv.h"
46 #include "intel_gmbus.h"
47 #include "intel_lvds.h"
48 #include "intel_panel.h"
49 
50 /* Private structure for the integrated LVDS support */
51 struct intel_lvds_pps {
52 	/* 100us units */
53 	int t1_t2;
54 	int t3;
55 	int t4;
56 	int t5;
57 	int tx;
58 
59 	int divider;
60 
61 	int port;
62 	bool powerdown_on_reset;
63 };
64 
65 struct intel_lvds_encoder {
66 	struct intel_encoder base;
67 
68 	bool is_dual_link;
69 	i915_reg_t reg;
70 	u32 a3_power;
71 
72 	struct intel_lvds_pps init_pps;
73 	u32 init_lvds_val;
74 
75 	struct intel_connector *attached_connector;
76 };
77 
78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
79 {
80 	return container_of(encoder, struct intel_lvds_encoder, base.base);
81 }
82 
83 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
84 			     i915_reg_t lvds_reg, enum pipe *pipe)
85 {
86 	u32 val;
87 
88 	val = I915_READ(lvds_reg);
89 
90 	/* asserts want to know the pipe even if the port is disabled */
91 	if (HAS_PCH_CPT(dev_priv))
92 		*pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
93 	else
94 		*pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
95 
96 	return val & LVDS_PORT_EN;
97 }
98 
99 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
100 				    enum pipe *pipe)
101 {
102 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
103 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
104 	intel_wakeref_t wakeref;
105 	bool ret;
106 
107 	wakeref = intel_display_power_get_if_enabled(dev_priv,
108 						     encoder->power_domain);
109 	if (!wakeref)
110 		return false;
111 
112 	ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
113 
114 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
115 
116 	return ret;
117 }
118 
119 static void intel_lvds_get_config(struct intel_encoder *encoder,
120 				  struct intel_crtc_state *pipe_config)
121 {
122 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
123 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
124 	u32 tmp, flags = 0;
125 
126 	pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
127 
128 	tmp = I915_READ(lvds_encoder->reg);
129 	if (tmp & LVDS_HSYNC_POLARITY)
130 		flags |= DRM_MODE_FLAG_NHSYNC;
131 	else
132 		flags |= DRM_MODE_FLAG_PHSYNC;
133 	if (tmp & LVDS_VSYNC_POLARITY)
134 		flags |= DRM_MODE_FLAG_NVSYNC;
135 	else
136 		flags |= DRM_MODE_FLAG_PVSYNC;
137 
138 	pipe_config->base.adjusted_mode.flags |= flags;
139 
140 	if (INTEL_GEN(dev_priv) < 5)
141 		pipe_config->gmch_pfit.lvds_border_bits =
142 			tmp & LVDS_BORDER_ENABLE;
143 
144 	/* gen2/3 store dither state in pfit control, needs to match */
145 	if (INTEL_GEN(dev_priv) < 4) {
146 		tmp = I915_READ(PFIT_CONTROL);
147 
148 		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
149 	}
150 
151 	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
152 }
153 
154 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
155 					struct intel_lvds_pps *pps)
156 {
157 	u32 val;
158 
159 	pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
160 
161 	val = I915_READ(PP_ON_DELAYS(0));
162 	pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
163 	pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
164 	pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
165 
166 	val = I915_READ(PP_OFF_DELAYS(0));
167 	pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
168 	pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
169 
170 	val = I915_READ(PP_DIVISOR(0));
171 	pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
172 	val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
173 	/*
174 	 * Remove the BSpec specified +1 (100ms) offset that accounts for a
175 	 * too short power-cycle delay due to the asynchronous programming of
176 	 * the register.
177 	 */
178 	if (val)
179 		val--;
180 	/* Convert from 100ms to 100us units */
181 	pps->t4 = val * 1000;
182 
183 	if (INTEL_GEN(dev_priv) <= 4 &&
184 	    pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
185 		DRM_DEBUG_KMS("Panel power timings uninitialized, "
186 			      "setting defaults\n");
187 		/* Set T2 to 40ms and T5 to 200ms in 100 usec units */
188 		pps->t1_t2 = 40 * 10;
189 		pps->t5 = 200 * 10;
190 		/* Set T3 to 35ms and Tx to 200ms in 100 usec units */
191 		pps->t3 = 35 * 10;
192 		pps->tx = 200 * 10;
193 	}
194 
195 	DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
196 			 "divider %d port %d powerdown_on_reset %d\n",
197 			 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
198 			 pps->divider, pps->port, pps->powerdown_on_reset);
199 }
200 
201 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
202 				   struct intel_lvds_pps *pps)
203 {
204 	u32 val;
205 
206 	val = I915_READ(PP_CONTROL(0));
207 	WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
208 	if (pps->powerdown_on_reset)
209 		val |= PANEL_POWER_RESET;
210 	I915_WRITE(PP_CONTROL(0), val);
211 
212 	I915_WRITE(PP_ON_DELAYS(0),
213 		   REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
214 		   REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
215 		   REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
216 
217 	I915_WRITE(PP_OFF_DELAYS(0),
218 		   REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
219 		   REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
220 
221 	I915_WRITE(PP_DIVISOR(0),
222 		   REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
223 		   REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
224 				  DIV_ROUND_UP(pps->t4, 1000) + 1));
225 }
226 
227 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
228 				  const struct intel_crtc_state *pipe_config,
229 				  const struct drm_connector_state *conn_state)
230 {
231 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
232 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
233 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
234 	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
235 	int pipe = crtc->pipe;
236 	u32 temp;
237 
238 	if (HAS_PCH_SPLIT(dev_priv)) {
239 		assert_fdi_rx_pll_disabled(dev_priv, pipe);
240 		assert_shared_dpll_disabled(dev_priv,
241 					    pipe_config->shared_dpll);
242 	} else {
243 		assert_pll_disabled(dev_priv, pipe);
244 	}
245 
246 	intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
247 
248 	temp = lvds_encoder->init_lvds_val;
249 	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
250 
251 	if (HAS_PCH_CPT(dev_priv)) {
252 		temp &= ~LVDS_PIPE_SEL_MASK_CPT;
253 		temp |= LVDS_PIPE_SEL_CPT(pipe);
254 	} else {
255 		temp &= ~LVDS_PIPE_SEL_MASK;
256 		temp |= LVDS_PIPE_SEL(pipe);
257 	}
258 
259 	/* set the corresponsding LVDS_BORDER bit */
260 	temp &= ~LVDS_BORDER_ENABLE;
261 	temp |= pipe_config->gmch_pfit.lvds_border_bits;
262 
263 	/*
264 	 * Set the B0-B3 data pairs corresponding to whether we're going to
265 	 * set the DPLLs for dual-channel mode or not.
266 	 */
267 	if (lvds_encoder->is_dual_link)
268 		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
269 	else
270 		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
271 
272 	/*
273 	 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
274 	 * appropriately here, but we need to look more thoroughly into how
275 	 * panels behave in the two modes. For now, let's just maintain the
276 	 * value we got from the BIOS.
277 	 */
278 	temp &= ~LVDS_A3_POWER_MASK;
279 	temp |= lvds_encoder->a3_power;
280 
281 	/*
282 	 * Set the dithering flag on LVDS as needed, note that there is no
283 	 * special lvds dither control bit on pch-split platforms, dithering is
284 	 * only controlled through the PIPECONF reg.
285 	 */
286 	if (IS_GEN(dev_priv, 4)) {
287 		/*
288 		 * Bspec wording suggests that LVDS port dithering only exists
289 		 * for 18bpp panels.
290 		 */
291 		if (pipe_config->dither && pipe_config->pipe_bpp == 18)
292 			temp |= LVDS_ENABLE_DITHER;
293 		else
294 			temp &= ~LVDS_ENABLE_DITHER;
295 	}
296 	temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
297 	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
298 		temp |= LVDS_HSYNC_POLARITY;
299 	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
300 		temp |= LVDS_VSYNC_POLARITY;
301 
302 	I915_WRITE(lvds_encoder->reg, temp);
303 }
304 
305 /*
306  * Sets the power state for the panel.
307  */
308 static void intel_enable_lvds(struct intel_encoder *encoder,
309 			      const struct intel_crtc_state *pipe_config,
310 			      const struct drm_connector_state *conn_state)
311 {
312 	struct drm_device *dev = encoder->base.dev;
313 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
314 	struct drm_i915_private *dev_priv = to_i915(dev);
315 
316 	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
317 
318 	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
319 	POSTING_READ(lvds_encoder->reg);
320 
321 	if (intel_wait_for_register(&dev_priv->uncore,
322 				    PP_STATUS(0), PP_ON, PP_ON, 5000))
323 		DRM_ERROR("timed out waiting for panel to power on\n");
324 
325 	intel_panel_enable_backlight(pipe_config, conn_state);
326 }
327 
328 static void intel_disable_lvds(struct intel_encoder *encoder,
329 			       const struct intel_crtc_state *old_crtc_state,
330 			       const struct drm_connector_state *old_conn_state)
331 {
332 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
333 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
334 
335 	I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
336 	if (intel_wait_for_register(&dev_priv->uncore,
337 				    PP_STATUS(0), PP_ON, 0, 1000))
338 		DRM_ERROR("timed out waiting for panel to power off\n");
339 
340 	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
341 	POSTING_READ(lvds_encoder->reg);
342 }
343 
344 static void gmch_disable_lvds(struct intel_encoder *encoder,
345 			      const struct intel_crtc_state *old_crtc_state,
346 			      const struct drm_connector_state *old_conn_state)
347 
348 {
349 	intel_panel_disable_backlight(old_conn_state);
350 
351 	intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
352 }
353 
354 static void pch_disable_lvds(struct intel_encoder *encoder,
355 			     const struct intel_crtc_state *old_crtc_state,
356 			     const struct drm_connector_state *old_conn_state)
357 {
358 	intel_panel_disable_backlight(old_conn_state);
359 }
360 
361 static void pch_post_disable_lvds(struct intel_encoder *encoder,
362 				  const struct intel_crtc_state *old_crtc_state,
363 				  const struct drm_connector_state *old_conn_state)
364 {
365 	intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
366 }
367 
368 static enum drm_mode_status
369 intel_lvds_mode_valid(struct drm_connector *connector,
370 		      struct drm_display_mode *mode)
371 {
372 	struct intel_connector *intel_connector = to_intel_connector(connector);
373 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
374 	int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
375 
376 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
377 		return MODE_NO_DBLESCAN;
378 	if (mode->hdisplay > fixed_mode->hdisplay)
379 		return MODE_PANEL;
380 	if (mode->vdisplay > fixed_mode->vdisplay)
381 		return MODE_PANEL;
382 	if (fixed_mode->clock > max_pixclk)
383 		return MODE_CLOCK_HIGH;
384 
385 	return MODE_OK;
386 }
387 
388 static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
389 				     struct intel_crtc_state *pipe_config,
390 				     struct drm_connector_state *conn_state)
391 {
392 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
393 	struct intel_lvds_encoder *lvds_encoder =
394 		to_lvds_encoder(&intel_encoder->base);
395 	struct intel_connector *intel_connector =
396 		lvds_encoder->attached_connector;
397 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
398 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
399 	unsigned int lvds_bpp;
400 
401 	/* Should never happen!! */
402 	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
403 		DRM_ERROR("Can't support LVDS on pipe A\n");
404 		return -EINVAL;
405 	}
406 
407 	if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
408 		lvds_bpp = 8*3;
409 	else
410 		lvds_bpp = 6*3;
411 
412 	if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
413 		DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
414 			      pipe_config->pipe_bpp, lvds_bpp);
415 		pipe_config->pipe_bpp = lvds_bpp;
416 	}
417 
418 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
419 
420 	/*
421 	 * We have timings from the BIOS for the panel, put them in
422 	 * to the adjusted mode.  The CRTC will be set up for this mode,
423 	 * with the panel scaling set up to source from the H/VDisplay
424 	 * of the original mode.
425 	 */
426 	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
427 			       adjusted_mode);
428 
429 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
430 		return -EINVAL;
431 
432 	if (HAS_PCH_SPLIT(dev_priv)) {
433 		pipe_config->has_pch_encoder = true;
434 
435 		intel_pch_panel_fitting(intel_crtc, pipe_config,
436 					conn_state->scaling_mode);
437 	} else {
438 		intel_gmch_panel_fitting(intel_crtc, pipe_config,
439 					 conn_state->scaling_mode);
440 
441 	}
442 
443 	/*
444 	 * XXX: It would be nice to support lower refresh rates on the
445 	 * panels to reduce power consumption, and perhaps match the
446 	 * user's requested refresh rate.
447 	 */
448 
449 	return 0;
450 }
451 
452 static enum drm_connector_status
453 intel_lvds_detect(struct drm_connector *connector, bool force)
454 {
455 	return connector_status_connected;
456 }
457 
458 /*
459  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
460  */
461 static int intel_lvds_get_modes(struct drm_connector *connector)
462 {
463 	struct intel_connector *intel_connector = to_intel_connector(connector);
464 	struct drm_device *dev = connector->dev;
465 	struct drm_display_mode *mode;
466 
467 	/* use cached edid if we have one */
468 	if (!IS_ERR_OR_NULL(intel_connector->edid))
469 		return drm_add_edid_modes(connector, intel_connector->edid);
470 
471 	mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
472 	if (mode == NULL)
473 		return 0;
474 
475 	drm_mode_probed_add(connector, mode);
476 	return 1;
477 }
478 
479 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
480 	.get_modes = intel_lvds_get_modes,
481 	.mode_valid = intel_lvds_mode_valid,
482 	.atomic_check = intel_digital_connector_atomic_check,
483 };
484 
485 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
486 	.detect = intel_lvds_detect,
487 	.fill_modes = drm_helper_probe_single_connector_modes,
488 	.atomic_get_property = intel_digital_connector_atomic_get_property,
489 	.atomic_set_property = intel_digital_connector_atomic_set_property,
490 	.late_register = intel_connector_register,
491 	.early_unregister = intel_connector_unregister,
492 	.destroy = intel_connector_destroy,
493 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
494 	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
495 };
496 
497 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
498 	.destroy = intel_encoder_destroy,
499 };
500 
501 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
502 {
503 	DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
504 	return 1;
505 }
506 
507 /* These systems claim to have LVDS, but really don't */
508 static const struct dmi_system_id intel_no_lvds[] = {
509 	{
510 		.callback = intel_no_lvds_dmi_callback,
511 		.ident = "Apple Mac Mini (Core series)",
512 		.matches = {
513 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
514 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
515 		},
516 	},
517 	{
518 		.callback = intel_no_lvds_dmi_callback,
519 		.ident = "Apple Mac Mini (Core 2 series)",
520 		.matches = {
521 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
522 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
523 		},
524 	},
525 	{
526 		.callback = intel_no_lvds_dmi_callback,
527 		.ident = "MSI IM-945GSE-A",
528 		.matches = {
529 			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
530 			DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
531 		},
532 	},
533 	{
534 		.callback = intel_no_lvds_dmi_callback,
535 		.ident = "Dell Studio Hybrid",
536 		.matches = {
537 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
538 			DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
539 		},
540 	},
541 	{
542 		.callback = intel_no_lvds_dmi_callback,
543 		.ident = "Dell OptiPlex FX170",
544 		.matches = {
545 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
546 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
547 		},
548 	},
549 	{
550 		.callback = intel_no_lvds_dmi_callback,
551 		.ident = "AOpen Mini PC",
552 		.matches = {
553 			DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
554 			DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
555 		},
556 	},
557 	{
558 		.callback = intel_no_lvds_dmi_callback,
559 		.ident = "AOpen Mini PC MP915",
560 		.matches = {
561 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
562 			DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
563 		},
564 	},
565 	{
566 		.callback = intel_no_lvds_dmi_callback,
567 		.ident = "AOpen i915GMm-HFS",
568 		.matches = {
569 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
570 			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
571 		},
572 	},
573 	{
574 		.callback = intel_no_lvds_dmi_callback,
575                 .ident = "AOpen i45GMx-I",
576                 .matches = {
577                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
578                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
579                 },
580         },
581 	{
582 		.callback = intel_no_lvds_dmi_callback,
583 		.ident = "Aopen i945GTt-VFA",
584 		.matches = {
585 			DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
586 		},
587 	},
588 	{
589 		.callback = intel_no_lvds_dmi_callback,
590 		.ident = "Clientron U800",
591 		.matches = {
592 			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
593 			DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
594 		},
595 	},
596 	{
597                 .callback = intel_no_lvds_dmi_callback,
598                 .ident = "Clientron E830",
599                 .matches = {
600                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
601                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
602                 },
603         },
604         {
605 		.callback = intel_no_lvds_dmi_callback,
606 		.ident = "Asus EeeBox PC EB1007",
607 		.matches = {
608 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
609 			DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
610 		},
611 	},
612 	{
613 		.callback = intel_no_lvds_dmi_callback,
614 		.ident = "Asus AT5NM10T-I",
615 		.matches = {
616 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
617 			DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
618 		},
619 	},
620 	{
621 		.callback = intel_no_lvds_dmi_callback,
622 		.ident = "Hewlett-Packard HP t5740",
623 		.matches = {
624 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
625 			DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
626 		},
627 	},
628 	{
629 		.callback = intel_no_lvds_dmi_callback,
630 		.ident = "Hewlett-Packard t5745",
631 		.matches = {
632 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
633 			DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
634 		},
635 	},
636 	{
637 		.callback = intel_no_lvds_dmi_callback,
638 		.ident = "Hewlett-Packard st5747",
639 		.matches = {
640 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
641 			DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
642 		},
643 	},
644 	{
645 		.callback = intel_no_lvds_dmi_callback,
646 		.ident = "MSI Wind Box DC500",
647 		.matches = {
648 			DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
649 			DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
650 		},
651 	},
652 	{
653 		.callback = intel_no_lvds_dmi_callback,
654 		.ident = "Gigabyte GA-D525TUD",
655 		.matches = {
656 			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
657 			DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
658 		},
659 	},
660 	{
661 		.callback = intel_no_lvds_dmi_callback,
662 		.ident = "Supermicro X7SPA-H",
663 		.matches = {
664 			DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
665 			DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
666 		},
667 	},
668 	{
669 		.callback = intel_no_lvds_dmi_callback,
670 		.ident = "Fujitsu Esprimo Q900",
671 		.matches = {
672 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
673 			DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
674 		},
675 	},
676 	{
677 		.callback = intel_no_lvds_dmi_callback,
678 		.ident = "Intel D410PT",
679 		.matches = {
680 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
681 			DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
682 		},
683 	},
684 	{
685 		.callback = intel_no_lvds_dmi_callback,
686 		.ident = "Intel D425KT",
687 		.matches = {
688 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
689 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
690 		},
691 	},
692 	{
693 		.callback = intel_no_lvds_dmi_callback,
694 		.ident = "Intel D510MO",
695 		.matches = {
696 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
697 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
698 		},
699 	},
700 	{
701 		.callback = intel_no_lvds_dmi_callback,
702 		.ident = "Intel D525MW",
703 		.matches = {
704 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
705 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
706 		},
707 	},
708 	{
709 		.callback = intel_no_lvds_dmi_callback,
710 		.ident = "Radiant P845",
711 		.matches = {
712 			DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
713 			DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
714 		},
715 	},
716 
717 	{ }	/* terminating entry */
718 };
719 
720 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
721 {
722 	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
723 	return 1;
724 }
725 
726 static const struct dmi_system_id intel_dual_link_lvds[] = {
727 	{
728 		.callback = intel_dual_link_lvds_callback,
729 		.ident = "Apple MacBook Pro 15\" (2010)",
730 		.matches = {
731 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
732 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
733 		},
734 	},
735 	{
736 		.callback = intel_dual_link_lvds_callback,
737 		.ident = "Apple MacBook Pro 15\" (2011)",
738 		.matches = {
739 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
740 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
741 		},
742 	},
743 	{
744 		.callback = intel_dual_link_lvds_callback,
745 		.ident = "Apple MacBook Pro 15\" (2012)",
746 		.matches = {
747 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
748 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
749 		},
750 	},
751 	{ }	/* terminating entry */
752 };
753 
754 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
755 {
756 	struct intel_encoder *encoder;
757 
758 	for_each_intel_encoder(&dev_priv->drm, encoder) {
759 		if (encoder->type == INTEL_OUTPUT_LVDS)
760 			return encoder;
761 	}
762 
763 	return NULL;
764 }
765 
766 bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
767 {
768 	struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
769 
770 	return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
771 }
772 
773 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
774 {
775 	struct drm_device *dev = lvds_encoder->base.base.dev;
776 	unsigned int val;
777 	struct drm_i915_private *dev_priv = to_i915(dev);
778 
779 	/* use the module option value if specified */
780 	if (i915_modparams.lvds_channel_mode > 0)
781 		return i915_modparams.lvds_channel_mode == 2;
782 
783 	/* single channel LVDS is limited to 112 MHz */
784 	if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
785 		return true;
786 
787 	if (dmi_check_system(intel_dual_link_lvds))
788 		return true;
789 
790 	/*
791 	 * BIOS should set the proper LVDS register value at boot, but
792 	 * in reality, it doesn't set the value when the lid is closed;
793 	 * we need to check "the value to be set" in VBT when LVDS
794 	 * register is uninitialized.
795 	 */
796 	val = I915_READ(lvds_encoder->reg);
797 	if (HAS_PCH_CPT(dev_priv))
798 		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
799 	else
800 		val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
801 	if (val == 0)
802 		val = dev_priv->vbt.bios_lvds_val;
803 
804 	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
805 }
806 
807 /**
808  * intel_lvds_init - setup LVDS connectors on this device
809  * @dev_priv: i915 device
810  *
811  * Create the connector, register the LVDS DDC bus, and try to figure out what
812  * modes we can display on the LVDS panel (if present).
813  */
814 void intel_lvds_init(struct drm_i915_private *dev_priv)
815 {
816 	struct drm_device *dev = &dev_priv->drm;
817 	struct intel_lvds_encoder *lvds_encoder;
818 	struct intel_encoder *intel_encoder;
819 	struct intel_connector *intel_connector;
820 	struct drm_connector *connector;
821 	struct drm_encoder *encoder;
822 	struct drm_display_mode *fixed_mode = NULL;
823 	struct drm_display_mode *downclock_mode = NULL;
824 	struct edid *edid;
825 	i915_reg_t lvds_reg;
826 	u32 lvds;
827 	u8 pin;
828 	u32 allowed_scalers;
829 
830 	/* Skip init on machines we know falsely report LVDS */
831 	if (dmi_check_system(intel_no_lvds)) {
832 		WARN(!dev_priv->vbt.int_lvds_support,
833 		     "Useless DMI match. Internal LVDS support disabled by VBT\n");
834 		return;
835 	}
836 
837 	if (!dev_priv->vbt.int_lvds_support) {
838 		DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
839 		return;
840 	}
841 
842 	if (HAS_PCH_SPLIT(dev_priv))
843 		lvds_reg = PCH_LVDS;
844 	else
845 		lvds_reg = LVDS;
846 
847 	lvds = I915_READ(lvds_reg);
848 
849 	if (HAS_PCH_SPLIT(dev_priv)) {
850 		if ((lvds & LVDS_DETECTED) == 0)
851 			return;
852 	}
853 
854 	pin = GMBUS_PIN_PANEL;
855 	if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
856 		if ((lvds & LVDS_PORT_EN) == 0) {
857 			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
858 			return;
859 		}
860 		DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
861 	}
862 
863 	lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
864 	if (!lvds_encoder)
865 		return;
866 
867 	intel_connector = intel_connector_alloc();
868 	if (!intel_connector) {
869 		kfree(lvds_encoder);
870 		return;
871 	}
872 
873 	lvds_encoder->attached_connector = intel_connector;
874 
875 	intel_encoder = &lvds_encoder->base;
876 	encoder = &intel_encoder->base;
877 	connector = &intel_connector->base;
878 	drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
879 			   DRM_MODE_CONNECTOR_LVDS);
880 
881 	drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
882 			 DRM_MODE_ENCODER_LVDS, "LVDS");
883 
884 	intel_encoder->enable = intel_enable_lvds;
885 	intel_encoder->pre_enable = intel_pre_enable_lvds;
886 	intel_encoder->compute_config = intel_lvds_compute_config;
887 	if (HAS_PCH_SPLIT(dev_priv)) {
888 		intel_encoder->disable = pch_disable_lvds;
889 		intel_encoder->post_disable = pch_post_disable_lvds;
890 	} else {
891 		intel_encoder->disable = gmch_disable_lvds;
892 	}
893 	intel_encoder->get_hw_state = intel_lvds_get_hw_state;
894 	intel_encoder->get_config = intel_lvds_get_config;
895 	intel_encoder->update_pipe = intel_panel_update_backlight;
896 	intel_connector->get_hw_state = intel_connector_get_hw_state;
897 
898 	intel_connector_attach_encoder(intel_connector, intel_encoder);
899 
900 	intel_encoder->type = INTEL_OUTPUT_LVDS;
901 	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
902 	intel_encoder->port = PORT_NONE;
903 	intel_encoder->cloneable = 0;
904 	if (HAS_PCH_SPLIT(dev_priv))
905 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
906 	else if (IS_GEN(dev_priv, 4))
907 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
908 	else
909 		intel_encoder->crtc_mask = (1 << 1);
910 
911 	drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
912 	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
913 	connector->interlace_allowed = false;
914 	connector->doublescan_allowed = false;
915 
916 	lvds_encoder->reg = lvds_reg;
917 
918 	/* create the scaling mode property */
919 	allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
920 	allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
921 	allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
922 	drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
923 	connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
924 
925 	intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
926 	lvds_encoder->init_lvds_val = lvds;
927 
928 	/*
929 	 * LVDS discovery:
930 	 * 1) check for EDID on DDC
931 	 * 2) check for VBT data
932 	 * 3) check to see if LVDS is already on
933 	 *    if none of the above, no panel
934 	 */
935 
936 	/*
937 	 * Attempt to get the fixed panel mode from DDC.  Assume that the
938 	 * preferred mode is the right one.
939 	 */
940 	mutex_lock(&dev->mode_config.mutex);
941 	if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
942 		edid = drm_get_edid_switcheroo(connector,
943 				    intel_gmbus_get_adapter(dev_priv, pin));
944 	else
945 		edid = drm_get_edid(connector,
946 				    intel_gmbus_get_adapter(dev_priv, pin));
947 	if (edid) {
948 		if (drm_add_edid_modes(connector, edid)) {
949 			drm_connector_update_edid_property(connector,
950 								edid);
951 		} else {
952 			kfree(edid);
953 			edid = ERR_PTR(-EINVAL);
954 		}
955 	} else {
956 		edid = ERR_PTR(-ENOENT);
957 	}
958 	intel_connector->edid = edid;
959 
960 	fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
961 	if (fixed_mode)
962 		goto out;
963 
964 	/* Failed to get EDID, what about VBT? */
965 	fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
966 	if (fixed_mode)
967 		goto out;
968 
969 	/*
970 	 * If we didn't get EDID, try checking if the panel is already turned
971 	 * on.  If so, assume that whatever is currently programmed is the
972 	 * correct mode.
973 	 */
974 	fixed_mode = intel_encoder_current_mode(intel_encoder);
975 	if (fixed_mode) {
976 		DRM_DEBUG_KMS("using current (BIOS) mode: ");
977 		drm_mode_debug_printmodeline(fixed_mode);
978 		fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
979 	}
980 
981 	/* If we still don't have a mode after all that, give up. */
982 	if (!fixed_mode)
983 		goto failed;
984 
985 out:
986 	mutex_unlock(&dev->mode_config.mutex);
987 
988 	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
989 	intel_panel_setup_backlight(connector, INVALID_PIPE);
990 
991 	lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
992 	DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
993 		      lvds_encoder->is_dual_link ? "dual" : "single");
994 
995 	lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
996 
997 	return;
998 
999 failed:
1000 	mutex_unlock(&dev->mode_config.mutex);
1001 
1002 	DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1003 	drm_connector_cleanup(connector);
1004 	drm_encoder_cleanup(encoder);
1005 	kfree(lvds_encoder);
1006 	intel_connector_free(intel_connector);
1007 	return;
1008 }
1009