1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_ddi.h" 8 #include "intel_ddi_buf_trans.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 12 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 13 * them for both DP and FDI transports, allowing those ports to 14 * automatically adapt to HDMI connections as well 15 */ 16 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_dp[] = { 17 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, 18 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, 19 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } }, 20 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } }, 21 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, 22 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, 23 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } }, 24 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, 25 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } }, 26 }; 27 28 static const struct intel_ddi_buf_trans hsw_ddi_translations_dp = { 29 .entries = _hsw_ddi_translations_dp, 30 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_dp), 31 }; 32 33 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_fdi[] = { 34 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, 35 { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } }, 36 { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } }, 37 { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } }, 38 { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } }, 39 { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } }, 40 { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } }, 41 { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } }, 42 { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } }, 43 }; 44 45 static const struct intel_ddi_buf_trans hsw_ddi_translations_fdi = { 46 .entries = _hsw_ddi_translations_fdi, 47 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_fdi), 48 }; 49 50 static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { 51 /* Idx NT mV d T mV d db */ 52 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */ 53 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */ 54 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2: 400 600 3.5 */ 55 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3: 600 600 0 */ 56 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */ 57 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */ 58 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6: 800 800 0 */ 59 { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7: 800 1000 2 */ 60 { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8: 850 850 0 */ 61 { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9: 900 900 0 */ 62 { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10: 950 950 0 */ 63 { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */ 64 }; 65 66 static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { 67 .entries = _hsw_ddi_translations_hdmi, 68 .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), 69 .hdmi_default_entry = 6, 70 }; 71 72 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { 73 { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } }, 74 { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } }, 75 { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } }, 76 { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } }, 77 { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } }, 78 { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } }, 79 { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } }, 80 { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } }, 81 { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } }, 82 }; 83 84 static const struct intel_ddi_buf_trans bdw_ddi_translations_edp = { 85 .entries = _bdw_ddi_translations_edp, 86 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_edp), 87 }; 88 89 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_dp[] = { 90 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, 91 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, 92 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, 93 { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } }, 94 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, 95 { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } }, 96 { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } }, 97 { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } }, 98 { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } }, 99 }; 100 101 static const struct intel_ddi_buf_trans bdw_ddi_translations_dp = { 102 .entries = _bdw_ddi_translations_dp, 103 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_dp), 104 }; 105 106 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_fdi[] = { 107 { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } }, 108 { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } }, 109 { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } }, 110 { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } }, 111 { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } }, 112 { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } }, 113 { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } }, 114 { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } }, 115 { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } }, 116 }; 117 118 static const struct intel_ddi_buf_trans bdw_ddi_translations_fdi = { 119 .entries = _bdw_ddi_translations_fdi, 120 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_fdi), 121 }; 122 123 static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { 124 /* Idx NT mV d T mV df db */ 125 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */ 126 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */ 127 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2: 400 800 6 */ 128 { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3: 450 450 0 */ 129 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */ 130 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */ 131 { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6: 600 1000 4.5 */ 132 { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7: 800 800 0 */ 133 { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8: 800 1000 2 */ 134 { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */ 135 }; 136 137 static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { 138 .entries = _bdw_ddi_translations_hdmi, 139 .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), 140 .hdmi_default_entry = 7, 141 }; 142 143 /* Skylake H and S */ 144 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_dp[] = { 145 { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, 146 { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, 147 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 148 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 149 { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, 150 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 151 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 152 { .hsw = { 0x00002016, 0x000000DF, 0x0 } }, 153 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 154 }; 155 156 static const struct intel_ddi_buf_trans skl_ddi_translations_dp = { 157 .entries = _skl_ddi_translations_dp, 158 .num_entries = ARRAY_SIZE(_skl_ddi_translations_dp), 159 }; 160 161 /* Skylake U */ 162 static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_dp[] = { 163 { .hsw = { 0x0000201B, 0x000000A2, 0x0 } }, 164 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 165 { .hsw = { 0x80007011, 0x000000CD, 0x1 } }, 166 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 167 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, 168 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 169 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 170 { .hsw = { 0x00002016, 0x00000088, 0x0 } }, 171 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 172 }; 173 174 static const struct intel_ddi_buf_trans skl_u_ddi_translations_dp = { 175 .entries = _skl_u_ddi_translations_dp, 176 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_dp), 177 }; 178 179 /* Skylake Y */ 180 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_dp[] = { 181 { .hsw = { 0x00000018, 0x000000A2, 0x0 } }, 182 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 183 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 184 { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, 185 { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, 186 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 187 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 188 { .hsw = { 0x00000018, 0x00000088, 0x0 } }, 189 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 190 }; 191 192 static const struct intel_ddi_buf_trans skl_y_ddi_translations_dp = { 193 .entries = _skl_y_ddi_translations_dp, 194 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_dp), 195 }; 196 197 /* Kabylake H and S */ 198 static const union intel_ddi_buf_trans_entry _kbl_ddi_translations_dp[] = { 199 { .hsw = { 0x00002016, 0x000000A0, 0x0 } }, 200 { .hsw = { 0x00005012, 0x0000009B, 0x0 } }, 201 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 202 { .hsw = { 0x80009010, 0x000000C0, 0x1 } }, 203 { .hsw = { 0x00002016, 0x0000009B, 0x0 } }, 204 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 205 { .hsw = { 0x80007011, 0x000000C0, 0x1 } }, 206 { .hsw = { 0x00002016, 0x00000097, 0x0 } }, 207 { .hsw = { 0x80005012, 0x000000C0, 0x1 } }, 208 }; 209 210 static const struct intel_ddi_buf_trans kbl_ddi_translations_dp = { 211 .entries = _kbl_ddi_translations_dp, 212 .num_entries = ARRAY_SIZE(_kbl_ddi_translations_dp), 213 }; 214 215 /* Kabylake U */ 216 static const union intel_ddi_buf_trans_entry _kbl_u_ddi_translations_dp[] = { 217 { .hsw = { 0x0000201B, 0x000000A1, 0x0 } }, 218 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 219 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 220 { .hsw = { 0x80009010, 0x000000C0, 0x3 } }, 221 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } }, 222 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 223 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 224 { .hsw = { 0x00002016, 0x0000004F, 0x0 } }, 225 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 226 }; 227 228 static const struct intel_ddi_buf_trans kbl_u_ddi_translations_dp = { 229 .entries = _kbl_u_ddi_translations_dp, 230 .num_entries = ARRAY_SIZE(_kbl_u_ddi_translations_dp), 231 }; 232 233 /* Kabylake Y */ 234 static const union intel_ddi_buf_trans_entry _kbl_y_ddi_translations_dp[] = { 235 { .hsw = { 0x00001017, 0x000000A1, 0x0 } }, 236 { .hsw = { 0x00005012, 0x00000088, 0x0 } }, 237 { .hsw = { 0x80007011, 0x000000CD, 0x3 } }, 238 { .hsw = { 0x8000800F, 0x000000C0, 0x3 } }, 239 { .hsw = { 0x00001017, 0x0000009D, 0x0 } }, 240 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 241 { .hsw = { 0x80007011, 0x000000C0, 0x3 } }, 242 { .hsw = { 0x00001017, 0x0000004C, 0x0 } }, 243 { .hsw = { 0x80005012, 0x000000C0, 0x3 } }, 244 }; 245 246 static const struct intel_ddi_buf_trans kbl_y_ddi_translations_dp = { 247 .entries = _kbl_y_ddi_translations_dp, 248 .num_entries = ARRAY_SIZE(_kbl_y_ddi_translations_dp), 249 }; 250 251 /* 252 * Skylake/Kabylake H and S 253 * eDP 1.4 low vswing translation parameters 254 */ 255 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_edp[] = { 256 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 257 { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, 258 { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, 259 { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, 260 { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, 261 { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, 262 { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, 263 { .hsw = { 0x00000018, 0x000000AB, 0x0 } }, 264 { .hsw = { 0x00007013, 0x0000009F, 0x0 } }, 265 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 266 }; 267 268 static const struct intel_ddi_buf_trans skl_ddi_translations_edp = { 269 .entries = _skl_ddi_translations_edp, 270 .num_entries = ARRAY_SIZE(_skl_ddi_translations_edp), 271 }; 272 273 /* 274 * Skylake/Kabylake U 275 * eDP 1.4 low vswing translation parameters 276 */ 277 static const union intel_ddi_buf_trans_entry _skl_u_ddi_translations_edp[] = { 278 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 279 { .hsw = { 0x00004013, 0x000000A9, 0x0 } }, 280 { .hsw = { 0x00007011, 0x000000A2, 0x0 } }, 281 { .hsw = { 0x00009010, 0x0000009C, 0x0 } }, 282 { .hsw = { 0x00000018, 0x000000A9, 0x0 } }, 283 { .hsw = { 0x00006013, 0x000000A2, 0x0 } }, 284 { .hsw = { 0x00007011, 0x000000A6, 0x0 } }, 285 { .hsw = { 0x00002016, 0x000000AB, 0x0 } }, 286 { .hsw = { 0x00005013, 0x0000009F, 0x0 } }, 287 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 288 }; 289 290 static const struct intel_ddi_buf_trans skl_u_ddi_translations_edp = { 291 .entries = _skl_u_ddi_translations_edp, 292 .num_entries = ARRAY_SIZE(_skl_u_ddi_translations_edp), 293 }; 294 295 /* 296 * Skylake/Kabylake Y 297 * eDP 1.4 low vswing translation parameters 298 */ 299 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_edp[] = { 300 { .hsw = { 0x00000018, 0x000000A8, 0x0 } }, 301 { .hsw = { 0x00004013, 0x000000AB, 0x0 } }, 302 { .hsw = { 0x00007011, 0x000000A4, 0x0 } }, 303 { .hsw = { 0x00009010, 0x000000DF, 0x0 } }, 304 { .hsw = { 0x00000018, 0x000000AA, 0x0 } }, 305 { .hsw = { 0x00006013, 0x000000A4, 0x0 } }, 306 { .hsw = { 0x00007011, 0x0000009D, 0x0 } }, 307 { .hsw = { 0x00000018, 0x000000A0, 0x0 } }, 308 { .hsw = { 0x00006012, 0x000000DF, 0x0 } }, 309 { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, 310 }; 311 312 static const struct intel_ddi_buf_trans skl_y_ddi_translations_edp = { 313 .entries = _skl_y_ddi_translations_edp, 314 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_edp), 315 }; 316 317 /* Skylake/Kabylake U, H and S */ 318 static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { 319 { .hsw = { 0x00000018, 0x000000AC, 0x0 } }, 320 { .hsw = { 0x00005012, 0x0000009D, 0x0 } }, 321 { .hsw = { 0x00007011, 0x00000088, 0x0 } }, 322 { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, 323 { .hsw = { 0x00000018, 0x00000098, 0x0 } }, 324 { .hsw = { 0x00004013, 0x00000088, 0x0 } }, 325 { .hsw = { 0x80006012, 0x000000CD, 0x1 } }, 326 { .hsw = { 0x00000018, 0x000000DF, 0x0 } }, 327 { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */ 328 { .hsw = { 0x80003015, 0x000000C0, 0x1 } }, 329 { .hsw = { 0x80000018, 0x000000C0, 0x1 } }, 330 }; 331 332 static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { 333 .entries = _skl_ddi_translations_hdmi, 334 .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), 335 .hdmi_default_entry = 8, 336 }; 337 338 /* Skylake/Kabylake Y */ 339 static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { 340 { .hsw = { 0x00000018, 0x000000A1, 0x0 } }, 341 { .hsw = { 0x00005012, 0x000000DF, 0x0 } }, 342 { .hsw = { 0x80007011, 0x000000CB, 0x3 } }, 343 { .hsw = { 0x00000018, 0x000000A4, 0x0 } }, 344 { .hsw = { 0x00000018, 0x0000009D, 0x0 } }, 345 { .hsw = { 0x00004013, 0x00000080, 0x0 } }, 346 { .hsw = { 0x80006013, 0x000000C0, 0x3 } }, 347 { .hsw = { 0x00000018, 0x0000008A, 0x0 } }, 348 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */ 349 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, 350 { .hsw = { 0x80000018, 0x000000C0, 0x3 } }, 351 }; 352 353 static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { 354 .entries = _skl_y_ddi_translations_hdmi, 355 .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), 356 .hdmi_default_entry = 8, 357 }; 358 359 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { 360 /* Idx NT mV diff db */ 361 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ 362 { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ 363 { .bxt = { 104, 0x9A, 0, 64, } }, /* 2: 400 6 */ 364 { .bxt = { 154, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ 365 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ 366 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ 367 { .bxt = { 154, 0x9A, 0, 64, } }, /* 6: 600 6 */ 368 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ 369 { .bxt = { 154, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ 370 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ 371 }; 372 373 static const struct intel_ddi_buf_trans bxt_ddi_translations_dp = { 374 .entries = _bxt_ddi_translations_dp, 375 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_dp), 376 }; 377 378 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_edp[] = { 379 /* Idx NT mV diff db */ 380 { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */ 381 { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */ 382 { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */ 383 { .bxt = { 54, 0, 0, 69, } }, /* 3: 200 6 */ 384 { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */ 385 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */ 386 { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */ 387 { .bxt = { 43, 0, 0, 128, } }, /* 7: 300 0 */ 388 { .bxt = { 54, 0, 0, 101, } }, /* 8: 300 1.5 */ 389 { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */ 390 }; 391 392 static const struct intel_ddi_buf_trans bxt_ddi_translations_edp = { 393 .entries = _bxt_ddi_translations_edp, 394 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_edp), 395 }; 396 397 /* BSpec has 2 recommended values - entries 0 and 8. 398 * Using the entry with higher vswing. 399 */ 400 static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { 401 /* Idx NT mV diff db */ 402 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */ 403 { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */ 404 { .bxt = { 52, 0x9A, 0, 64, } }, /* 2: 400 6 */ 405 { .bxt = { 42, 0x9A, 0, 43, } }, /* 3: 400 9.5 */ 406 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */ 407 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */ 408 { .bxt = { 77, 0x9A, 0, 64, } }, /* 6: 600 6 */ 409 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */ 410 { .bxt = { 102, 0x9A, 0, 85, } }, /* 8: 800 3.5 */ 411 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */ 412 }; 413 414 static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { 415 .entries = _bxt_ddi_translations_hdmi, 416 .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), 417 .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, 418 }; 419 420 /* Voltage Swing Programming for VccIO 0.85V for DP */ 421 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_85V[] = { 422 /* NT mV Trans mV db */ 423 { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 424 { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ 425 { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ 426 { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ 427 { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 428 { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 429 { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 430 { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */ 431 { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ 432 { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 433 }; 434 435 static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_85V = { 436 .entries = _cnl_ddi_translations_dp_0_85V, 437 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_85V), 438 }; 439 440 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 441 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] = { 442 /* NT mV Trans mV db */ 443 { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ 444 { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ 445 { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */ 446 { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 */ 447 { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */ 448 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */ 449 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 450 }; 451 452 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = { 453 .entries = _cnl_ddi_translations_hdmi_0_85V, 454 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V), 455 .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1, 456 }; 457 458 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 459 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_85V[] = { 460 /* NT mV Trans mV db */ 461 { .cnl = { 0xA, 0x66, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ 462 { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ 463 { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ 464 { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ 465 { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ 466 { .cnl = { 0xA, 0x66, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ 467 { .cnl = { 0xB, 0x70, 0x3C, 0x00, 0x03 } }, /* 460 600 2.3 */ 468 { .cnl = { 0xC, 0x75, 0x3C, 0x00, 0x03 } }, /* 537 700 2.3 */ 469 { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 470 }; 471 472 static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_85V = { 473 .entries = _cnl_ddi_translations_edp_0_85V, 474 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_85V), 475 }; 476 477 /* Voltage Swing Programming for VccIO 0.95V for DP */ 478 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_0_95V[] = { 479 /* NT mV Trans mV db */ 480 { .cnl = { 0xA, 0x5D, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 481 { .cnl = { 0xA, 0x6A, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ 482 { .cnl = { 0xB, 0x7A, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ 483 { .cnl = { 0x6, 0x7C, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ 484 { .cnl = { 0xA, 0x69, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 485 { .cnl = { 0xB, 0x7A, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 486 { .cnl = { 0x6, 0x7C, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 487 { .cnl = { 0xB, 0x7D, 0x3C, 0x00, 0x03 } }, /* 650 725 0.9 */ 488 { .cnl = { 0x6, 0x7C, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ 489 { .cnl = { 0x6, 0x7B, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 490 }; 491 492 static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_0_95V = { 493 .entries = _cnl_ddi_translations_dp_0_95V, 494 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_0_95V), 495 }; 496 497 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 498 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] = { 499 /* NT mV Trans mV db */ 500 { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 501 { .cnl = { 0xB, 0x69, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ 502 { .cnl = { 0x5, 0x76, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ 503 { .cnl = { 0xA, 0x5E, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ 504 { .cnl = { 0xB, 0x69, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ 505 { .cnl = { 0xB, 0x79, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 506 { .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */ 507 { .cnl = { 0x5, 0x76, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */ 508 { .cnl = { 0x6, 0x7D, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */ 509 { .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */ 510 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ 511 }; 512 513 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = { 514 .entries = _cnl_ddi_translations_hdmi_0_95V, 515 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V), 516 .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1, 517 }; 518 519 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 520 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_0_95V[] = { 521 /* NT mV Trans mV db */ 522 { .cnl = { 0xA, 0x61, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ 523 { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ 524 { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ 525 { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ 526 { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ 527 { .cnl = { 0xA, 0x61, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ 528 { .cnl = { 0xB, 0x68, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */ 529 { .cnl = { 0xC, 0x6E, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */ 530 { .cnl = { 0x4, 0x7F, 0x3A, 0x00, 0x05 } }, /* 460 600 2.3 */ 531 { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 532 }; 533 534 static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_0_95V = { 535 .entries = _cnl_ddi_translations_edp_0_95V, 536 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_0_95V), 537 }; 538 539 /* Voltage Swing Programming for VccIO 1.05V for DP */ 540 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_dp_1_05V[] = { 541 /* NT mV Trans mV db */ 542 { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 543 { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ 544 { .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ 545 { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 400 1050 8.4 */ 546 { .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ 547 { .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 548 { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 550 1050 5.6 */ 549 { .cnl = { 0x5, 0x76, 0x3E, 0x00, 0x01 } }, /* 850 900 0.5 */ 550 { .cnl = { 0x6, 0x7F, 0x36, 0x00, 0x09 } }, /* 750 1050 2.9 */ 551 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ 552 }; 553 554 static const struct intel_ddi_buf_trans cnl_ddi_translations_dp_1_05V = { 555 .entries = _cnl_ddi_translations_dp_1_05V, 556 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_dp_1_05V), 557 }; 558 559 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 560 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] = { 561 /* NT mV Trans mV db */ 562 { .cnl = { 0xA, 0x58, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 563 { .cnl = { 0xB, 0x64, 0x37, 0x00, 0x08 } }, /* 400 600 3.5 */ 564 { .cnl = { 0x5, 0x70, 0x31, 0x00, 0x0E } }, /* 400 800 6.0 */ 565 { .cnl = { 0xA, 0x5B, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ 566 { .cnl = { 0xB, 0x64, 0x3F, 0x00, 0x00 } }, /* 600 600 0.0 */ 567 { .cnl = { 0x5, 0x73, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 568 { .cnl = { 0x6, 0x7C, 0x32, 0x00, 0x0D } }, /* 600 1000 4.4 */ 569 { .cnl = { 0x5, 0x70, 0x3F, 0x00, 0x00 } }, /* 800 800 0.0 */ 570 { .cnl = { 0x6, 0x7C, 0x39, 0x00, 0x06 } }, /* 800 1000 1.9 */ 571 { .cnl = { 0x6, 0x7F, 0x39, 0x00, 0x06 } }, /* 850 1050 1.8 */ 572 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1050 1050 0.0 */ 573 }; 574 575 static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = { 576 .entries = _cnl_ddi_translations_hdmi_1_05V, 577 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V), 578 .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1, 579 }; 580 581 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 582 static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_edp_1_05V[] = { 583 /* NT mV Trans mV db */ 584 { .cnl = { 0xA, 0x5E, 0x3A, 0x00, 0x05 } }, /* 384 500 2.3 */ 585 { .cnl = { 0x0, 0x7F, 0x38, 0x00, 0x07 } }, /* 153 200 2.3 */ 586 { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 192 250 2.3 */ 587 { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 230 300 2.3 */ 588 { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 269 350 2.3 */ 589 { .cnl = { 0xA, 0x5E, 0x3C, 0x00, 0x03 } }, /* 446 500 1.0 */ 590 { .cnl = { 0xB, 0x64, 0x39, 0x00, 0x06 } }, /* 460 600 2.3 */ 591 { .cnl = { 0xE, 0x6A, 0x39, 0x00, 0x06 } }, /* 537 700 2.3 */ 592 { .cnl = { 0x2, 0x7F, 0x3F, 0x00, 0x00 } }, /* 400 400 0.0 */ 593 }; 594 595 static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = { 596 .entries = _cnl_ddi_translations_edp_1_05V, 597 .num_entries = ARRAY_SIZE(_cnl_ddi_translations_edp_1_05V), 598 }; 599 600 /* icl_combo_phy_ddi_translations */ 601 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = { 602 /* NT mV Trans mV db */ 603 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 604 { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 605 { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 606 { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 607 { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 608 { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 609 { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 610 { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 611 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 612 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 613 }; 614 615 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = { 616 .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 617 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3), 618 }; 619 620 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = { 621 /* NT mV Trans mV db */ 622 { .cnl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 623 { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ 624 { .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ 625 { .cnl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */ 626 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 627 { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 628 { .cnl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ 629 { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 630 { .cnl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 631 { .cnl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 632 }; 633 634 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2 = { 635 .entries = _icl_combo_phy_ddi_translations_edp_hbr2, 636 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2), 637 }; 638 639 static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = { 640 /* NT mV Trans mV db */ 641 { .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */ 642 { .cnl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */ 643 { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */ 644 { .cnl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */ 645 { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */ 646 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */ 647 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */ 648 }; 649 650 static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { 651 .entries = _icl_combo_phy_ddi_translations_hdmi, 652 .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), 653 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, 654 }; 655 656 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { 657 /* NT mV Trans mV db */ 658 { .cnl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 659 { .cnl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ 660 { .cnl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */ 661 { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */ 662 { .cnl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 663 { .cnl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ 664 { .cnl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 665 { .cnl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 666 { .cnl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */ 667 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 668 }; 669 670 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_dp = { 671 .entries = _ehl_combo_phy_ddi_translations_dp, 672 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_dp), 673 }; 674 675 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_edp_hbr2[] = { 676 /* NT mV Trans mV db */ 677 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 678 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ 679 { .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ 680 { .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */ 681 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 682 { .cnl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */ 683 { .cnl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */ 684 { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 685 { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 686 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 687 }; 688 689 static const struct intel_ddi_buf_trans ehl_combo_phy_ddi_translations_edp_hbr2 = { 690 .entries = _ehl_combo_phy_ddi_translations_edp_hbr2, 691 .num_entries = ARRAY_SIZE(_ehl_combo_phy_ddi_translations_edp_hbr2), 692 }; 693 694 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr[] = { 695 /* NT mV Trans mV db */ 696 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 697 { .cnl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */ 698 { .cnl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */ 699 { .cnl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */ 700 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 701 { .cnl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 702 { .cnl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */ 703 { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 704 { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 705 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 706 }; 707 708 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr = { 709 .entries = _jsl_combo_phy_ddi_translations_edp_hbr, 710 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr), 711 }; 712 713 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_ddi_translations_edp_hbr2[] = { 714 /* NT mV Trans mV db */ 715 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */ 716 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */ 717 { .cnl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */ 718 { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */ 719 { .cnl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */ 720 { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */ 721 { .cnl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */ 722 { .cnl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */ 723 { .cnl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 724 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 725 }; 726 727 static const struct intel_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2 = { 728 .entries = _jsl_combo_phy_ddi_translations_edp_hbr2, 729 .num_entries = ARRAY_SIZE(_jsl_combo_phy_ddi_translations_edp_hbr2), 730 }; 731 732 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { 733 /* NT mV Trans mV db */ 734 { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 735 { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ 736 { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 737 { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 738 { .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 739 { .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 740 { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 741 { .cnl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 742 { .cnl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */ 743 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 744 }; 745 746 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr = { 747 .entries = _dg1_combo_phy_ddi_translations_dp_rbr_hbr, 748 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_rbr_hbr), 749 }; 750 751 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 752 /* NT mV Trans mV db */ 753 { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 754 { .cnl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */ 755 { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 756 { .cnl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */ 757 { .cnl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 758 { .cnl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 759 { .cnl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */ 760 { .cnl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 761 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 762 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 763 }; 764 765 static const struct intel_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 766 .entries = _dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, 767 .num_entries = ARRAY_SIZE(_dg1_combo_phy_ddi_translations_dp_hbr2_hbr3), 768 }; 769 770 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_rbr_hbr[] = { 771 /* Voltage swing pre-emphasis */ 772 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ 773 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ 774 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ 775 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ 776 { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */ 777 { .mg = { 0x2B, 0x00, 0x08 } }, /* 1 1 */ 778 { .mg = { 0x30, 0x00, 0x0F } }, /* 1 2 */ 779 { .mg = { 0x31, 0x00, 0x03 } }, /* 2 0 */ 780 { .mg = { 0x34, 0x00, 0x0B } }, /* 2 1 */ 781 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ 782 }; 783 784 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr = { 785 .entries = _icl_mg_phy_ddi_translations_rbr_hbr, 786 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_rbr_hbr), 787 }; 788 789 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 790 /* Voltage swing pre-emphasis */ 791 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */ 792 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */ 793 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */ 794 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */ 795 { .mg = { 0x26, 0x00, 0x00 } }, /* 1 0 */ 796 { .mg = { 0x2C, 0x00, 0x07 } }, /* 1 1 */ 797 { .mg = { 0x33, 0x00, 0x0C } }, /* 1 2 */ 798 { .mg = { 0x2E, 0x00, 0x00 } }, /* 2 0 */ 799 { .mg = { 0x36, 0x00, 0x09 } }, /* 2 1 */ 800 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */ 801 }; 802 803 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3 = { 804 .entries = _icl_mg_phy_ddi_translations_hbr2_hbr3, 805 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hbr2_hbr3), 806 }; 807 808 static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] = { 809 /* HDMI Preset VS Pre-emph */ 810 { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */ 811 { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */ 812 { .mg = { 0x29, 0x0, 0x0 } }, /* 3 650mV 0dB */ 813 { .mg = { 0x32, 0x0, 0x0 } }, /* 4 800mV 0dB */ 814 { .mg = { 0x3F, 0x0, 0x0 } }, /* 5 1000mV 0dB */ 815 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ 816 { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ 817 { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */ 818 { .mg = { 0x37, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ 819 { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */ 820 }; 821 822 static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { 823 .entries = _icl_mg_phy_ddi_translations_hdmi, 824 .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), 825 .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, 826 }; 827 828 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { 829 /* VS pre-emp Non-trans mV Pre-emph dB */ 830 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 831 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ 832 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 833 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */ 834 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 835 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 836 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 837 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 838 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 839 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ 840 }; 841 842 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr = { 843 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr, 844 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr), 845 }; 846 847 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr2[] = { 848 /* VS pre-emp Non-trans mV Pre-emph dB */ 849 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 850 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */ 851 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 852 { .dkl = { 0x0, 0x0, 0x19 } }, /* 0 3 400mV 9.5 dB */ 853 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 854 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 855 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 856 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 857 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 858 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */ 859 }; 860 861 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_dp_hbr2 = { 862 .entries = _tgl_dkl_phy_ddi_translations_dp_hbr2, 863 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_dp_hbr2), 864 }; 865 866 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[] = { 867 /* HDMI Preset VS Pre-emph */ 868 { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */ 869 { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */ 870 { .dkl = { 0x4, 0x0, 0x0 } }, /* 3 650mV 0dB */ 871 { .dkl = { 0x2, 0x0, 0x0 } }, /* 4 800mV 0dB */ 872 { .dkl = { 0x0, 0x0, 0x0 } }, /* 5 1000mV 0dB */ 873 { .dkl = { 0x0, 0x0, 0x5 } }, /* 6 Full -1.5 dB */ 874 { .dkl = { 0x0, 0x0, 0x6 } }, /* 7 Full -1.8 dB */ 875 { .dkl = { 0x0, 0x0, 0x7 } }, /* 8 Full -2 dB */ 876 { .dkl = { 0x0, 0x0, 0x8 } }, /* 9 Full -2.5 dB */ 877 { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */ 878 }; 879 880 static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { 881 .entries = _tgl_dkl_phy_ddi_translations_hdmi, 882 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), 883 .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, 884 }; 885 886 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { 887 /* NT mV Trans mV db */ 888 { .cnl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 889 { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 890 { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 891 { .cnl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 892 { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 893 { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 894 { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 895 { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 896 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 897 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 898 }; 899 900 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr = { 901 .entries = _tgl_combo_phy_ddi_translations_dp_hbr, 902 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr), 903 }; 904 905 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr2[] = { 906 /* NT mV Trans mV db */ 907 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 908 { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 909 { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 910 { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 911 { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 912 { .cnl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 913 { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 914 { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 915 { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 916 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 917 }; 918 919 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2 = { 920 .entries = _tgl_combo_phy_ddi_translations_dp_hbr2, 921 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_dp_hbr2), 922 }; 923 924 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 925 /* NT mV Trans mV db */ 926 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 927 { .cnl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */ 928 { .cnl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */ 929 { .cnl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */ 930 { .cnl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 931 { .cnl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */ 932 { .cnl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */ 933 { .cnl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 934 { .cnl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */ 935 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 936 }; 937 938 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2 = { 939 .entries = _tgl_uy_combo_phy_ddi_translations_dp_hbr2, 940 .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_ddi_translations_dp_hbr2), 941 }; 942 943 /* 944 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 945 * that DisplayPort specification requires 946 */ 947 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 948 /* VS pre-emp */ 949 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */ 950 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */ 951 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */ 952 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */ 953 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */ 954 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */ 955 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */ 956 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */ 957 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */ 958 }; 959 960 static const struct intel_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl = { 961 .entries = _tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 962 .num_entries = ARRAY_SIZE(_tgl_combo_phy_ddi_translations_edp_hbr2_hobl), 963 }; 964 965 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr[] = { 966 /* NT mV Trans mV db */ 967 { .cnl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 968 { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 969 { .cnl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */ 970 { .cnl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */ 971 { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 972 { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 973 { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 974 { .cnl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */ 975 { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 976 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 977 }; 978 979 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr = { 980 .entries = _rkl_combo_phy_ddi_translations_dp_hbr, 981 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr), 982 }; 983 984 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 985 /* NT mV Trans mV db */ 986 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 987 { .cnl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */ 988 { .cnl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */ 989 { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ 990 { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 991 { .cnl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */ 992 { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */ 993 { .cnl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 994 { .cnl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */ 995 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 996 }; 997 998 static const struct intel_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 999 .entries = _rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, 1000 .num_entries = ARRAY_SIZE(_rkl_combo_phy_ddi_translations_dp_hbr2_hbr3), 1001 }; 1002 1003 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 1004 /* NT mV Trans mV db */ 1005 { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */ 1006 { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */ 1007 { .cnl = { 0xC, 0x63, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */ 1008 { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */ 1009 { .cnl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 1010 { .cnl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */ 1011 { .cnl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 500 900 5.1 */ 1012 { .cnl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */ 1013 { .cnl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */ 1014 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 1015 }; 1016 1017 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_dp_hbr2_hbr3 = { 1018 .entries = _adls_combo_phy_ddi_translations_dp_hbr2_hbr3, 1019 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_dp_hbr2_hbr3), 1020 }; 1021 1022 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr2[] = { 1023 /* NT mV Trans mV db */ 1024 { .cnl = { 0x9, 0x70, 0x3C, 0x00, 0x03 } }, /* 200 200 0.0 */ 1025 { .cnl = { 0x9, 0x6D, 0x3A, 0x00, 0x05 } }, /* 200 250 1.9 */ 1026 { .cnl = { 0x9, 0x7F, 0x36, 0x00, 0x09 } }, /* 200 300 3.5 */ 1027 { .cnl = { 0x4, 0x59, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */ 1028 { .cnl = { 0x2, 0x77, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */ 1029 { .cnl = { 0x2, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */ 1030 { .cnl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */ 1031 { .cnl = { 0x4, 0x5E, 0x3D, 0x00, 0x04 } }, /* 300 300 0.0 */ 1032 { .cnl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */ 1033 { .cnl = { 0x4, 0x6F, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */ 1034 }; 1035 1036 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr2 = { 1037 .entries = _adls_combo_phy_ddi_translations_edp_hbr2, 1038 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr2), 1039 }; 1040 1041 static const union intel_ddi_buf_trans_entry _adls_combo_phy_ddi_translations_edp_hbr3[] = { 1042 /* NT mV Trans mV db */ 1043 { .cnl = { 0xA, 0x5E, 0x34, 0x00, 0x0B } }, /* 350 350 0.0 */ 1044 { .cnl = { 0xA, 0x69, 0x32, 0x00, 0x0D } }, /* 350 500 3.1 */ 1045 { .cnl = { 0xC, 0x74, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */ 1046 { .cnl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */ 1047 { .cnl = { 0xA, 0x5C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */ 1048 { .cnl = { 0xC, 0x7F, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */ 1049 { .cnl = { 0x6, 0x7F, 0x33, 0x00, 0x0C } }, /* 500 900 5.1 */ 1050 { .cnl = { 0xC, 0x7F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */ 1051 { .cnl = { 0x6, 0x7F, 0x3C, 0x00, 0x03 } }, /* 600 900 3.5 */ 1052 { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */ 1053 }; 1054 1055 static const struct intel_ddi_buf_trans adls_combo_phy_ddi_translations_edp_hbr3 = { 1056 .entries = _adls_combo_phy_ddi_translations_edp_hbr3, 1057 .num_entries = ARRAY_SIZE(_adls_combo_phy_ddi_translations_edp_hbr3), 1058 }; 1059 1060 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr[] = { 1061 /* VS pre-emp Non-trans mV Pre-emph dB */ 1062 { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */ 1063 { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */ 1064 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */ 1065 { .dkl = { 0x0, 0x0, 0x17 } }, /* 0 3 400mV 9.5 dB */ 1066 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 1067 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */ 1068 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 1069 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 1070 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */ 1071 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ 1072 }; 1073 1074 static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr = { 1075 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr, 1076 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr), 1077 }; 1078 1079 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3[] = { 1080 /* VS pre-emp Non-trans mV Pre-emph dB */ 1081 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */ 1082 { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */ 1083 { .dkl = { 0x2, 0x0, 0x0A } }, /* 0 2 400mV 6 dB */ 1084 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */ 1085 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */ 1086 { .dkl = { 0x2, 0x0, 0x06 } }, /* 1 1 600mV 3.5 dB */ 1087 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */ 1088 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */ 1089 { .dkl = { 0x0, 0x0, 0x09 } }, /* 2 1 800mV 3.5 dB */ 1090 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */ 1091 }; 1092 1093 static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3 = { 1094 .entries = _adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, 1095 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3), 1096 }; 1097 1098 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table) 1099 { 1100 return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1101 } 1102 1103 static const struct intel_ddi_buf_trans * 1104 intel_get_buf_trans(const struct intel_ddi_buf_trans *ddi_translations, int *num_entries) 1105 { 1106 *num_entries = ddi_translations->num_entries; 1107 return ddi_translations; 1108 } 1109 1110 static const struct intel_ddi_buf_trans * 1111 hsw_get_buf_trans(struct intel_encoder *encoder, 1112 const struct intel_crtc_state *crtc_state, 1113 int *n_entries) 1114 { 1115 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1116 return intel_get_buf_trans(&hsw_ddi_translations_fdi, n_entries); 1117 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1118 return intel_get_buf_trans(&hsw_ddi_translations_hdmi, n_entries); 1119 else 1120 return intel_get_buf_trans(&hsw_ddi_translations_dp, n_entries); 1121 } 1122 1123 static const struct intel_ddi_buf_trans * 1124 bdw_get_buf_trans(struct intel_encoder *encoder, 1125 const struct intel_crtc_state *crtc_state, 1126 int *n_entries) 1127 { 1128 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1129 1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1131 return intel_get_buf_trans(&bdw_ddi_translations_fdi, n_entries); 1132 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1133 return intel_get_buf_trans(&bdw_ddi_translations_hdmi, n_entries); 1134 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1135 i915->vbt.edp.low_vswing) 1136 return intel_get_buf_trans(&bdw_ddi_translations_edp, n_entries); 1137 else 1138 return intel_get_buf_trans(&bdw_ddi_translations_dp, n_entries); 1139 } 1140 1141 static int skl_buf_trans_num_entries(enum port port, int n_entries) 1142 { 1143 /* Only DDIA and DDIE can select the 10th register with DP */ 1144 if (port == PORT_A || port == PORT_E) 1145 return min(n_entries, 10); 1146 else 1147 return min(n_entries, 9); 1148 } 1149 1150 static const struct intel_ddi_buf_trans * 1151 _skl_get_buf_trans_dp(struct intel_encoder *encoder, 1152 const struct intel_ddi_buf_trans *ddi_translations, 1153 int *n_entries) 1154 { 1155 ddi_translations = intel_get_buf_trans(ddi_translations, n_entries); 1156 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 1157 return ddi_translations; 1158 } 1159 1160 static const struct intel_ddi_buf_trans * 1161 skl_y_get_buf_trans(struct intel_encoder *encoder, 1162 const struct intel_crtc_state *crtc_state, 1163 int *n_entries) 1164 { 1165 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1166 1167 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1168 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); 1169 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1170 i915->vbt.edp.low_vswing) 1171 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); 1172 else 1173 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_dp, n_entries); 1174 } 1175 1176 static const struct intel_ddi_buf_trans * 1177 skl_u_get_buf_trans(struct intel_encoder *encoder, 1178 const struct intel_crtc_state *crtc_state, 1179 int *n_entries) 1180 { 1181 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1182 1183 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1184 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1185 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1186 i915->vbt.edp.low_vswing) 1187 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); 1188 else 1189 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_dp, n_entries); 1190 } 1191 1192 static const struct intel_ddi_buf_trans * 1193 skl_get_buf_trans(struct intel_encoder *encoder, 1194 const struct intel_crtc_state *crtc_state, 1195 int *n_entries) 1196 { 1197 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1198 1199 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1200 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1201 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1202 i915->vbt.edp.low_vswing) 1203 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); 1204 else 1205 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_dp, n_entries); 1206 } 1207 1208 static const struct intel_ddi_buf_trans * 1209 kbl_y_get_buf_trans(struct intel_encoder *encoder, 1210 const struct intel_crtc_state *crtc_state, 1211 int *n_entries) 1212 { 1213 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1214 1215 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1216 return intel_get_buf_trans(&skl_y_ddi_translations_hdmi, n_entries); 1217 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1218 i915->vbt.edp.low_vswing) 1219 return _skl_get_buf_trans_dp(encoder, &skl_y_ddi_translations_edp, n_entries); 1220 else 1221 return _skl_get_buf_trans_dp(encoder, &kbl_y_ddi_translations_dp, n_entries); 1222 } 1223 1224 static const struct intel_ddi_buf_trans * 1225 kbl_u_get_buf_trans(struct intel_encoder *encoder, 1226 const struct intel_crtc_state *crtc_state, 1227 int *n_entries) 1228 { 1229 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1230 1231 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1232 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1233 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1234 i915->vbt.edp.low_vswing) 1235 return _skl_get_buf_trans_dp(encoder, &skl_u_ddi_translations_edp, n_entries); 1236 else 1237 return _skl_get_buf_trans_dp(encoder, &kbl_u_ddi_translations_dp, n_entries); 1238 } 1239 1240 static const struct intel_ddi_buf_trans * 1241 kbl_get_buf_trans(struct intel_encoder *encoder, 1242 const struct intel_crtc_state *crtc_state, 1243 int *n_entries) 1244 { 1245 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1246 1247 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1248 return intel_get_buf_trans(&skl_ddi_translations_hdmi, n_entries); 1249 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1250 i915->vbt.edp.low_vswing) 1251 return _skl_get_buf_trans_dp(encoder, &skl_ddi_translations_edp, n_entries); 1252 else 1253 return _skl_get_buf_trans_dp(encoder, &kbl_ddi_translations_dp, n_entries); 1254 } 1255 1256 static const struct intel_ddi_buf_trans * 1257 bxt_get_buf_trans(struct intel_encoder *encoder, 1258 const struct intel_crtc_state *crtc_state, 1259 int *n_entries) 1260 { 1261 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1262 1263 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1264 return intel_get_buf_trans(&bxt_ddi_translations_hdmi, n_entries); 1265 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1266 i915->vbt.edp.low_vswing) 1267 return intel_get_buf_trans(&bxt_ddi_translations_edp, n_entries); 1268 else 1269 return intel_get_buf_trans(&bxt_ddi_translations_dp, n_entries); 1270 } 1271 1272 static const struct intel_ddi_buf_trans * 1273 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 1274 { 1275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1276 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1277 1278 if (voltage == VOLTAGE_INFO_0_85V) { 1279 return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_85V, 1280 n_entries); 1281 } else if (voltage == VOLTAGE_INFO_0_95V) { 1282 return intel_get_buf_trans(&cnl_ddi_translations_hdmi_0_95V, 1283 n_entries); 1284 } else if (voltage == VOLTAGE_INFO_1_05V) { 1285 return intel_get_buf_trans(&cnl_ddi_translations_hdmi_1_05V, 1286 n_entries); 1287 } else { 1288 *n_entries = 1; /* shut up gcc */ 1289 MISSING_CASE(voltage); 1290 } 1291 return NULL; 1292 } 1293 1294 static const struct intel_ddi_buf_trans * 1295 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 1296 { 1297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1298 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1299 1300 if (voltage == VOLTAGE_INFO_0_85V) { 1301 return intel_get_buf_trans(&cnl_ddi_translations_dp_0_85V, 1302 n_entries); 1303 } else if (voltage == VOLTAGE_INFO_0_95V) { 1304 return intel_get_buf_trans(&cnl_ddi_translations_dp_0_95V, 1305 n_entries); 1306 } else if (voltage == VOLTAGE_INFO_1_05V) { 1307 return intel_get_buf_trans(&cnl_ddi_translations_dp_1_05V, 1308 n_entries); 1309 } else { 1310 *n_entries = 1; /* shut up gcc */ 1311 MISSING_CASE(voltage); 1312 } 1313 return NULL; 1314 } 1315 1316 static const struct intel_ddi_buf_trans * 1317 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1318 { 1319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1320 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1321 1322 if (dev_priv->vbt.edp.low_vswing) { 1323 if (voltage == VOLTAGE_INFO_0_85V) { 1324 return intel_get_buf_trans(&cnl_ddi_translations_edp_0_85V, 1325 n_entries); 1326 } else if (voltage == VOLTAGE_INFO_0_95V) { 1327 return intel_get_buf_trans(&cnl_ddi_translations_edp_0_95V, 1328 n_entries); 1329 } else if (voltage == VOLTAGE_INFO_1_05V) { 1330 return intel_get_buf_trans(&cnl_ddi_translations_edp_1_05V, 1331 n_entries); 1332 } else { 1333 *n_entries = 1; /* shut up gcc */ 1334 MISSING_CASE(voltage); 1335 } 1336 return NULL; 1337 } else { 1338 return cnl_get_buf_trans_dp(encoder, n_entries); 1339 } 1340 } 1341 1342 static const struct intel_ddi_buf_trans * 1343 cnl_get_buf_trans(struct intel_encoder *encoder, 1344 const struct intel_crtc_state *crtc_state, 1345 int *n_entries) 1346 { 1347 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1348 return cnl_get_buf_trans_hdmi(encoder, n_entries); 1349 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1350 return cnl_get_buf_trans_edp(encoder, n_entries); 1351 return cnl_get_buf_trans_dp(encoder, n_entries); 1352 } 1353 1354 static const struct intel_ddi_buf_trans * 1355 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1356 const struct intel_crtc_state *crtc_state, 1357 int *n_entries) 1358 { 1359 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1360 n_entries); 1361 } 1362 1363 static const struct intel_ddi_buf_trans * 1364 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1365 const struct intel_crtc_state *crtc_state, 1366 int *n_entries) 1367 { 1368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1369 1370 if (crtc_state->port_clock > 540000) { 1371 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1372 n_entries); 1373 } else if (dev_priv->vbt.edp.low_vswing) { 1374 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1375 n_entries); 1376 } 1377 1378 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1379 } 1380 1381 static const struct intel_ddi_buf_trans * 1382 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1383 const struct intel_crtc_state *crtc_state, 1384 int *n_entries) 1385 { 1386 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1387 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1388 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1389 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1390 else 1391 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1392 } 1393 1394 static const struct intel_ddi_buf_trans * 1395 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1396 const struct intel_crtc_state *crtc_state, 1397 int *n_entries) 1398 { 1399 if (crtc_state->port_clock > 270000) { 1400 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hbr2_hbr3, 1401 n_entries); 1402 } else { 1403 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_rbr_hbr, 1404 n_entries); 1405 } 1406 } 1407 1408 static const struct intel_ddi_buf_trans * 1409 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1410 const struct intel_crtc_state *crtc_state, 1411 int *n_entries) 1412 { 1413 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1414 return intel_get_buf_trans(&icl_mg_phy_ddi_translations_hdmi, n_entries); 1415 else 1416 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1417 } 1418 1419 static const struct intel_ddi_buf_trans * 1420 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1421 const struct intel_crtc_state *crtc_state, 1422 int *n_entries) 1423 { 1424 if (crtc_state->port_clock > 270000) 1425 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1426 else 1427 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1428 } 1429 1430 static const struct intel_ddi_buf_trans * 1431 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1432 const struct intel_crtc_state *crtc_state, 1433 int *n_entries) 1434 { 1435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1436 1437 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1438 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1439 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1440 dev_priv->vbt.edp.low_vswing) 1441 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1442 else 1443 return intel_get_buf_trans(&ehl_combo_phy_ddi_translations_dp, n_entries); 1444 } 1445 1446 static const struct intel_ddi_buf_trans * 1447 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1448 const struct intel_crtc_state *crtc_state, 1449 int *n_entries) 1450 { 1451 if (crtc_state->port_clock > 270000) 1452 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr2, n_entries); 1453 else 1454 return intel_get_buf_trans(&jsl_combo_phy_ddi_translations_edp_hbr, n_entries); 1455 } 1456 1457 static const struct intel_ddi_buf_trans * 1458 jsl_get_combo_buf_trans(struct intel_encoder *encoder, 1459 const struct intel_crtc_state *crtc_state, 1460 int *n_entries) 1461 { 1462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1463 1464 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1465 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1466 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 1467 dev_priv->vbt.edp.low_vswing) 1468 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1469 else 1470 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, n_entries); 1471 } 1472 1473 static const struct intel_ddi_buf_trans * 1474 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1475 const struct intel_crtc_state *crtc_state, 1476 int *n_entries) 1477 { 1478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1479 1480 if (crtc_state->port_clock > 270000) { 1481 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1482 return intel_get_buf_trans(&tgl_uy_combo_phy_ddi_translations_dp_hbr2, 1483 n_entries); 1484 } else { 1485 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr2, 1486 n_entries); 1487 } 1488 } else { 1489 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, 1490 n_entries); 1491 } 1492 } 1493 1494 static const struct intel_ddi_buf_trans * 1495 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1496 const struct intel_crtc_state *crtc_state, 1497 int *n_entries) 1498 { 1499 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1500 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1501 1502 if (crtc_state->port_clock > 540000) { 1503 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1504 n_entries); 1505 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1506 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1507 n_entries); 1508 } else if (dev_priv->vbt.edp.low_vswing) { 1509 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1510 n_entries); 1511 } 1512 1513 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1514 } 1515 1516 static const struct intel_ddi_buf_trans * 1517 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1518 const struct intel_crtc_state *crtc_state, 1519 int *n_entries) 1520 { 1521 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1522 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1523 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1524 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1525 else 1526 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1527 } 1528 1529 static const struct intel_ddi_buf_trans * 1530 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1531 const struct intel_crtc_state *crtc_state, 1532 int *n_entries) 1533 { 1534 if (crtc_state->port_clock > 270000) 1535 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_hbr2_hbr3, 1536 n_entries); 1537 else 1538 return intel_get_buf_trans(&dg1_combo_phy_ddi_translations_dp_rbr_hbr, 1539 n_entries); 1540 } 1541 1542 static const struct intel_ddi_buf_trans * 1543 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1544 const struct intel_crtc_state *crtc_state, 1545 int *n_entries) 1546 { 1547 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1548 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1549 1550 if (crtc_state->port_clock > 540000) 1551 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1552 n_entries); 1553 else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) 1554 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1555 n_entries); 1556 else if (dev_priv->vbt.edp.low_vswing) 1557 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1558 n_entries); 1559 else 1560 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1561 } 1562 1563 static const struct intel_ddi_buf_trans * 1564 dg1_get_combo_buf_trans(struct intel_encoder *encoder, 1565 const struct intel_crtc_state *crtc_state, 1566 int *n_entries) 1567 { 1568 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1569 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1570 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1571 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1572 else 1573 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1574 } 1575 1576 static const struct intel_ddi_buf_trans * 1577 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1578 const struct intel_crtc_state *crtc_state, 1579 int *n_entries) 1580 { 1581 if (crtc_state->port_clock > 270000) 1582 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); 1583 else 1584 return intel_get_buf_trans(&rkl_combo_phy_ddi_translations_dp_hbr, n_entries); 1585 } 1586 1587 static const struct intel_ddi_buf_trans * 1588 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1589 const struct intel_crtc_state *crtc_state, 1590 int *n_entries) 1591 { 1592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1594 1595 if (crtc_state->port_clock > 540000) { 1596 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3, 1597 n_entries); 1598 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1599 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, 1600 n_entries); 1601 } else if (dev_priv->vbt.edp.low_vswing) { 1602 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2, 1603 n_entries); 1604 } 1605 1606 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1607 } 1608 1609 static const struct intel_ddi_buf_trans * 1610 rkl_get_combo_buf_trans(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state, 1612 int *n_entries) 1613 { 1614 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1615 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1616 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1617 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1618 else 1619 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1620 } 1621 1622 static const struct intel_ddi_buf_trans * 1623 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1624 const struct intel_crtc_state *crtc_state, 1625 int *n_entries) 1626 { 1627 if (crtc_state->port_clock > 270000) 1628 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_dp_hbr2_hbr3, n_entries); 1629 else 1630 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_dp_hbr, n_entries); 1631 } 1632 1633 static const struct intel_ddi_buf_trans * 1634 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1635 const struct intel_crtc_state *crtc_state, 1636 int *n_entries) 1637 { 1638 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1639 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1640 1641 if (crtc_state->port_clock > 540000) 1642 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr3, n_entries); 1643 else if (i915->vbt.edp.hobl && !intel_dp->hobl_failed) 1644 return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl, n_entries); 1645 else if (i915->vbt.edp.low_vswing) 1646 return intel_get_buf_trans(&adls_combo_phy_ddi_translations_edp_hbr2, n_entries); 1647 else 1648 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1649 } 1650 1651 static const struct intel_ddi_buf_trans * 1652 adls_get_combo_buf_trans(struct intel_encoder *encoder, 1653 const struct intel_crtc_state *crtc_state, 1654 int *n_entries) 1655 { 1656 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1657 return intel_get_buf_trans(&icl_combo_phy_ddi_translations_hdmi, n_entries); 1658 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1659 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1660 else 1661 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1662 } 1663 1664 static const struct intel_ddi_buf_trans * 1665 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1666 const struct intel_crtc_state *crtc_state, 1667 int *n_entries) 1668 { 1669 if (crtc_state->port_clock > 270000) { 1670 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr2, 1671 n_entries); 1672 } else { 1673 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_dp_hbr, 1674 n_entries); 1675 } 1676 } 1677 1678 static const struct intel_ddi_buf_trans * 1679 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1680 const struct intel_crtc_state *crtc_state, 1681 int *n_entries) 1682 { 1683 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1684 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); 1685 else 1686 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1687 } 1688 1689 static const struct intel_ddi_buf_trans * 1690 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1691 const struct intel_crtc_state *crtc_state, 1692 int *n_entries) 1693 { 1694 if (crtc_state->port_clock > 270000) { 1695 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3, 1696 n_entries); 1697 } else { 1698 return intel_get_buf_trans(&adlp_dkl_phy_ddi_translations_dp_hbr, 1699 n_entries); 1700 } 1701 } 1702 1703 static const struct intel_ddi_buf_trans * 1704 adlp_get_dkl_buf_trans(struct intel_encoder *encoder, 1705 const struct intel_crtc_state *crtc_state, 1706 int *n_entries) 1707 { 1708 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1709 return intel_get_buf_trans(&tgl_dkl_phy_ddi_translations_hdmi, n_entries); 1710 else 1711 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1712 } 1713 1714 int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, 1715 const struct intel_crtc_state *crtc_state, 1716 int *default_entry) 1717 { 1718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1719 const struct intel_ddi_buf_trans *ddi_translations; 1720 int n_entries; 1721 1722 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1723 1724 if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { 1725 *default_entry = 0; 1726 return 0; 1727 } 1728 1729 *default_entry = ddi_translations->hdmi_default_entry; 1730 1731 return n_entries; 1732 } 1733 1734 void intel_ddi_buf_trans_init(struct intel_encoder *encoder) 1735 { 1736 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1737 enum phy phy = intel_port_to_phy(i915, encoder->port); 1738 1739 if (IS_ALDERLAKE_P(i915)) { 1740 if (intel_phy_is_combo(i915, phy)) 1741 encoder->get_buf_trans = tgl_get_combo_buf_trans; 1742 else 1743 encoder->get_buf_trans = adlp_get_dkl_buf_trans; 1744 } else if (IS_ALDERLAKE_S(i915)) { 1745 encoder->get_buf_trans = adls_get_combo_buf_trans; 1746 } else if (IS_ROCKETLAKE(i915)) { 1747 encoder->get_buf_trans = rkl_get_combo_buf_trans; 1748 } else if (IS_DG1(i915)) { 1749 encoder->get_buf_trans = dg1_get_combo_buf_trans; 1750 } else if (DISPLAY_VER(i915) >= 12) { 1751 if (intel_phy_is_combo(i915, phy)) 1752 encoder->get_buf_trans = tgl_get_combo_buf_trans; 1753 else 1754 encoder->get_buf_trans = tgl_get_dkl_buf_trans; 1755 } else if (DISPLAY_VER(i915) == 11) { 1756 if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) 1757 encoder->get_buf_trans = jsl_get_combo_buf_trans; 1758 else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) 1759 encoder->get_buf_trans = ehl_get_combo_buf_trans; 1760 else if (intel_phy_is_combo(i915, phy)) 1761 encoder->get_buf_trans = icl_get_combo_buf_trans; 1762 else 1763 encoder->get_buf_trans = icl_get_mg_buf_trans; 1764 } else if (IS_CANNONLAKE(i915)) { 1765 encoder->get_buf_trans = cnl_get_buf_trans; 1766 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1767 encoder->get_buf_trans = bxt_get_buf_trans; 1768 } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) { 1769 encoder->get_buf_trans = kbl_y_get_buf_trans; 1770 } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) { 1771 encoder->get_buf_trans = kbl_u_get_buf_trans; 1772 } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { 1773 encoder->get_buf_trans = kbl_get_buf_trans; 1774 } else if (IS_SKL_ULX(i915)) { 1775 encoder->get_buf_trans = skl_y_get_buf_trans; 1776 } else if (IS_SKL_ULT(i915)) { 1777 encoder->get_buf_trans = skl_u_get_buf_trans; 1778 } else if (IS_SKYLAKE(i915)) { 1779 encoder->get_buf_trans = skl_get_buf_trans; 1780 } else if (IS_BROADWELL(i915)) { 1781 encoder->get_buf_trans = bdw_get_buf_trans; 1782 } else { 1783 encoder->get_buf_trans = hsw_get_buf_trans; 1784 } 1785 } 1786