1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "intel_ddi.h"
8 #include "intel_ddi_buf_trans.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11 #include "intel_dp.h"
12 
13 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
14  * them for both DP and FDI transports, allowing those ports to
15  * automatically adapt to HDMI connections as well
16  */
17 static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = {
18 	{ .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
19 	{ .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
20 	{ .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
21 	{ .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
22 	{ .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
23 	{ .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
24 	{ .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
25 	{ .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
26 	{ .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
27 };
28 
29 static const struct intel_ddi_buf_trans hsw_trans_dp = {
30 	.entries = _hsw_trans_dp,
31 	.num_entries = ARRAY_SIZE(_hsw_trans_dp),
32 };
33 
34 static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = {
35 	{ .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
36 	{ .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
37 	{ .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
38 	{ .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
39 	{ .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
40 	{ .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
41 	{ .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
42 	{ .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
43 	{ .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
44 };
45 
46 static const struct intel_ddi_buf_trans hsw_trans_fdi = {
47 	.entries = _hsw_trans_fdi,
48 	.num_entries = ARRAY_SIZE(_hsw_trans_fdi),
49 };
50 
51 static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = {
52 							/* Idx	NT mV d	T mV d	db	*/
53 	{ .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },	/* 0:	400	400	0	*/
54 	{ .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } },	/* 1:	400	500	2	*/
55 	{ .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },	/* 2:	400	600	3.5	*/
56 	{ .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },	/* 3:	600	600	0	*/
57 	{ .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } },	/* 4:	600	750	2	*/
58 	{ .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },	/* 5:	600	900	3.5	*/
59 	{ .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },	/* 6:	800	800	0	*/
60 	{ .hsw = { 0x80E79FFF, 0x00030002, 0x0 } },	/* 7:	800	1000	2	*/
61 	{ .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } },	/* 8:	850	850	0	*/
62 	{ .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } },	/* 9:	900	900	0	*/
63 	{ .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } },	/* 10:	950	950	0	*/
64 	{ .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } },	/* 11:	1000	1000	0	*/
65 };
66 
67 static const struct intel_ddi_buf_trans hsw_trans_hdmi = {
68 	.entries = _hsw_trans_hdmi,
69 	.num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
70 	.hdmi_default_entry = 6,
71 };
72 
73 static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = {
74 	{ .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
75 	{ .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
76 	{ .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
77 	{ .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
78 	{ .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
79 	{ .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
80 	{ .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
81 	{ .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
82 	{ .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
83 };
84 
85 static const struct intel_ddi_buf_trans bdw_trans_edp = {
86 	.entries = _bdw_trans_edp,
87 	.num_entries = ARRAY_SIZE(_bdw_trans_edp),
88 };
89 
90 static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = {
91 	{ .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
92 	{ .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
93 	{ .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
94 	{ .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
95 	{ .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
96 	{ .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
97 	{ .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
98 	{ .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
99 	{ .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
100 };
101 
102 static const struct intel_ddi_buf_trans bdw_trans_dp = {
103 	.entries = _bdw_trans_dp,
104 	.num_entries = ARRAY_SIZE(_bdw_trans_dp),
105 };
106 
107 static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = {
108 	{ .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
109 	{ .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
110 	{ .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
111 	{ .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
112 	{ .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
113 	{ .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
114 	{ .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
115 	{ .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
116 	{ .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
117 };
118 
119 static const struct intel_ddi_buf_trans bdw_trans_fdi = {
120 	.entries = _bdw_trans_fdi,
121 	.num_entries = ARRAY_SIZE(_bdw_trans_fdi),
122 };
123 
124 static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = {
125 							/* Idx	NT mV d	T mV df	db	*/
126 	{ .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },	/* 0:	400	400	0	*/
127 	{ .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },	/* 1:	400	600	3.5	*/
128 	{ .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },	/* 2:	400	800	6	*/
129 	{ .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } },	/* 3:	450	450	0	*/
130 	{ .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },	/* 4:	600	600	0	*/
131 	{ .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } },	/* 5:	600	800	2.5	*/
132 	{ .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } },	/* 6:	600	1000	4.5	*/
133 	{ .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } },	/* 7:	800	800	0	*/
134 	{ .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } },	/* 8:	800	1000	2	*/
135 	{ .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } },	/* 9:	1000	1000	0	*/
136 };
137 
138 static const struct intel_ddi_buf_trans bdw_trans_hdmi = {
139 	.entries = _bdw_trans_hdmi,
140 	.num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
141 	.hdmi_default_entry = 7,
142 };
143 
144 /* Skylake H and S */
145 static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = {
146 	{ .hsw = { 0x00002016, 0x000000A0, 0x0 } },
147 	{ .hsw = { 0x00005012, 0x0000009B, 0x0 } },
148 	{ .hsw = { 0x00007011, 0x00000088, 0x0 } },
149 	{ .hsw = { 0x80009010, 0x000000C0, 0x1 } },
150 	{ .hsw = { 0x00002016, 0x0000009B, 0x0 } },
151 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
152 	{ .hsw = { 0x80007011, 0x000000C0, 0x1 } },
153 	{ .hsw = { 0x00002016, 0x000000DF, 0x0 } },
154 	{ .hsw = { 0x80005012, 0x000000C0, 0x1 } },
155 };
156 
157 static const struct intel_ddi_buf_trans skl_trans_dp = {
158 	.entries = _skl_trans_dp,
159 	.num_entries = ARRAY_SIZE(_skl_trans_dp),
160 };
161 
162 /* Skylake U */
163 static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = {
164 	{ .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
165 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
166 	{ .hsw = { 0x80007011, 0x000000CD, 0x1 } },
167 	{ .hsw = { 0x80009010, 0x000000C0, 0x1 } },
168 	{ .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
169 	{ .hsw = { 0x80005012, 0x000000C0, 0x1 } },
170 	{ .hsw = { 0x80007011, 0x000000C0, 0x1 } },
171 	{ .hsw = { 0x00002016, 0x00000088, 0x0 } },
172 	{ .hsw = { 0x80005012, 0x000000C0, 0x1 } },
173 };
174 
175 static const struct intel_ddi_buf_trans skl_u_trans_dp = {
176 	.entries = _skl_u_trans_dp,
177 	.num_entries = ARRAY_SIZE(_skl_u_trans_dp),
178 };
179 
180 /* Skylake Y */
181 static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = {
182 	{ .hsw = { 0x00000018, 0x000000A2, 0x0 } },
183 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
184 	{ .hsw = { 0x80007011, 0x000000CD, 0x3 } },
185 	{ .hsw = { 0x80009010, 0x000000C0, 0x3 } },
186 	{ .hsw = { 0x00000018, 0x0000009D, 0x0 } },
187 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
188 	{ .hsw = { 0x80007011, 0x000000C0, 0x3 } },
189 	{ .hsw = { 0x00000018, 0x00000088, 0x0 } },
190 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
191 };
192 
193 static const struct intel_ddi_buf_trans skl_y_trans_dp = {
194 	.entries = _skl_y_trans_dp,
195 	.num_entries = ARRAY_SIZE(_skl_y_trans_dp),
196 };
197 
198 /* Kabylake H and S */
199 static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = {
200 	{ .hsw = { 0x00002016, 0x000000A0, 0x0 } },
201 	{ .hsw = { 0x00005012, 0x0000009B, 0x0 } },
202 	{ .hsw = { 0x00007011, 0x00000088, 0x0 } },
203 	{ .hsw = { 0x80009010, 0x000000C0, 0x1 } },
204 	{ .hsw = { 0x00002016, 0x0000009B, 0x0 } },
205 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
206 	{ .hsw = { 0x80007011, 0x000000C0, 0x1 } },
207 	{ .hsw = { 0x00002016, 0x00000097, 0x0 } },
208 	{ .hsw = { 0x80005012, 0x000000C0, 0x1 } },
209 };
210 
211 static const struct intel_ddi_buf_trans kbl_trans_dp = {
212 	.entries = _kbl_trans_dp,
213 	.num_entries = ARRAY_SIZE(_kbl_trans_dp),
214 };
215 
216 /* Kabylake U */
217 static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = {
218 	{ .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
219 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
220 	{ .hsw = { 0x80007011, 0x000000CD, 0x3 } },
221 	{ .hsw = { 0x80009010, 0x000000C0, 0x3 } },
222 	{ .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
223 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
224 	{ .hsw = { 0x80007011, 0x000000C0, 0x3 } },
225 	{ .hsw = { 0x00002016, 0x0000004F, 0x0 } },
226 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
227 };
228 
229 static const struct intel_ddi_buf_trans kbl_u_trans_dp = {
230 	.entries = _kbl_u_trans_dp,
231 	.num_entries = ARRAY_SIZE(_kbl_u_trans_dp),
232 };
233 
234 /* Kabylake Y */
235 static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = {
236 	{ .hsw = { 0x00001017, 0x000000A1, 0x0 } },
237 	{ .hsw = { 0x00005012, 0x00000088, 0x0 } },
238 	{ .hsw = { 0x80007011, 0x000000CD, 0x3 } },
239 	{ .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
240 	{ .hsw = { 0x00001017, 0x0000009D, 0x0 } },
241 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
242 	{ .hsw = { 0x80007011, 0x000000C0, 0x3 } },
243 	{ .hsw = { 0x00001017, 0x0000004C, 0x0 } },
244 	{ .hsw = { 0x80005012, 0x000000C0, 0x3 } },
245 };
246 
247 static const struct intel_ddi_buf_trans kbl_y_trans_dp = {
248 	.entries = _kbl_y_trans_dp,
249 	.num_entries = ARRAY_SIZE(_kbl_y_trans_dp),
250 };
251 
252 /*
253  * Skylake/Kabylake H and S
254  * eDP 1.4 low vswing translation parameters
255  */
256 static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = {
257 	{ .hsw = { 0x00000018, 0x000000A8, 0x0 } },
258 	{ .hsw = { 0x00004013, 0x000000A9, 0x0 } },
259 	{ .hsw = { 0x00007011, 0x000000A2, 0x0 } },
260 	{ .hsw = { 0x00009010, 0x0000009C, 0x0 } },
261 	{ .hsw = { 0x00000018, 0x000000A9, 0x0 } },
262 	{ .hsw = { 0x00006013, 0x000000A2, 0x0 } },
263 	{ .hsw = { 0x00007011, 0x000000A6, 0x0 } },
264 	{ .hsw = { 0x00000018, 0x000000AB, 0x0 } },
265 	{ .hsw = { 0x00007013, 0x0000009F, 0x0 } },
266 	{ .hsw = { 0x00000018, 0x000000DF, 0x0 } },
267 };
268 
269 static const struct intel_ddi_buf_trans skl_trans_edp = {
270 	.entries = _skl_trans_edp,
271 	.num_entries = ARRAY_SIZE(_skl_trans_edp),
272 };
273 
274 /*
275  * Skylake/Kabylake U
276  * eDP 1.4 low vswing translation parameters
277  */
278 static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = {
279 	{ .hsw = { 0x00000018, 0x000000A8, 0x0 } },
280 	{ .hsw = { 0x00004013, 0x000000A9, 0x0 } },
281 	{ .hsw = { 0x00007011, 0x000000A2, 0x0 } },
282 	{ .hsw = { 0x00009010, 0x0000009C, 0x0 } },
283 	{ .hsw = { 0x00000018, 0x000000A9, 0x0 } },
284 	{ .hsw = { 0x00006013, 0x000000A2, 0x0 } },
285 	{ .hsw = { 0x00007011, 0x000000A6, 0x0 } },
286 	{ .hsw = { 0x00002016, 0x000000AB, 0x0 } },
287 	{ .hsw = { 0x00005013, 0x0000009F, 0x0 } },
288 	{ .hsw = { 0x00000018, 0x000000DF, 0x0 } },
289 };
290 
291 static const struct intel_ddi_buf_trans skl_u_trans_edp = {
292 	.entries = _skl_u_trans_edp,
293 	.num_entries = ARRAY_SIZE(_skl_u_trans_edp),
294 };
295 
296 /*
297  * Skylake/Kabylake Y
298  * eDP 1.4 low vswing translation parameters
299  */
300 static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = {
301 	{ .hsw = { 0x00000018, 0x000000A8, 0x0 } },
302 	{ .hsw = { 0x00004013, 0x000000AB, 0x0 } },
303 	{ .hsw = { 0x00007011, 0x000000A4, 0x0 } },
304 	{ .hsw = { 0x00009010, 0x000000DF, 0x0 } },
305 	{ .hsw = { 0x00000018, 0x000000AA, 0x0 } },
306 	{ .hsw = { 0x00006013, 0x000000A4, 0x0 } },
307 	{ .hsw = { 0x00007011, 0x0000009D, 0x0 } },
308 	{ .hsw = { 0x00000018, 0x000000A0, 0x0 } },
309 	{ .hsw = { 0x00006012, 0x000000DF, 0x0 } },
310 	{ .hsw = { 0x00000018, 0x0000008A, 0x0 } },
311 };
312 
313 static const struct intel_ddi_buf_trans skl_y_trans_edp = {
314 	.entries = _skl_y_trans_edp,
315 	.num_entries = ARRAY_SIZE(_skl_y_trans_edp),
316 };
317 
318 /* Skylake/Kabylake U, H and S */
319 static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = {
320 	{ .hsw = { 0x00000018, 0x000000AC, 0x0 } },
321 	{ .hsw = { 0x00005012, 0x0000009D, 0x0 } },
322 	{ .hsw = { 0x00007011, 0x00000088, 0x0 } },
323 	{ .hsw = { 0x00000018, 0x000000A1, 0x0 } },
324 	{ .hsw = { 0x00000018, 0x00000098, 0x0 } },
325 	{ .hsw = { 0x00004013, 0x00000088, 0x0 } },
326 	{ .hsw = { 0x80006012, 0x000000CD, 0x1 } },
327 	{ .hsw = { 0x00000018, 0x000000DF, 0x0 } },
328 	{ .hsw = { 0x80003015, 0x000000CD, 0x1 } },	/* Default */
329 	{ .hsw = { 0x80003015, 0x000000C0, 0x1 } },
330 	{ .hsw = { 0x80000018, 0x000000C0, 0x1 } },
331 };
332 
333 static const struct intel_ddi_buf_trans skl_trans_hdmi = {
334 	.entries = _skl_trans_hdmi,
335 	.num_entries = ARRAY_SIZE(_skl_trans_hdmi),
336 	.hdmi_default_entry = 8,
337 };
338 
339 /* Skylake/Kabylake Y */
340 static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = {
341 	{ .hsw = { 0x00000018, 0x000000A1, 0x0 } },
342 	{ .hsw = { 0x00005012, 0x000000DF, 0x0 } },
343 	{ .hsw = { 0x80007011, 0x000000CB, 0x3 } },
344 	{ .hsw = { 0x00000018, 0x000000A4, 0x0 } },
345 	{ .hsw = { 0x00000018, 0x0000009D, 0x0 } },
346 	{ .hsw = { 0x00004013, 0x00000080, 0x0 } },
347 	{ .hsw = { 0x80006013, 0x000000C0, 0x3 } },
348 	{ .hsw = { 0x00000018, 0x0000008A, 0x0 } },
349 	{ .hsw = { 0x80003015, 0x000000C0, 0x3 } },	/* Default */
350 	{ .hsw = { 0x80003015, 0x000000C0, 0x3 } },
351 	{ .hsw = { 0x80000018, 0x000000C0, 0x3 } },
352 };
353 
354 static const struct intel_ddi_buf_trans skl_y_trans_hdmi = {
355 	.entries = _skl_y_trans_hdmi,
356 	.num_entries = ARRAY_SIZE(_skl_y_trans_hdmi),
357 	.hdmi_default_entry = 8,
358 };
359 
360 static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = {
361 						/* Idx	NT mV diff	db  */
362 	{ .bxt = { 52,  0x9A, 0, 128, } },	/* 0:	400		0   */
363 	{ .bxt = { 78,  0x9A, 0, 85,  } },	/* 1:	400		3.5 */
364 	{ .bxt = { 104, 0x9A, 0, 64,  } },	/* 2:	400		6   */
365 	{ .bxt = { 154, 0x9A, 0, 43,  } },	/* 3:	400		9.5 */
366 	{ .bxt = { 77,  0x9A, 0, 128, } },	/* 4:	600		0   */
367 	{ .bxt = { 116, 0x9A, 0, 85,  } },	/* 5:	600		3.5 */
368 	{ .bxt = { 154, 0x9A, 0, 64,  } },	/* 6:	600		6   */
369 	{ .bxt = { 102, 0x9A, 0, 128, } },	/* 7:	800		0   */
370 	{ .bxt = { 154, 0x9A, 0, 85,  } },	/* 8:	800		3.5 */
371 	{ .bxt = { 154, 0x9A, 1, 128, } },	/* 9:	1200		0   */
372 };
373 
374 static const struct intel_ddi_buf_trans bxt_trans_dp = {
375 	.entries = _bxt_trans_dp,
376 	.num_entries = ARRAY_SIZE(_bxt_trans_dp),
377 };
378 
379 static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = {
380 					/* Idx	NT mV diff	db  */
381 	{ .bxt = { 26, 0, 0, 128, } },	/* 0:	200		0   */
382 	{ .bxt = { 38, 0, 0, 112, } },	/* 1:	200		1.5 */
383 	{ .bxt = { 48, 0, 0, 96,  } },	/* 2:	200		4   */
384 	{ .bxt = { 54, 0, 0, 69,  } },	/* 3:	200		6   */
385 	{ .bxt = { 32, 0, 0, 128, } },	/* 4:	250		0   */
386 	{ .bxt = { 48, 0, 0, 104, } },	/* 5:	250		1.5 */
387 	{ .bxt = { 54, 0, 0, 85,  } },	/* 6:	250		4   */
388 	{ .bxt = { 43, 0, 0, 128, } },	/* 7:	300		0   */
389 	{ .bxt = { 54, 0, 0, 101, } },	/* 8:	300		1.5 */
390 	{ .bxt = { 48, 0, 0, 128, } },	/* 9:	300		0   */
391 };
392 
393 static const struct intel_ddi_buf_trans bxt_trans_edp = {
394 	.entries = _bxt_trans_edp,
395 	.num_entries = ARRAY_SIZE(_bxt_trans_edp),
396 };
397 
398 /* BSpec has 2 recommended values - entries 0 and 8.
399  * Using the entry with higher vswing.
400  */
401 static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = {
402 						/* Idx	NT mV diff	db  */
403 	{ .bxt = { 52,  0x9A, 0, 128, } },	/* 0:	400		0   */
404 	{ .bxt = { 52,  0x9A, 0, 85,  } },	/* 1:	400		3.5 */
405 	{ .bxt = { 52,  0x9A, 0, 64,  } },	/* 2:	400		6   */
406 	{ .bxt = { 42,  0x9A, 0, 43,  } },	/* 3:	400		9.5 */
407 	{ .bxt = { 77,  0x9A, 0, 128, } },	/* 4:	600		0   */
408 	{ .bxt = { 77,  0x9A, 0, 85,  } },	/* 5:	600		3.5 */
409 	{ .bxt = { 77,  0x9A, 0, 64,  } },	/* 6:	600		6   */
410 	{ .bxt = { 102, 0x9A, 0, 128, } },	/* 7:	800		0   */
411 	{ .bxt = { 102, 0x9A, 0, 85,  } },	/* 8:	800		3.5 */
412 	{ .bxt = { 154, 0x9A, 1, 128, } },	/* 9:	1200		0   */
413 };
414 
415 static const struct intel_ddi_buf_trans bxt_trans_hdmi = {
416 	.entries = _bxt_trans_hdmi,
417 	.num_entries = ARRAY_SIZE(_bxt_trans_hdmi),
418 	.hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
419 };
420 
421 /* icl_combo_phy_trans */
422 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
423 							/* NT mV Trans mV db    */
424 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
425 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
426 	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
427 	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
428 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
429 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
430 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
431 	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
432 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
433 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
434 };
435 
436 static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = {
437 	.entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
438 	.num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
439 };
440 
441 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = {
442 							/* NT mV Trans mV db    */
443 	{ .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
444 	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
445 	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
446 	{ .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },	/* 200   350      4.9   */
447 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
448 	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
449 	{ .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
450 	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
451 	{ .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
452 	{ .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
453 };
454 
455 static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = {
456 	.entries = _icl_combo_phy_trans_edp_hbr2,
457 	.num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
458 };
459 
460 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = {
461 							/* NT mV Trans mV db    */
462 	{ .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },	/* 450   450      0.0   */
463 	{ .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },	/* 450   650      3.2   */
464 	{ .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },	/* 450   850      5.5   */
465 	{ .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },	/* 650   650      0.0   ALS */
466 	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 650   850      2.3   */
467 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 850   850      0.0   */
468 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   850      3.0   */
469 };
470 
471 static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
472 	.entries = _icl_combo_phy_trans_hdmi,
473 	.num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi),
474 	.hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
475 };
476 
477 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
478 							/* NT mV Trans mV db    */
479 	{ .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
480 	{ .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
481 	{ .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
482 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 350   900      8.2   */
483 	{ .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
484 	{ .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
485 	{ .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
486 	{ .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
487 	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
488 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
489 };
490 
491 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = {
492 	.entries = _ehl_combo_phy_trans_dp,
493 	.num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp),
494 };
495 
496 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = {
497 							/* NT mV Trans mV db    */
498 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
499 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
500 	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
501 	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 200   350      4.9   */
502 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
503 	{ .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },	/* 250   300      1.6   */
504 	{ .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },	/* 250   350      2.9   */
505 	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
506 	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
507 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
508 };
509 
510 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = {
511 	.entries = _ehl_combo_phy_trans_edp_hbr2,
512 	.num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2),
513 };
514 
515 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = {
516 							/* NT mV Trans mV db    */
517 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
518 	{ .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },	/* 200   250      1.9   */
519 	{ .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },	/* 200   300      3.5   */
520 	{ .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },	/* 200   350      4.9   */
521 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
522 	{ .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
523 	{ .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },	/* 250   350      2.9   */
524 	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
525 	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
526 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
527 };
528 
529 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = {
530 	.entries = _jsl_combo_phy_trans_edp_hbr,
531 	.num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr),
532 };
533 
534 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = {
535 							/* NT mV Trans mV db    */
536 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   200      0.0   */
537 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 200   250      1.9   */
538 	{ .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },	/* 200   300      3.5   */
539 	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 200   350      4.9   */
540 	{ .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   250      0.0   */
541 	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 250   300      1.6   */
542 	{ .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },	/* 250   350      2.9   */
543 	{ .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },	/* 300   300      0.0   */
544 	{ .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
545 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
546 };
547 
548 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = {
549 	.entries = _jsl_combo_phy_trans_edp_hbr2,
550 	.num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2),
551 };
552 
553 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = {
554 							/* NT mV Trans mV db    */
555 	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
556 	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
557 	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
558 	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
559 	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
560 	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
561 	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
562 	{ .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
563 	{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },	/* 600   900      3.5   */
564 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
565 };
566 
567 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = {
568 	.entries = _dg1_combo_phy_trans_dp_rbr_hbr,
569 	.num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr),
570 };
571 
572 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = {
573 							/* NT mV Trans mV db    */
574 	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
575 	{ .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },	/* 350   500      3.1   */
576 	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
577 	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
578 	{ .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
579 	{ .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
580 	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
581 	{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
582 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
583 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
584 };
585 
586 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = {
587 	.entries = _dg1_combo_phy_trans_dp_hbr2_hbr3,
588 	.num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3),
589 };
590 
591 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = {
592 					/* Voltage swing  pre-emphasis */
593 	{ .mg = { 0x18, 0x00, 0x00 } },	/* 0              0   */
594 	{ .mg = { 0x1D, 0x00, 0x05 } },	/* 0              1   */
595 	{ .mg = { 0x24, 0x00, 0x0C } },	/* 0              2   */
596 	{ .mg = { 0x2B, 0x00, 0x14 } },	/* 0              3   */
597 	{ .mg = { 0x21, 0x00, 0x00 } },	/* 1              0   */
598 	{ .mg = { 0x2B, 0x00, 0x08 } },	/* 1              1   */
599 	{ .mg = { 0x30, 0x00, 0x0F } },	/* 1              2   */
600 	{ .mg = { 0x31, 0x00, 0x03 } },	/* 2              0   */
601 	{ .mg = { 0x34, 0x00, 0x0B } },	/* 2              1   */
602 	{ .mg = { 0x3F, 0x00, 0x00 } },	/* 3              0   */
603 };
604 
605 static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = {
606 	.entries = _icl_mg_phy_trans_rbr_hbr,
607 	.num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr),
608 };
609 
610 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = {
611 					/* Voltage swing  pre-emphasis */
612 	{ .mg = { 0x18, 0x00, 0x00 } },	/* 0              0   */
613 	{ .mg = { 0x1D, 0x00, 0x05 } },	/* 0              1   */
614 	{ .mg = { 0x24, 0x00, 0x0C } },	/* 0              2   */
615 	{ .mg = { 0x2B, 0x00, 0x14 } },	/* 0              3   */
616 	{ .mg = { 0x26, 0x00, 0x00 } },	/* 1              0   */
617 	{ .mg = { 0x2C, 0x00, 0x07 } },	/* 1              1   */
618 	{ .mg = { 0x33, 0x00, 0x0C } },	/* 1              2   */
619 	{ .mg = { 0x2E, 0x00, 0x00 } },	/* 2              0   */
620 	{ .mg = { 0x36, 0x00, 0x09 } },	/* 2              1   */
621 	{ .mg = { 0x3F, 0x00, 0x00 } },	/* 3              0   */
622 };
623 
624 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = {
625 	.entries = _icl_mg_phy_trans_hbr2_hbr3,
626 	.num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3),
627 };
628 
629 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = {
630 					/* HDMI Preset	VS	Pre-emph */
631 	{ .mg = { 0x1A, 0x0, 0x0 } },	/* 1		400mV	0dB */
632 	{ .mg = { 0x20, 0x0, 0x0 } },	/* 2		500mV	0dB */
633 	{ .mg = { 0x29, 0x0, 0x0 } },	/* 3		650mV	0dB */
634 	{ .mg = { 0x32, 0x0, 0x0 } },	/* 4		800mV	0dB */
635 	{ .mg = { 0x3F, 0x0, 0x0 } },	/* 5		1000mV	0dB */
636 	{ .mg = { 0x3A, 0x0, 0x5 } },	/* 6		Full	-1.5 dB */
637 	{ .mg = { 0x39, 0x0, 0x6 } },	/* 7		Full	-1.8 dB */
638 	{ .mg = { 0x38, 0x0, 0x7 } },	/* 8		Full	-2 dB */
639 	{ .mg = { 0x37, 0x0, 0x8 } },	/* 9		Full	-2.5 dB */
640 	{ .mg = { 0x36, 0x0, 0x9 } },	/* 10		Full	-3 dB */
641 };
642 
643 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = {
644 	.entries = _icl_mg_phy_trans_hdmi,
645 	.num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi),
646 	.hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1,
647 };
648 
649 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = {
650 					/* VS	pre-emp	Non-trans mV	Pre-emph dB */
651 	{ .dkl = { 0x7, 0x0, 0x00 } },	/* 0	0	400mV		0 dB */
652 	{ .dkl = { 0x5, 0x0, 0x05 } },	/* 0	1	400mV		3.5 dB */
653 	{ .dkl = { 0x2, 0x0, 0x0B } },	/* 0	2	400mV		6 dB */
654 	{ .dkl = { 0x0, 0x0, 0x18 } },	/* 0	3	400mV		9.5 dB */
655 	{ .dkl = { 0x5, 0x0, 0x00 } },	/* 1	0	600mV		0 dB */
656 	{ .dkl = { 0x2, 0x0, 0x08 } },	/* 1	1	600mV		3.5 dB */
657 	{ .dkl = { 0x0, 0x0, 0x14 } },	/* 1	2	600mV		6 dB */
658 	{ .dkl = { 0x2, 0x0, 0x00 } },	/* 2	0	800mV		0 dB */
659 	{ .dkl = { 0x0, 0x0, 0x0B } },	/* 2	1	800mV		3.5 dB */
660 	{ .dkl = { 0x0, 0x0, 0x00 } },	/* 3	0	1200mV		0 dB HDMI default */
661 };
662 
663 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = {
664 	.entries = _tgl_dkl_phy_trans_dp_hbr,
665 	.num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr),
666 };
667 
668 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = {
669 					/* VS	pre-emp	Non-trans mV	Pre-emph dB */
670 	{ .dkl = { 0x7, 0x0, 0x00 } },	/* 0	0	400mV		0 dB */
671 	{ .dkl = { 0x5, 0x0, 0x05 } },	/* 0	1	400mV		3.5 dB */
672 	{ .dkl = { 0x2, 0x0, 0x0B } },	/* 0	2	400mV		6 dB */
673 	{ .dkl = { 0x0, 0x0, 0x19 } },	/* 0	3	400mV		9.5 dB */
674 	{ .dkl = { 0x5, 0x0, 0x00 } },	/* 1	0	600mV		0 dB */
675 	{ .dkl = { 0x2, 0x0, 0x08 } },	/* 1	1	600mV		3.5 dB */
676 	{ .dkl = { 0x0, 0x0, 0x14 } },	/* 1	2	600mV		6 dB */
677 	{ .dkl = { 0x2, 0x0, 0x00 } },	/* 2	0	800mV		0 dB */
678 	{ .dkl = { 0x0, 0x0, 0x0B } },	/* 2	1	800mV		3.5 dB */
679 	{ .dkl = { 0x0, 0x0, 0x00 } },	/* 3	0	1200mV		0 dB HDMI default */
680 };
681 
682 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = {
683 	.entries = _tgl_dkl_phy_trans_dp_hbr2,
684 	.num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2),
685 };
686 
687 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = {
688 					/* HDMI Preset	VS	Pre-emph */
689 	{ .dkl = { 0x7, 0x0, 0x0 } },	/* 1		400mV	0dB */
690 	{ .dkl = { 0x6, 0x0, 0x0 } },	/* 2		500mV	0dB */
691 	{ .dkl = { 0x4, 0x0, 0x0 } },	/* 3		650mV	0dB */
692 	{ .dkl = { 0x2, 0x0, 0x0 } },	/* 4		800mV	0dB */
693 	{ .dkl = { 0x0, 0x0, 0x0 } },	/* 5		1000mV	0dB */
694 	{ .dkl = { 0x0, 0x0, 0x5 } },	/* 6		Full	-1.5 dB */
695 	{ .dkl = { 0x0, 0x0, 0x6 } },	/* 7		Full	-1.8 dB */
696 	{ .dkl = { 0x0, 0x0, 0x7 } },	/* 8		Full	-2 dB */
697 	{ .dkl = { 0x0, 0x0, 0x8 } },	/* 9		Full	-2.5 dB */
698 	{ .dkl = { 0x0, 0x0, 0xA } },	/* 10		Full	-3 dB */
699 };
700 
701 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = {
702 	.entries = _tgl_dkl_phy_trans_hdmi,
703 	.num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi),
704 	.hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1,
705 };
706 
707 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = {
708 							/* NT mV Trans mV db    */
709 	{ .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
710 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
711 	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
712 	{ .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
713 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
714 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
715 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
716 	{ .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
717 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
718 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
719 };
720 
721 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = {
722 	.entries = _tgl_combo_phy_trans_dp_hbr,
723 	.num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr),
724 };
725 
726 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = {
727 							/* NT mV Trans mV db    */
728 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
729 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
730 	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
731 	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
732 	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
733 	{ .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
734 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
735 	{ .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
736 	{ .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
737 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
738 };
739 
740 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = {
741 	.entries = _tgl_combo_phy_trans_dp_hbr2,
742 	.num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2),
743 };
744 
745 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = {
746 							/* NT mV Trans mV db    */
747 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
748 	{ .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },	/* 350   500      3.1   */
749 	{ .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },	/* 350   700      6.0   */
750 	{ .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },	/* 350   900      8.2   */
751 	{ .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
752 	{ .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },	/* 500   700      2.9   */
753 	{ .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
754 	{ .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },	/* 650   700      0.6   */
755 	{ .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },	/* 600   900      3.5   */
756 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
757 };
758 
759 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = {
760 	.entries = _tgl_uy_combo_phy_trans_dp_hbr2,
761 	.num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2),
762 };
763 
764 /*
765  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
766  * that DisplayPort specification requires
767  */
768 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = {
769 							/* VS	pre-emp	*/
770 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	0	*/
771 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	1	*/
772 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	2	*/
773 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 0	3	*/
774 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	0	*/
775 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	1	*/
776 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1	2	*/
777 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	0	*/
778 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 2	1	*/
779 };
780 
781 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = {
782 	.entries = _tgl_combo_phy_trans_edp_hbr2_hobl,
783 	.num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl),
784 };
785 
786 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = {
787 							/* NT mV Trans mV db    */
788 	{ .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
789 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
790 	{ .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
791 	{ .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },	/* 350   900      8.2   */
792 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
793 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
794 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
795 	{ .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
796 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
797 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
798 };
799 
800 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = {
801 	.entries = _rkl_combo_phy_trans_dp_hbr,
802 	.num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr),
803 };
804 
805 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = {
806 							/* NT mV Trans mV db    */
807 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
808 	{ .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },	/* 350   500      3.1   */
809 	{ .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },	/* 350   700      6.0   */
810 	{ .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },	/* 350   900      8.2   */
811 	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
812 	{ .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },	/* 500   700      2.9   */
813 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
814 	{ .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
815 	{ .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },	/* 600   900      3.5   */
816 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
817 };
818 
819 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = {
820 	.entries = _rkl_combo_phy_trans_dp_hbr2_hbr3,
821 	.num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3),
822 };
823 
824 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = {
825 							/* NT mV Trans mV db    */
826 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
827 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
828 	{ .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
829 	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
830 	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
831 	{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
832 	{ .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
833 	{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
834 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
835 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
836 };
837 
838 static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = {
839 	.entries = _adls_combo_phy_trans_dp_hbr2_hbr3,
840 	.num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3),
841 };
842 
843 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = {
844 							/* NT mV Trans mV db    */
845 	{ .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } },	/* 200   200      0.0   */
846 	{ .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } },	/* 200   250      1.9   */
847 	{ .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } },	/* 200   300      3.5   */
848 	{ .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } },	/* 200   350      4.9   */
849 	{ .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } },	/* 250   250      0.0   */
850 	{ .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } },	/* 250   300      1.6   */
851 	{ .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },	/* 250   350      2.9   */
852 	{ .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } },	/* 300   300      0.0   */
853 	{ .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },	/* 300   350      1.3   */
854 	{ .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } },	/* 350   350      0.0   */
855 };
856 
857 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = {
858 	.entries = _adls_combo_phy_trans_edp_hbr2,
859 	.num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2),
860 };
861 
862 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = {
863 							/* NT mV Trans mV db    */
864 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
865 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
866 	{ .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
867 	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
868 	{ .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
869 	{ .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },	/* 500   700      2.9   */
870 	{ .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },	/* 500   900      5.1   */
871 	{ .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
872 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
873 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
874 };
875 
876 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
877 	.entries = _adls_combo_phy_trans_edp_hbr3,
878 	.num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
879 };
880 
881 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_hdmi[] = {
882 							/* NT mV Trans mV    db   */
883 	{ .icl = { 0x6, 0x60, 0x3F, 0x00, 0x00 } },	/*  400    400      0.0 */
884 	{ .icl = { 0x6, 0x68, 0x3F, 0x00, 0x00 } },	/*  500    500      0.0 */
885 	{ .icl = { 0xA, 0x73, 0x3F, 0x00, 0x00 } },	/*  650    650      0.0 ALS */
886 	{ .icl = { 0xA, 0x78, 0x3F, 0x00, 0x00 } },	/*  800    800      0.0 */
887 	{ .icl = { 0xB, 0x7F, 0x3F, 0x00, 0x00 } },	/* 1000   1000      0.0 Re-timer */
888 	{ .icl = { 0xB, 0x7F, 0x3B, 0x00, 0x04 } },	/* Full    Red     -1.5 */
889 	{ .icl = { 0xB, 0x7F, 0x39, 0x00, 0x06 } },	/* Full    Red     -1.8 */
890 	{ .icl = { 0xB, 0x7F, 0x37, 0x00, 0x08 } },	/* Full    Red     -2.0 CRLS */
891 	{ .icl = { 0xB, 0x7F, 0x35, 0x00, 0x0A } },	/* Full    Red     -2.5 */
892 	{ .icl = { 0xB, 0x7F, 0x33, 0x00, 0x0C } },	/* Full    Red     -3.0 */
893 };
894 
895 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_hdmi = {
896 	.entries = _adlp_combo_phy_trans_hdmi,
897 	.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi),
898 	.hdmi_default_entry = ARRAY_SIZE(_adlp_combo_phy_trans_hdmi) - 1,
899 };
900 
901 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
902 							/* NT mV Trans mV db    */
903 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
904 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
905 	{ .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } },	/* 350   700      6.0   */
906 	{ .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },	/* 350   900      8.2   */
907 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
908 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
909 	{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },	/* 500   900      5.1   */
910 	{ .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } },	/* 650   700      0.6   */
911 	{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },	/* 600   900      3.5   */
912 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
913 };
914 
915 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = {
916 	.entries = _adlp_combo_phy_trans_dp_hbr,
917 	.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr),
918 };
919 
920 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = {
921 							/* NT mV Trans mV db    */
922 	{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },	/* 350   350      0.0   */
923 	{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },	/* 350   500      3.1   */
924 	{ .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },	/* 350   700      6.0   */
925 	{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },	/* 350   900      8.2   */
926 	{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },	/* 500   500      0.0   */
927 	{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },	/* 500   700      2.9   */
928 	{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },	/* 500   900      5.1   */
929 	{ .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } },	/* 650   700      0.6   */
930 	{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },	/* 600   900      3.5   */
931 	{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },	/* 900   900      0.0   */
932 };
933 
934 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
935 	.entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
936 	.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
937 };
938 
939 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
940 	.entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
941 	.num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
942 };
943 
944 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
945 	.entries = _icl_combo_phy_trans_edp_hbr2,
946 	.num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
947 };
948 
949 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = {
950 					/* VS	pre-emp	Non-trans mV	Pre-emph dB */
951 	{ .dkl = { 0x7, 0x0, 0x01 } },	/* 0	0	400mV		0 dB */
952 	{ .dkl = { 0x5, 0x0, 0x06 } },	/* 0	1	400mV		3.5 dB */
953 	{ .dkl = { 0x2, 0x0, 0x0B } },	/* 0	2	400mV		6 dB */
954 	{ .dkl = { 0x0, 0x0, 0x17 } },	/* 0	3	400mV		9.5 dB */
955 	{ .dkl = { 0x5, 0x0, 0x00 } },	/* 1	0	600mV		0 dB */
956 	{ .dkl = { 0x2, 0x0, 0x08 } },	/* 1	1	600mV		3.5 dB */
957 	{ .dkl = { 0x0, 0x0, 0x14 } },	/* 1	2	600mV		6 dB */
958 	{ .dkl = { 0x2, 0x0, 0x00 } },	/* 2	0	800mV		0 dB */
959 	{ .dkl = { 0x0, 0x0, 0x0B } },	/* 2	1	800mV		3.5 dB */
960 	{ .dkl = { 0x0, 0x0, 0x00 } },	/* 3	0	1200mV		0 dB */
961 };
962 
963 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = {
964 	.entries = _adlp_dkl_phy_trans_dp_hbr,
965 	.num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr),
966 };
967 
968 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = {
969 					/* VS	pre-emp	Non-trans mV	Pre-emph dB */
970 	{ .dkl = { 0x7, 0x0, 0x00 } },	/* 0	0	400mV		0 dB */
971 	{ .dkl = { 0x5, 0x0, 0x04 } },	/* 0	1	400mV		3.5 dB */
972 	{ .dkl = { 0x2, 0x0, 0x0A } },	/* 0	2	400mV		6 dB */
973 	{ .dkl = { 0x0, 0x0, 0x18 } },	/* 0	3	400mV		9.5 dB */
974 	{ .dkl = { 0x5, 0x0, 0x00 } },	/* 1	0	600mV		0 dB */
975 	{ .dkl = { 0x2, 0x0, 0x06 } },	/* 1	1	600mV		3.5 dB */
976 	{ .dkl = { 0x0, 0x0, 0x14 } },	/* 1	2	600mV		6 dB */
977 	{ .dkl = { 0x2, 0x0, 0x00 } },	/* 2	0	800mV		0 dB */
978 	{ .dkl = { 0x0, 0x0, 0x09 } },	/* 2	1	800mV		3.5 dB */
979 	{ .dkl = { 0x0, 0x0, 0x00 } },	/* 3	0	1200mV		0 dB */
980 };
981 
982 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
983 	.entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3,
984 	.num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3),
985 };
986 
987 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
988 	{ .snps = { 25, 0, 0 } },	/* VS 0, pre-emph 0 */
989 	{ .snps = { 32, 0, 6 } },	/* VS 0, pre-emph 1 */
990 	{ .snps = { 35, 0, 10 } },	/* VS 0, pre-emph 2 */
991 	{ .snps = { 43, 0, 17 } },	/* VS 0, pre-emph 3 */
992 	{ .snps = { 35, 0, 0 } },	/* VS 1, pre-emph 0 */
993 	{ .snps = { 45, 0, 8 } },	/* VS 1, pre-emph 1 */
994 	{ .snps = { 48, 0, 14 } },	/* VS 1, pre-emph 2 */
995 	{ .snps = { 47, 0, 0 } },	/* VS 2, pre-emph 0 */
996 	{ .snps = { 55, 0, 7 } },	/* VS 2, pre-emph 1 */
997 	{ .snps = { 62, 0, 0 } },	/* VS 3, pre-emph 0 */
998 };
999 
1000 static const struct intel_ddi_buf_trans dg2_snps_trans = {
1001 	.entries = _dg2_snps_trans,
1002 	.num_entries = ARRAY_SIZE(_dg2_snps_trans),
1003 	.hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1,
1004 };
1005 
1006 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
1007 	{ .snps = { 62, 0, 0 } },	/* preset 0 */
1008 	{ .snps = { 55, 0, 7 } },	/* preset 1 */
1009 	{ .snps = { 50, 0, 12 } },	/* preset 2 */
1010 	{ .snps = { 44, 0, 18 } },	/* preset 3 */
1011 	{ .snps = { 35, 0, 21 } },	/* preset 4 */
1012 	{ .snps = { 59, 3, 0 } },	/* preset 5 */
1013 	{ .snps = { 53, 3, 6 } },	/* preset 6 */
1014 	{ .snps = { 48, 3, 11 } },	/* preset 7 */
1015 	{ .snps = { 42, 5, 15 } },	/* preset 8 */
1016 	{ .snps = { 37, 5, 20 } },	/* preset 9 */
1017 	{ .snps = { 56, 6, 0 } },	/* preset 10 */
1018 	{ .snps = { 48, 7, 7 } },	/* preset 11 */
1019 	{ .snps = { 45, 7, 10 } },	/* preset 12 */
1020 	{ .snps = { 39, 8, 15 } },	/* preset 13 */
1021 	{ .snps = { 48, 14, 0 } },	/* preset 14 */
1022 	{ .snps = { 45, 4, 4 } },	/* preset 15 */
1023 };
1024 
1025 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
1026 	.entries = _dg2_snps_trans_uhbr,
1027 	.num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
1028 };
1029 
1030 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
1031 {
1032 	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
1033 }
1034 
1035 static bool use_edp_hobl(struct intel_encoder *encoder)
1036 {
1037 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1038 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1039 
1040 	return i915->vbt.edp.hobl && !intel_dp->hobl_failed;
1041 }
1042 
1043 static bool use_edp_low_vswing(struct intel_encoder *encoder)
1044 {
1045 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1046 
1047 	return i915->vbt.edp.low_vswing;
1048 }
1049 
1050 static const struct intel_ddi_buf_trans *
1051 intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries)
1052 {
1053 	*num_entries = trans->num_entries;
1054 	return trans;
1055 }
1056 
1057 static const struct intel_ddi_buf_trans *
1058 hsw_get_buf_trans(struct intel_encoder *encoder,
1059 		  const struct intel_crtc_state *crtc_state,
1060 		  int *n_entries)
1061 {
1062 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1063 		return intel_get_buf_trans(&hsw_trans_fdi, n_entries);
1064 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1065 		return intel_get_buf_trans(&hsw_trans_hdmi, n_entries);
1066 	else
1067 		return intel_get_buf_trans(&hsw_trans_dp, n_entries);
1068 }
1069 
1070 static const struct intel_ddi_buf_trans *
1071 bdw_get_buf_trans(struct intel_encoder *encoder,
1072 		  const struct intel_crtc_state *crtc_state,
1073 		  int *n_entries)
1074 {
1075 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1076 		return intel_get_buf_trans(&bdw_trans_fdi, n_entries);
1077 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1078 		return intel_get_buf_trans(&bdw_trans_hdmi, n_entries);
1079 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1080 		 use_edp_low_vswing(encoder))
1081 		return intel_get_buf_trans(&bdw_trans_edp, n_entries);
1082 	else
1083 		return intel_get_buf_trans(&bdw_trans_dp, n_entries);
1084 }
1085 
1086 static int skl_buf_trans_num_entries(enum port port, int n_entries)
1087 {
1088 	/* Only DDIA and DDIE can select the 10th register with DP */
1089 	if (port == PORT_A || port == PORT_E)
1090 		return min(n_entries, 10);
1091 	else
1092 		return min(n_entries, 9);
1093 }
1094 
1095 static const struct intel_ddi_buf_trans *
1096 _skl_get_buf_trans_dp(struct intel_encoder *encoder,
1097 		      const struct intel_ddi_buf_trans *trans,
1098 		      int *n_entries)
1099 {
1100 	trans = intel_get_buf_trans(trans, n_entries);
1101 	*n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1102 	return trans;
1103 }
1104 
1105 static const struct intel_ddi_buf_trans *
1106 skl_y_get_buf_trans(struct intel_encoder *encoder,
1107 		    const struct intel_crtc_state *crtc_state,
1108 		    int *n_entries)
1109 {
1110 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1111 		return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1112 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1113 		 use_edp_low_vswing(encoder))
1114 		return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1115 	else
1116 		return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries);
1117 }
1118 
1119 static const struct intel_ddi_buf_trans *
1120 skl_u_get_buf_trans(struct intel_encoder *encoder,
1121 		    const struct intel_crtc_state *crtc_state,
1122 		    int *n_entries)
1123 {
1124 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1125 		return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1126 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1127 		 use_edp_low_vswing(encoder))
1128 		return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1129 	else
1130 		return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries);
1131 }
1132 
1133 static const struct intel_ddi_buf_trans *
1134 skl_get_buf_trans(struct intel_encoder *encoder,
1135 		  const struct intel_crtc_state *crtc_state,
1136 		  int *n_entries)
1137 {
1138 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1139 		return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1140 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1141 		 use_edp_low_vswing(encoder))
1142 		return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1143 	else
1144 		return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries);
1145 }
1146 
1147 static const struct intel_ddi_buf_trans *
1148 kbl_y_get_buf_trans(struct intel_encoder *encoder,
1149 		    const struct intel_crtc_state *crtc_state,
1150 		    int *n_entries)
1151 {
1152 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1153 		return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1154 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1155 		 use_edp_low_vswing(encoder))
1156 		return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1157 	else
1158 		return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries);
1159 }
1160 
1161 static const struct intel_ddi_buf_trans *
1162 kbl_u_get_buf_trans(struct intel_encoder *encoder,
1163 		    const struct intel_crtc_state *crtc_state,
1164 		    int *n_entries)
1165 {
1166 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1167 		return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1168 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1169 		 use_edp_low_vswing(encoder))
1170 		return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1171 	else
1172 		return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries);
1173 }
1174 
1175 static const struct intel_ddi_buf_trans *
1176 kbl_get_buf_trans(struct intel_encoder *encoder,
1177 		  const struct intel_crtc_state *crtc_state,
1178 		  int *n_entries)
1179 {
1180 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1181 		return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1182 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1183 		 use_edp_low_vswing(encoder))
1184 		return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1185 	else
1186 		return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries);
1187 }
1188 
1189 static const struct intel_ddi_buf_trans *
1190 bxt_get_buf_trans(struct intel_encoder *encoder,
1191 		  const struct intel_crtc_state *crtc_state,
1192 		  int *n_entries)
1193 {
1194 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1195 		return intel_get_buf_trans(&bxt_trans_hdmi, n_entries);
1196 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1197 		 use_edp_low_vswing(encoder))
1198 		return intel_get_buf_trans(&bxt_trans_edp, n_entries);
1199 	else
1200 		return intel_get_buf_trans(&bxt_trans_dp, n_entries);
1201 }
1202 
1203 static const struct intel_ddi_buf_trans *
1204 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1205 			   const struct intel_crtc_state *crtc_state,
1206 			   int *n_entries)
1207 {
1208 	return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1209 				   n_entries);
1210 }
1211 
1212 static const struct intel_ddi_buf_trans *
1213 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1214 			    const struct intel_crtc_state *crtc_state,
1215 			    int *n_entries)
1216 {
1217 	if (crtc_state->port_clock > 540000) {
1218 		return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1219 					   n_entries);
1220 	} else if (use_edp_low_vswing(encoder)) {
1221 		return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1222 					   n_entries);
1223 	}
1224 
1225 	return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1226 }
1227 
1228 static const struct intel_ddi_buf_trans *
1229 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1230 			const struct intel_crtc_state *crtc_state,
1231 			int *n_entries)
1232 {
1233 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1234 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1235 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1236 		return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1237 	else
1238 		return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1239 }
1240 
1241 static const struct intel_ddi_buf_trans *
1242 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1243 			const struct intel_crtc_state *crtc_state,
1244 			int *n_entries)
1245 {
1246 	if (crtc_state->port_clock > 270000) {
1247 		return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3,
1248 					   n_entries);
1249 	} else {
1250 		return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr,
1251 					   n_entries);
1252 	}
1253 }
1254 
1255 static const struct intel_ddi_buf_trans *
1256 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1257 		     const struct intel_crtc_state *crtc_state,
1258 		     int *n_entries)
1259 {
1260 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1261 		return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries);
1262 	else
1263 		return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1264 }
1265 
1266 static const struct intel_ddi_buf_trans *
1267 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1268 			    const struct intel_crtc_state *crtc_state,
1269 			    int *n_entries)
1270 {
1271 	if (crtc_state->port_clock > 270000)
1272 		return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries);
1273 	else
1274 		return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries);
1275 }
1276 
1277 static const struct intel_ddi_buf_trans *
1278 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1279 			const struct intel_crtc_state *crtc_state,
1280 			int *n_entries)
1281 {
1282 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1283 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1284 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1285 		 use_edp_low_vswing(encoder))
1286 		return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1287 	else
1288 		return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries);
1289 }
1290 
1291 static const struct intel_ddi_buf_trans *
1292 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1293 			    const struct intel_crtc_state *crtc_state,
1294 			    int *n_entries)
1295 {
1296 	if (crtc_state->port_clock > 270000)
1297 		return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries);
1298 	else
1299 		return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries);
1300 }
1301 
1302 static const struct intel_ddi_buf_trans *
1303 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1304 			const struct intel_crtc_state *crtc_state,
1305 			int *n_entries)
1306 {
1307 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1308 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1309 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1310 		 use_edp_low_vswing(encoder))
1311 		return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1312 	else
1313 		return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries);
1314 }
1315 
1316 static const struct intel_ddi_buf_trans *
1317 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1318 			   const struct intel_crtc_state *crtc_state,
1319 			   int *n_entries)
1320 {
1321 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1322 
1323 	if (crtc_state->port_clock > 270000) {
1324 		if (IS_TGL_UY(dev_priv)) {
1325 			return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
1326 						   n_entries);
1327 		} else {
1328 			return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2,
1329 						   n_entries);
1330 		}
1331 	} else {
1332 		return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr,
1333 					   n_entries);
1334 	}
1335 }
1336 
1337 static const struct intel_ddi_buf_trans *
1338 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1339 			    const struct intel_crtc_state *crtc_state,
1340 			    int *n_entries)
1341 {
1342 	if (crtc_state->port_clock > 540000) {
1343 		return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1344 					   n_entries);
1345 	} else if (use_edp_hobl(encoder)) {
1346 		return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1347 					   n_entries);
1348 	} else if (use_edp_low_vswing(encoder)) {
1349 		return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1350 					   n_entries);
1351 	}
1352 
1353 	return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1354 }
1355 
1356 static const struct intel_ddi_buf_trans *
1357 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1358 			const struct intel_crtc_state *crtc_state,
1359 			int *n_entries)
1360 {
1361 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1362 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1363 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1364 		return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1365 	else
1366 		return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1367 }
1368 
1369 static const struct intel_ddi_buf_trans *
1370 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1371 			   const struct intel_crtc_state *crtc_state,
1372 			   int *n_entries)
1373 {
1374 	if (crtc_state->port_clock > 270000)
1375 		return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3,
1376 					   n_entries);
1377 	else
1378 		return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr,
1379 					   n_entries);
1380 }
1381 
1382 static const struct intel_ddi_buf_trans *
1383 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1384 			    const struct intel_crtc_state *crtc_state,
1385 			    int *n_entries)
1386 {
1387 	if (crtc_state->port_clock > 540000)
1388 		return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1389 					   n_entries);
1390 	else if (use_edp_hobl(encoder))
1391 		return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1392 					   n_entries);
1393 	else if (use_edp_low_vswing(encoder))
1394 		return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1395 					   n_entries);
1396 	else
1397 		return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1398 }
1399 
1400 static const struct intel_ddi_buf_trans *
1401 dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1402 			const struct intel_crtc_state *crtc_state,
1403 			int *n_entries)
1404 {
1405 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1406 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1407 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1408 		return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1409 	else
1410 		return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1411 }
1412 
1413 static const struct intel_ddi_buf_trans *
1414 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1415 			   const struct intel_crtc_state *crtc_state,
1416 			   int *n_entries)
1417 {
1418 	if (crtc_state->port_clock > 270000)
1419 		return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1420 	else
1421 		return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries);
1422 }
1423 
1424 static const struct intel_ddi_buf_trans *
1425 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1426 			    const struct intel_crtc_state *crtc_state,
1427 			    int *n_entries)
1428 {
1429 	if (crtc_state->port_clock > 540000) {
1430 		return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1431 					   n_entries);
1432 	} else if (use_edp_hobl(encoder)) {
1433 		return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1434 					   n_entries);
1435 	} else if (use_edp_low_vswing(encoder)) {
1436 		return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1437 					   n_entries);
1438 	}
1439 
1440 	return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1441 }
1442 
1443 static const struct intel_ddi_buf_trans *
1444 rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1445 			const struct intel_crtc_state *crtc_state,
1446 			int *n_entries)
1447 {
1448 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1449 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1450 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1451 		return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1452 	else
1453 		return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1454 }
1455 
1456 static const struct intel_ddi_buf_trans *
1457 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1458 			    const struct intel_crtc_state *crtc_state,
1459 			    int *n_entries)
1460 {
1461 	if (crtc_state->port_clock > 270000)
1462 		return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1463 	else
1464 		return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries);
1465 }
1466 
1467 static const struct intel_ddi_buf_trans *
1468 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1469 			     const struct intel_crtc_state *crtc_state,
1470 			     int *n_entries)
1471 {
1472 	if (crtc_state->port_clock > 540000)
1473 		return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries);
1474 	else if (use_edp_hobl(encoder))
1475 		return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries);
1476 	else if (use_edp_low_vswing(encoder))
1477 		return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries);
1478 	else
1479 		return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1480 }
1481 
1482 static const struct intel_ddi_buf_trans *
1483 adls_get_combo_buf_trans(struct intel_encoder *encoder,
1484 			 const struct intel_crtc_state *crtc_state,
1485 			 int *n_entries)
1486 {
1487 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1488 		return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1489 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1490 		return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1491 	else
1492 		return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1493 }
1494 
1495 static const struct intel_ddi_buf_trans *
1496 adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1497 			    const struct intel_crtc_state *crtc_state,
1498 			    int *n_entries)
1499 {
1500 	if (crtc_state->port_clock > 270000)
1501 		return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1502 	else
1503 		return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries);
1504 }
1505 
1506 static const struct intel_ddi_buf_trans *
1507 adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1508 			     const struct intel_crtc_state *crtc_state,
1509 			     int *n_entries)
1510 {
1511 	if (crtc_state->port_clock > 540000) {
1512 		return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3,
1513 					   n_entries);
1514 	} else if (use_edp_hobl(encoder)) {
1515 		return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1516 					   n_entries);
1517 	} else if (use_edp_low_vswing(encoder)) {
1518 		return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2,
1519 					   n_entries);
1520 	}
1521 
1522 	return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1523 }
1524 
1525 static const struct intel_ddi_buf_trans *
1526 adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1527 			 const struct intel_crtc_state *crtc_state,
1528 			 int *n_entries)
1529 {
1530 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1531 		return intel_get_buf_trans(&adlp_combo_phy_trans_hdmi, n_entries);
1532 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1533 		return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1534 	else
1535 		return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1536 }
1537 
1538 static const struct intel_ddi_buf_trans *
1539 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1540 			 const struct intel_crtc_state *crtc_state,
1541 			 int *n_entries)
1542 {
1543 	if (crtc_state->port_clock > 270000) {
1544 		return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2,
1545 					   n_entries);
1546 	} else {
1547 		return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr,
1548 					   n_entries);
1549 	}
1550 }
1551 
1552 static const struct intel_ddi_buf_trans *
1553 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1554 		      const struct intel_crtc_state *crtc_state,
1555 		      int *n_entries)
1556 {
1557 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1558 		return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1559 	else
1560 		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1561 }
1562 
1563 static const struct intel_ddi_buf_trans *
1564 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1565 			  const struct intel_crtc_state *crtc_state,
1566 			  int *n_entries)
1567 {
1568 	if (crtc_state->port_clock > 270000) {
1569 		return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3,
1570 					   n_entries);
1571 	} else {
1572 		return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr,
1573 					   n_entries);
1574 	}
1575 }
1576 
1577 static const struct intel_ddi_buf_trans *
1578 adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1579 		       const struct intel_crtc_state *crtc_state,
1580 		       int *n_entries)
1581 {
1582 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1583 		return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1584 	else
1585 		return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1586 }
1587 
1588 static const struct intel_ddi_buf_trans *
1589 dg2_get_snps_buf_trans(struct intel_encoder *encoder,
1590 		       const struct intel_crtc_state *crtc_state,
1591 		       int *n_entries)
1592 {
1593 	if (intel_crtc_has_dp_encoder(crtc_state) &&
1594 	    intel_dp_is_uhbr(crtc_state))
1595 		return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
1596 	else
1597 		return intel_get_buf_trans(&dg2_snps_trans, n_entries);
1598 }
1599 
1600 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1601 {
1602 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1603 	enum phy phy = intel_port_to_phy(i915, encoder->port);
1604 
1605 	if (IS_DG2(i915)) {
1606 		encoder->get_buf_trans = dg2_get_snps_buf_trans;
1607 	} else if (IS_ALDERLAKE_P(i915)) {
1608 		if (intel_phy_is_combo(i915, phy))
1609 			encoder->get_buf_trans = adlp_get_combo_buf_trans;
1610 		else
1611 			encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1612 	} else if (IS_ALDERLAKE_S(i915)) {
1613 		encoder->get_buf_trans = adls_get_combo_buf_trans;
1614 	} else if (IS_ROCKETLAKE(i915)) {
1615 		encoder->get_buf_trans = rkl_get_combo_buf_trans;
1616 	} else if (IS_DG1(i915)) {
1617 		encoder->get_buf_trans = dg1_get_combo_buf_trans;
1618 	} else if (DISPLAY_VER(i915) >= 12) {
1619 		if (intel_phy_is_combo(i915, phy))
1620 			encoder->get_buf_trans = tgl_get_combo_buf_trans;
1621 		else
1622 			encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1623 	} else if (DISPLAY_VER(i915) == 11) {
1624 		if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
1625 			encoder->get_buf_trans = jsl_get_combo_buf_trans;
1626 		else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1627 			encoder->get_buf_trans = ehl_get_combo_buf_trans;
1628 		else if (intel_phy_is_combo(i915, phy))
1629 			encoder->get_buf_trans = icl_get_combo_buf_trans;
1630 		else
1631 			encoder->get_buf_trans = icl_get_mg_buf_trans;
1632 	} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1633 		encoder->get_buf_trans = bxt_get_buf_trans;
1634 	} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1635 		encoder->get_buf_trans = kbl_y_get_buf_trans;
1636 	} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1637 		encoder->get_buf_trans = kbl_u_get_buf_trans;
1638 	} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
1639 		encoder->get_buf_trans = kbl_get_buf_trans;
1640 	} else if (IS_SKL_ULX(i915)) {
1641 		encoder->get_buf_trans = skl_y_get_buf_trans;
1642 	} else if (IS_SKL_ULT(i915)) {
1643 		encoder->get_buf_trans = skl_u_get_buf_trans;
1644 	} else if (IS_SKYLAKE(i915)) {
1645 		encoder->get_buf_trans = skl_get_buf_trans;
1646 	} else if (IS_BROADWELL(i915)) {
1647 		encoder->get_buf_trans = bdw_get_buf_trans;
1648 	} else {
1649 		encoder->get_buf_trans = hsw_get_buf_trans;
1650 	}
1651 }
1652