1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_ddi.h" 8 #include "intel_ddi_buf_trans.h" 9 #include "intel_display_types.h" 10 11 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 12 * them for both DP and FDI transports, allowing those ports to 13 * automatically adapt to HDMI connections as well 14 */ 15 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 16 { 0x00FFFFFF, 0x0006000E, 0x0 }, 17 { 0x00D75FFF, 0x0005000A, 0x0 }, 18 { 0x00C30FFF, 0x00040006, 0x0 }, 19 { 0x80AAAFFF, 0x000B0000, 0x0 }, 20 { 0x00FFFFFF, 0x0005000A, 0x0 }, 21 { 0x00D75FFF, 0x000C0004, 0x0 }, 22 { 0x80C30FFF, 0x000B0000, 0x0 }, 23 { 0x00FFFFFF, 0x00040006, 0x0 }, 24 { 0x80D75FFF, 0x000B0000, 0x0 }, 25 }; 26 27 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 28 { 0x00FFFFFF, 0x0007000E, 0x0 }, 29 { 0x00D75FFF, 0x000F000A, 0x0 }, 30 { 0x00C30FFF, 0x00060006, 0x0 }, 31 { 0x00AAAFFF, 0x001E0000, 0x0 }, 32 { 0x00FFFFFF, 0x000F000A, 0x0 }, 33 { 0x00D75FFF, 0x00160004, 0x0 }, 34 { 0x00C30FFF, 0x001E0000, 0x0 }, 35 { 0x00FFFFFF, 0x00060006, 0x0 }, 36 { 0x00D75FFF, 0x001E0000, 0x0 }, 37 }; 38 39 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 40 /* Idx NT mV d T mV d db */ 41 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 42 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 43 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 44 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 45 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 46 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 47 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 48 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 49 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 50 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 51 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 52 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 53 }; 54 55 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 56 { 0x00FFFFFF, 0x00000012, 0x0 }, 57 { 0x00EBAFFF, 0x00020011, 0x0 }, 58 { 0x00C71FFF, 0x0006000F, 0x0 }, 59 { 0x00AAAFFF, 0x000E000A, 0x0 }, 60 { 0x00FFFFFF, 0x00020011, 0x0 }, 61 { 0x00DB6FFF, 0x0005000F, 0x0 }, 62 { 0x00BEEFFF, 0x000A000C, 0x0 }, 63 { 0x00FFFFFF, 0x0005000F, 0x0 }, 64 { 0x00DB6FFF, 0x000A000C, 0x0 }, 65 }; 66 67 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 68 { 0x00FFFFFF, 0x0007000E, 0x0 }, 69 { 0x00D75FFF, 0x000E000A, 0x0 }, 70 { 0x00BEFFFF, 0x00140006, 0x0 }, 71 { 0x80B2CFFF, 0x001B0002, 0x0 }, 72 { 0x00FFFFFF, 0x000E000A, 0x0 }, 73 { 0x00DB6FFF, 0x00160005, 0x0 }, 74 { 0x80C71FFF, 0x001A0002, 0x0 }, 75 { 0x00F7DFFF, 0x00180004, 0x0 }, 76 { 0x80D75FFF, 0x001B0002, 0x0 }, 77 }; 78 79 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 80 { 0x00FFFFFF, 0x0001000E, 0x0 }, 81 { 0x00D75FFF, 0x0004000A, 0x0 }, 82 { 0x00C30FFF, 0x00070006, 0x0 }, 83 { 0x00AAAFFF, 0x000C0000, 0x0 }, 84 { 0x00FFFFFF, 0x0004000A, 0x0 }, 85 { 0x00D75FFF, 0x00090004, 0x0 }, 86 { 0x00C30FFF, 0x000C0000, 0x0 }, 87 { 0x00FFFFFF, 0x00070006, 0x0 }, 88 { 0x00D75FFF, 0x000C0000, 0x0 }, 89 }; 90 91 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 92 /* Idx NT mV d T mV df db */ 93 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 94 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 95 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 96 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 97 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 98 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 99 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 100 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 101 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 102 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 103 }; 104 105 /* Skylake H and S */ 106 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 107 { 0x00002016, 0x000000A0, 0x0 }, 108 { 0x00005012, 0x0000009B, 0x0 }, 109 { 0x00007011, 0x00000088, 0x0 }, 110 { 0x80009010, 0x000000C0, 0x1 }, 111 { 0x00002016, 0x0000009B, 0x0 }, 112 { 0x00005012, 0x00000088, 0x0 }, 113 { 0x80007011, 0x000000C0, 0x1 }, 114 { 0x00002016, 0x000000DF, 0x0 }, 115 { 0x80005012, 0x000000C0, 0x1 }, 116 }; 117 118 /* Skylake U */ 119 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 120 { 0x0000201B, 0x000000A2, 0x0 }, 121 { 0x00005012, 0x00000088, 0x0 }, 122 { 0x80007011, 0x000000CD, 0x1 }, 123 { 0x80009010, 0x000000C0, 0x1 }, 124 { 0x0000201B, 0x0000009D, 0x0 }, 125 { 0x80005012, 0x000000C0, 0x1 }, 126 { 0x80007011, 0x000000C0, 0x1 }, 127 { 0x00002016, 0x00000088, 0x0 }, 128 { 0x80005012, 0x000000C0, 0x1 }, 129 }; 130 131 /* Skylake Y */ 132 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 133 { 0x00000018, 0x000000A2, 0x0 }, 134 { 0x00005012, 0x00000088, 0x0 }, 135 { 0x80007011, 0x000000CD, 0x3 }, 136 { 0x80009010, 0x000000C0, 0x3 }, 137 { 0x00000018, 0x0000009D, 0x0 }, 138 { 0x80005012, 0x000000C0, 0x3 }, 139 { 0x80007011, 0x000000C0, 0x3 }, 140 { 0x00000018, 0x00000088, 0x0 }, 141 { 0x80005012, 0x000000C0, 0x3 }, 142 }; 143 144 /* Kabylake H and S */ 145 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 146 { 0x00002016, 0x000000A0, 0x0 }, 147 { 0x00005012, 0x0000009B, 0x0 }, 148 { 0x00007011, 0x00000088, 0x0 }, 149 { 0x80009010, 0x000000C0, 0x1 }, 150 { 0x00002016, 0x0000009B, 0x0 }, 151 { 0x00005012, 0x00000088, 0x0 }, 152 { 0x80007011, 0x000000C0, 0x1 }, 153 { 0x00002016, 0x00000097, 0x0 }, 154 { 0x80005012, 0x000000C0, 0x1 }, 155 }; 156 157 /* Kabylake U */ 158 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 159 { 0x0000201B, 0x000000A1, 0x0 }, 160 { 0x00005012, 0x00000088, 0x0 }, 161 { 0x80007011, 0x000000CD, 0x3 }, 162 { 0x80009010, 0x000000C0, 0x3 }, 163 { 0x0000201B, 0x0000009D, 0x0 }, 164 { 0x80005012, 0x000000C0, 0x3 }, 165 { 0x80007011, 0x000000C0, 0x3 }, 166 { 0x00002016, 0x0000004F, 0x0 }, 167 { 0x80005012, 0x000000C0, 0x3 }, 168 }; 169 170 /* Kabylake Y */ 171 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 172 { 0x00001017, 0x000000A1, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000CD, 0x3 }, 175 { 0x8000800F, 0x000000C0, 0x3 }, 176 { 0x00001017, 0x0000009D, 0x0 }, 177 { 0x80005012, 0x000000C0, 0x3 }, 178 { 0x80007011, 0x000000C0, 0x3 }, 179 { 0x00001017, 0x0000004C, 0x0 }, 180 { 0x80005012, 0x000000C0, 0x3 }, 181 }; 182 183 /* 184 * Skylake/Kabylake H and S 185 * eDP 1.4 low vswing translation parameters 186 */ 187 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 188 { 0x00000018, 0x000000A8, 0x0 }, 189 { 0x00004013, 0x000000A9, 0x0 }, 190 { 0x00007011, 0x000000A2, 0x0 }, 191 { 0x00009010, 0x0000009C, 0x0 }, 192 { 0x00000018, 0x000000A9, 0x0 }, 193 { 0x00006013, 0x000000A2, 0x0 }, 194 { 0x00007011, 0x000000A6, 0x0 }, 195 { 0x00000018, 0x000000AB, 0x0 }, 196 { 0x00007013, 0x0000009F, 0x0 }, 197 { 0x00000018, 0x000000DF, 0x0 }, 198 }; 199 200 /* 201 * Skylake/Kabylake U 202 * eDP 1.4 low vswing translation parameters 203 */ 204 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 205 { 0x00000018, 0x000000A8, 0x0 }, 206 { 0x00004013, 0x000000A9, 0x0 }, 207 { 0x00007011, 0x000000A2, 0x0 }, 208 { 0x00009010, 0x0000009C, 0x0 }, 209 { 0x00000018, 0x000000A9, 0x0 }, 210 { 0x00006013, 0x000000A2, 0x0 }, 211 { 0x00007011, 0x000000A6, 0x0 }, 212 { 0x00002016, 0x000000AB, 0x0 }, 213 { 0x00005013, 0x0000009F, 0x0 }, 214 { 0x00000018, 0x000000DF, 0x0 }, 215 }; 216 217 /* 218 * Skylake/Kabylake Y 219 * eDP 1.4 low vswing translation parameters 220 */ 221 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 222 { 0x00000018, 0x000000A8, 0x0 }, 223 { 0x00004013, 0x000000AB, 0x0 }, 224 { 0x00007011, 0x000000A4, 0x0 }, 225 { 0x00009010, 0x000000DF, 0x0 }, 226 { 0x00000018, 0x000000AA, 0x0 }, 227 { 0x00006013, 0x000000A4, 0x0 }, 228 { 0x00007011, 0x0000009D, 0x0 }, 229 { 0x00000018, 0x000000A0, 0x0 }, 230 { 0x00006012, 0x000000DF, 0x0 }, 231 { 0x00000018, 0x0000008A, 0x0 }, 232 }; 233 234 /* Skylake/Kabylake U, H and S */ 235 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 236 { 0x00000018, 0x000000AC, 0x0 }, 237 { 0x00005012, 0x0000009D, 0x0 }, 238 { 0x00007011, 0x00000088, 0x0 }, 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00000018, 0x00000098, 0x0 }, 241 { 0x00004013, 0x00000088, 0x0 }, 242 { 0x80006012, 0x000000CD, 0x1 }, 243 { 0x00000018, 0x000000DF, 0x0 }, 244 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 245 { 0x80003015, 0x000000C0, 0x1 }, 246 { 0x80000018, 0x000000C0, 0x1 }, 247 }; 248 249 /* Skylake/Kabylake Y */ 250 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 251 { 0x00000018, 0x000000A1, 0x0 }, 252 { 0x00005012, 0x000000DF, 0x0 }, 253 { 0x80007011, 0x000000CB, 0x3 }, 254 { 0x00000018, 0x000000A4, 0x0 }, 255 { 0x00000018, 0x0000009D, 0x0 }, 256 { 0x00004013, 0x00000080, 0x0 }, 257 { 0x80006013, 0x000000C0, 0x3 }, 258 { 0x00000018, 0x0000008A, 0x0 }, 259 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 260 { 0x80003015, 0x000000C0, 0x3 }, 261 { 0x80000018, 0x000000C0, 0x3 }, 262 }; 263 264 265 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 266 /* Idx NT mV diff db */ 267 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 268 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 269 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 270 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 271 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 272 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 273 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 274 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 275 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 276 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 277 }; 278 279 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 280 /* Idx NT mV diff db */ 281 { 26, 0, 0, 128, }, /* 0: 200 0 */ 282 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 283 { 48, 0, 0, 96, }, /* 2: 200 4 */ 284 { 54, 0, 0, 69, }, /* 3: 200 6 */ 285 { 32, 0, 0, 128, }, /* 4: 250 0 */ 286 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 287 { 54, 0, 0, 85, }, /* 6: 250 4 */ 288 { 43, 0, 0, 128, }, /* 7: 300 0 */ 289 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 290 { 48, 0, 0, 128, }, /* 9: 300 0 */ 291 }; 292 293 /* BSpec has 2 recommended values - entries 0 and 8. 294 * Using the entry with higher vswing. 295 */ 296 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 297 /* Idx NT mV diff db */ 298 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 299 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 300 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 301 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 302 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 303 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 304 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 305 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 306 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 307 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 308 }; 309 310 /* Voltage Swing Programming for VccIO 0.85V for DP */ 311 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 312 /* NT mV Trans mV db */ 313 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 314 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 315 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 316 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 317 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 318 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 319 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 320 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 321 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 322 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 323 }; 324 325 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 326 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 327 /* NT mV Trans mV db */ 328 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 329 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 330 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 331 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 332 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 333 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 334 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 335 }; 336 337 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 338 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 339 /* NT mV Trans mV db */ 340 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 341 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 342 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 343 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 344 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 345 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 346 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 347 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 348 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 349 }; 350 351 /* Voltage Swing Programming for VccIO 0.95V for DP */ 352 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 353 /* NT mV Trans mV db */ 354 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 355 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 356 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 357 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 358 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 359 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 360 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 361 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 362 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 363 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 364 }; 365 366 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 367 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 368 /* NT mV Trans mV db */ 369 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 370 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 371 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 372 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 373 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 374 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 375 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 376 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 377 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 378 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 379 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 380 }; 381 382 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 383 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 384 /* NT mV Trans mV db */ 385 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 386 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 387 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 388 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 389 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 390 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 391 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 392 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 393 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 394 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 395 }; 396 397 /* Voltage Swing Programming for VccIO 1.05V for DP */ 398 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 399 /* NT mV Trans mV db */ 400 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 401 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 402 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 403 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 404 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 405 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 406 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 407 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 408 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 409 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 410 }; 411 412 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 416 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 417 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 418 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 419 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 420 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 421 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 422 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 423 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 424 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 425 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 426 }; 427 428 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 429 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 430 /* NT mV Trans mV db */ 431 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 432 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 433 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 434 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 435 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 436 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 437 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 438 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 439 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 440 }; 441 442 /* icl_combo_phy_ddi_translations */ 443 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 444 /* NT mV Trans mV db */ 445 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 446 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 447 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 448 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 449 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 450 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 451 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 452 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 453 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 455 }; 456 457 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 458 /* NT mV Trans mV db */ 459 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 460 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 461 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 462 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 463 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 464 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 465 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 466 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 467 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 468 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 469 }; 470 471 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 472 /* NT mV Trans mV db */ 473 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 474 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 475 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 476 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 477 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 478 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 479 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 480 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 481 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 482 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 483 }; 484 485 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 486 /* NT mV Trans mV db */ 487 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 488 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 489 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 490 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 491 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 492 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 493 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 494 }; 495 496 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 497 /* NT mV Trans mV db */ 498 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 499 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 500 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ 501 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ 502 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 503 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 504 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 505 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 506 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ 507 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 508 }; 509 510 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { 511 /* NT mV Trans mV db */ 512 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 513 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 514 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 515 { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ 516 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 517 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 518 { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 519 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 520 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 521 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 522 }; 523 524 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { 525 /* NT mV Trans mV db */ 526 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 527 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ 528 { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ 529 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ 530 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 531 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ 532 { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ 533 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 534 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 535 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 536 }; 537 538 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { 539 /* NT mV Trans mV db */ 540 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 541 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 542 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 543 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 544 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 545 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 546 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 547 { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 548 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 549 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 550 }; 551 552 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 553 /* NT mV Trans mV db */ 554 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 555 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 556 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 557 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 558 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 559 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 560 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 561 { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 562 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 563 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 564 }; 565 566 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 567 /* Voltage swing pre-emphasis */ 568 { 0x18, 0x00, 0x00 }, /* 0 0 */ 569 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 570 { 0x24, 0x00, 0x0C }, /* 0 2 */ 571 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 572 { 0x21, 0x00, 0x00 }, /* 1 0 */ 573 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 574 { 0x30, 0x00, 0x0F }, /* 1 2 */ 575 { 0x31, 0x00, 0x03 }, /* 2 0 */ 576 { 0x34, 0x00, 0x0B }, /* 2 1 */ 577 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 578 }; 579 580 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 581 /* Voltage swing pre-emphasis */ 582 { 0x18, 0x00, 0x00 }, /* 0 0 */ 583 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 584 { 0x24, 0x00, 0x0C }, /* 0 2 */ 585 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 586 { 0x26, 0x00, 0x00 }, /* 1 0 */ 587 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 588 { 0x33, 0x00, 0x0C }, /* 1 2 */ 589 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 590 { 0x36, 0x00, 0x09 }, /* 2 1 */ 591 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 592 }; 593 594 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 595 /* HDMI Preset VS Pre-emph */ 596 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 597 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 598 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 599 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 600 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 601 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 602 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 603 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 604 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 605 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 606 }; 607 608 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 609 /* VS pre-emp Non-trans mV Pre-emph dB */ 610 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 611 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 612 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 613 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 614 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 615 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 616 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 617 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 618 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 619 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 620 }; 621 622 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 623 /* VS pre-emp Non-trans mV Pre-emph dB */ 624 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 625 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 626 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 627 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 628 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 629 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 630 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 631 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 632 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 633 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 634 }; 635 636 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 637 /* HDMI Preset VS Pre-emph */ 638 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 639 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 640 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 641 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 642 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 643 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 644 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 645 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 646 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 647 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 648 }; 649 650 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 651 /* NT mV Trans mV db */ 652 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 653 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 654 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 655 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 656 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 657 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 658 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 659 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 660 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 661 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 662 }; 663 664 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 665 /* NT mV Trans mV db */ 666 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 667 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 668 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 669 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 670 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 671 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 672 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 673 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 674 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 675 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 676 }; 677 678 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 679 /* NT mV Trans mV db */ 680 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 681 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 682 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 683 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 684 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 685 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 686 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 687 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 688 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 689 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 690 }; 691 692 /* 693 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 694 * that DisplayPort specification requires 695 */ 696 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 697 /* VS pre-emp */ 698 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ 699 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ 700 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ 701 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ 702 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ 703 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ 704 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ 705 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ 707 }; 708 709 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = { 710 /* NT mV Trans mV db */ 711 { 0xA, 0x2F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 712 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 713 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 714 { 0x6, 0x7D, 0x2A, 0x00, 0x15 }, /* 350 900 8.2 */ 715 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 716 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 717 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 718 { 0xC, 0x6E, 0x3E, 0x00, 0x01 }, /* 650 700 0.6 */ 719 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 720 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 721 }; 722 723 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 724 /* NT mV Trans mV db */ 725 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 726 { 0xA, 0x50, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 727 { 0xC, 0x61, 0x33, 0x00, 0x0C }, /* 350 700 6.0 */ 728 { 0x6, 0x7F, 0x2E, 0x00, 0x11 }, /* 350 900 8.2 */ 729 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 730 { 0xC, 0x5F, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 731 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 732 { 0xC, 0x5F, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 733 { 0x6, 0x7E, 0x36, 0x00, 0x09 }, /* 600 900 3.5 */ 734 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 735 }; 736 737 bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) 738 { 739 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 740 } 741 742 static const struct ddi_buf_trans * 743 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 744 { 745 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 746 747 if (dev_priv->vbt.edp.low_vswing) { 748 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 749 return bdw_ddi_translations_edp; 750 } else { 751 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 752 return bdw_ddi_translations_dp; 753 } 754 } 755 756 static const struct ddi_buf_trans * 757 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 758 { 759 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 760 761 if (IS_SKL_ULX(dev_priv)) { 762 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 763 return skl_y_ddi_translations_dp; 764 } else if (IS_SKL_ULT(dev_priv)) { 765 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 766 return skl_u_ddi_translations_dp; 767 } else { 768 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 769 return skl_ddi_translations_dp; 770 } 771 } 772 773 static const struct ddi_buf_trans * 774 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 775 { 776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 777 778 if (IS_KBL_ULX(dev_priv) || 779 IS_CFL_ULX(dev_priv) || 780 IS_CML_ULX(dev_priv)) { 781 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 782 return kbl_y_ddi_translations_dp; 783 } else if (IS_KBL_ULT(dev_priv) || 784 IS_CFL_ULT(dev_priv) || 785 IS_CML_ULT(dev_priv)) { 786 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 787 return kbl_u_ddi_translations_dp; 788 } else { 789 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 790 return kbl_ddi_translations_dp; 791 } 792 } 793 794 static const struct ddi_buf_trans * 795 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 796 { 797 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 798 799 if (dev_priv->vbt.edp.low_vswing) { 800 if (IS_SKL_ULX(dev_priv) || 801 IS_KBL_ULX(dev_priv) || 802 IS_CFL_ULX(dev_priv) || 803 IS_CML_ULX(dev_priv)) { 804 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 805 return skl_y_ddi_translations_edp; 806 } else if (IS_SKL_ULT(dev_priv) || 807 IS_KBL_ULT(dev_priv) || 808 IS_CFL_ULT(dev_priv) || 809 IS_CML_ULT(dev_priv)) { 810 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 811 return skl_u_ddi_translations_edp; 812 } else { 813 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 814 return skl_ddi_translations_edp; 815 } 816 } 817 818 if (IS_KABYLAKE(dev_priv) || 819 IS_COFFEELAKE(dev_priv) || 820 IS_COMETLAKE(dev_priv)) 821 return kbl_get_buf_trans_dp(encoder, n_entries); 822 else 823 return skl_get_buf_trans_dp(encoder, n_entries); 824 } 825 826 static const struct ddi_buf_trans * 827 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 828 { 829 if (IS_SKL_ULX(dev_priv) || 830 IS_KBL_ULX(dev_priv) || 831 IS_CFL_ULX(dev_priv) || 832 IS_CML_ULX(dev_priv)) { 833 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 834 return skl_y_ddi_translations_hdmi; 835 } else { 836 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 837 return skl_ddi_translations_hdmi; 838 } 839 } 840 841 static int skl_buf_trans_num_entries(enum port port, int n_entries) 842 { 843 /* Only DDIA and DDIE can select the 10th register with DP */ 844 if (port == PORT_A || port == PORT_E) 845 return min(n_entries, 10); 846 else 847 return min(n_entries, 9); 848 } 849 850 const struct ddi_buf_trans * 851 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 852 { 853 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 854 855 if (IS_KABYLAKE(dev_priv) || 856 IS_COFFEELAKE(dev_priv) || 857 IS_COMETLAKE(dev_priv)) { 858 const struct ddi_buf_trans *ddi_translations = 859 kbl_get_buf_trans_dp(encoder, n_entries); 860 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 861 return ddi_translations; 862 } else if (IS_SKYLAKE(dev_priv)) { 863 const struct ddi_buf_trans *ddi_translations = 864 skl_get_buf_trans_dp(encoder, n_entries); 865 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 866 return ddi_translations; 867 } else if (IS_BROADWELL(dev_priv)) { 868 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 869 return bdw_ddi_translations_dp; 870 } else if (IS_HASWELL(dev_priv)) { 871 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 872 return hsw_ddi_translations_dp; 873 } 874 875 *n_entries = 0; 876 return NULL; 877 } 878 879 const struct ddi_buf_trans * 880 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 881 { 882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 883 884 if (IS_GEN9_BC(dev_priv)) { 885 const struct ddi_buf_trans *ddi_translations = 886 skl_get_buf_trans_edp(encoder, n_entries); 887 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 888 return ddi_translations; 889 } else if (IS_BROADWELL(dev_priv)) { 890 return bdw_get_buf_trans_edp(encoder, n_entries); 891 } else if (IS_HASWELL(dev_priv)) { 892 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 893 return hsw_ddi_translations_dp; 894 } 895 896 *n_entries = 0; 897 return NULL; 898 } 899 900 const struct ddi_buf_trans * 901 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 902 int *n_entries) 903 { 904 if (IS_BROADWELL(dev_priv)) { 905 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 906 return bdw_ddi_translations_fdi; 907 } else if (IS_HASWELL(dev_priv)) { 908 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 909 return hsw_ddi_translations_fdi; 910 } 911 912 *n_entries = 0; 913 return NULL; 914 } 915 916 const struct ddi_buf_trans * 917 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 918 int *n_entries) 919 { 920 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 921 922 if (IS_GEN9_BC(dev_priv)) { 923 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 924 } else if (IS_BROADWELL(dev_priv)) { 925 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 926 return bdw_ddi_translations_hdmi; 927 } else if (IS_HASWELL(dev_priv)) { 928 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 929 return hsw_ddi_translations_hdmi; 930 } 931 932 *n_entries = 0; 933 return NULL; 934 } 935 936 static const struct bxt_ddi_buf_trans * 937 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 938 { 939 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 940 return bxt_ddi_translations_dp; 941 } 942 943 static const struct bxt_ddi_buf_trans * 944 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 945 { 946 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 947 948 if (dev_priv->vbt.edp.low_vswing) { 949 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 950 return bxt_ddi_translations_edp; 951 } 952 953 return bxt_get_buf_trans_dp(encoder, n_entries); 954 } 955 956 static const struct bxt_ddi_buf_trans * 957 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 958 { 959 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 960 return bxt_ddi_translations_hdmi; 961 } 962 963 const struct bxt_ddi_buf_trans * 964 bxt_get_buf_trans(struct intel_encoder *encoder, 965 const struct intel_crtc_state *crtc_state, 966 int *n_entries) 967 { 968 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 969 return bxt_get_buf_trans_hdmi(encoder, n_entries); 970 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 971 return bxt_get_buf_trans_edp(encoder, n_entries); 972 return bxt_get_buf_trans_dp(encoder, n_entries); 973 } 974 975 static const struct cnl_ddi_buf_trans * 976 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 977 { 978 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 979 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 980 981 if (voltage == VOLTAGE_INFO_0_85V) { 982 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 983 return cnl_ddi_translations_hdmi_0_85V; 984 } else if (voltage == VOLTAGE_INFO_0_95V) { 985 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 986 return cnl_ddi_translations_hdmi_0_95V; 987 } else if (voltage == VOLTAGE_INFO_1_05V) { 988 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 989 return cnl_ddi_translations_hdmi_1_05V; 990 } else { 991 *n_entries = 1; /* shut up gcc */ 992 MISSING_CASE(voltage); 993 } 994 return NULL; 995 } 996 997 static const struct cnl_ddi_buf_trans * 998 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 999 { 1000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1001 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1002 1003 if (voltage == VOLTAGE_INFO_0_85V) { 1004 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 1005 return cnl_ddi_translations_dp_0_85V; 1006 } else if (voltage == VOLTAGE_INFO_0_95V) { 1007 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 1008 return cnl_ddi_translations_dp_0_95V; 1009 } else if (voltage == VOLTAGE_INFO_1_05V) { 1010 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 1011 return cnl_ddi_translations_dp_1_05V; 1012 } else { 1013 *n_entries = 1; /* shut up gcc */ 1014 MISSING_CASE(voltage); 1015 } 1016 return NULL; 1017 } 1018 1019 static const struct cnl_ddi_buf_trans * 1020 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1021 { 1022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1023 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1024 1025 if (dev_priv->vbt.edp.low_vswing) { 1026 if (voltage == VOLTAGE_INFO_0_85V) { 1027 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 1028 return cnl_ddi_translations_edp_0_85V; 1029 } else if (voltage == VOLTAGE_INFO_0_95V) { 1030 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 1031 return cnl_ddi_translations_edp_0_95V; 1032 } else if (voltage == VOLTAGE_INFO_1_05V) { 1033 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 1034 return cnl_ddi_translations_edp_1_05V; 1035 } else { 1036 *n_entries = 1; /* shut up gcc */ 1037 MISSING_CASE(voltage); 1038 } 1039 return NULL; 1040 } else { 1041 return cnl_get_buf_trans_dp(encoder, n_entries); 1042 } 1043 } 1044 1045 const struct cnl_ddi_buf_trans * 1046 cnl_get_buf_trans(struct intel_encoder *encoder, 1047 const struct intel_crtc_state *crtc_state, 1048 int *n_entries) 1049 { 1050 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1051 return cnl_get_buf_trans_hdmi(encoder, n_entries); 1052 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1053 return cnl_get_buf_trans_edp(encoder, n_entries); 1054 return cnl_get_buf_trans_dp(encoder, n_entries); 1055 } 1056 1057 static const struct cnl_ddi_buf_trans * 1058 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1059 const struct intel_crtc_state *crtc_state, 1060 int *n_entries) 1061 { 1062 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1063 return icl_combo_phy_ddi_translations_hdmi; 1064 } 1065 1066 static const struct cnl_ddi_buf_trans * 1067 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1068 const struct intel_crtc_state *crtc_state, 1069 int *n_entries) 1070 { 1071 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1072 return icl_combo_phy_ddi_translations_dp_hbr2; 1073 } 1074 1075 static const struct cnl_ddi_buf_trans * 1076 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1077 const struct intel_crtc_state *crtc_state, 1078 int *n_entries) 1079 { 1080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1081 1082 if (crtc_state->port_clock > 540000) { 1083 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1084 return icl_combo_phy_ddi_translations_edp_hbr3; 1085 } else if (dev_priv->vbt.edp.low_vswing) { 1086 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1087 return icl_combo_phy_ddi_translations_edp_hbr2; 1088 } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { 1089 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3); 1090 return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3; 1091 } else if (IS_DG1(dev_priv)) { 1092 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr); 1093 return dg1_combo_phy_ddi_translations_dp_rbr_hbr; 1094 } 1095 1096 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1097 } 1098 1099 const struct cnl_ddi_buf_trans * 1100 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1101 const struct intel_crtc_state *crtc_state, 1102 int *n_entries) 1103 { 1104 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1105 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1106 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1107 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1108 else 1109 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1110 } 1111 1112 static const struct icl_mg_phy_ddi_buf_trans * 1113 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, 1114 const struct intel_crtc_state *crtc_state, 1115 int *n_entries) 1116 { 1117 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1118 return icl_mg_phy_ddi_translations_hdmi; 1119 } 1120 1121 static const struct icl_mg_phy_ddi_buf_trans * 1122 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1123 const struct intel_crtc_state *crtc_state, 1124 int *n_entries) 1125 { 1126 if (crtc_state->port_clock > 270000) { 1127 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1128 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1129 } else { 1130 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1131 return icl_mg_phy_ddi_translations_rbr_hbr; 1132 } 1133 } 1134 1135 const struct icl_mg_phy_ddi_buf_trans * 1136 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1137 const struct intel_crtc_state *crtc_state, 1138 int *n_entries) 1139 { 1140 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1141 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries); 1142 else 1143 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1144 } 1145 1146 static const struct cnl_ddi_buf_trans * 1147 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1148 const struct intel_crtc_state *crtc_state, 1149 int *n_entries) 1150 { 1151 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1152 return icl_combo_phy_ddi_translations_hdmi; 1153 } 1154 1155 static const struct cnl_ddi_buf_trans * 1156 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1157 const struct intel_crtc_state *crtc_state, 1158 int *n_entries) 1159 { 1160 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1161 return ehl_combo_phy_ddi_translations_dp; 1162 } 1163 1164 static const struct cnl_ddi_buf_trans * 1165 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state, 1167 int *n_entries) 1168 { 1169 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1170 1171 if (dev_priv->vbt.edp.low_vswing) { 1172 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1173 return icl_combo_phy_ddi_translations_edp_hbr2; 1174 } 1175 1176 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1177 } 1178 1179 const struct cnl_ddi_buf_trans * 1180 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1181 const struct intel_crtc_state *crtc_state, 1182 int *n_entries) 1183 { 1184 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1185 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1186 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1187 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1188 else 1189 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1190 } 1191 1192 static const struct cnl_ddi_buf_trans * 1193 jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1194 const struct intel_crtc_state *crtc_state, 1195 int *n_entries) 1196 { 1197 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1198 return icl_combo_phy_ddi_translations_hdmi; 1199 } 1200 1201 static const struct cnl_ddi_buf_trans * 1202 jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1203 const struct intel_crtc_state *crtc_state, 1204 int *n_entries) 1205 { 1206 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1207 return icl_combo_phy_ddi_translations_dp_hbr2; 1208 } 1209 1210 static const struct cnl_ddi_buf_trans * 1211 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1212 const struct intel_crtc_state *crtc_state, 1213 int *n_entries) 1214 { 1215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1216 1217 if (dev_priv->vbt.edp.low_vswing) { 1218 if (crtc_state->port_clock > 270000) { 1219 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); 1220 return jsl_combo_phy_ddi_translations_edp_hbr2; 1221 } else { 1222 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); 1223 return jsl_combo_phy_ddi_translations_edp_hbr; 1224 } 1225 } 1226 1227 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1228 } 1229 1230 const struct cnl_ddi_buf_trans * 1231 jsl_get_combo_buf_trans(struct intel_encoder *encoder, 1232 const struct intel_crtc_state *crtc_state, 1233 int *n_entries) 1234 { 1235 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1236 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1237 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1238 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1239 else 1240 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1241 } 1242 1243 static const struct cnl_ddi_buf_trans * 1244 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1245 const struct intel_crtc_state *crtc_state, 1246 int *n_entries) 1247 { 1248 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1249 return icl_combo_phy_ddi_translations_hdmi; 1250 } 1251 1252 static const struct cnl_ddi_buf_trans * 1253 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1254 const struct intel_crtc_state *crtc_state, 1255 int *n_entries) 1256 { 1257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1258 1259 if (crtc_state->port_clock > 270000) { 1260 if (IS_ROCKETLAKE(dev_priv)) { 1261 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3); 1262 return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3; 1263 } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1264 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); 1265 return tgl_uy_combo_phy_ddi_translations_dp_hbr2; 1266 } else { 1267 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1268 return tgl_combo_phy_ddi_translations_dp_hbr2; 1269 } 1270 } else { 1271 if (IS_ROCKETLAKE(dev_priv)) { 1272 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr); 1273 return rkl_combo_phy_ddi_translations_dp_hbr; 1274 } else { 1275 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1276 return tgl_combo_phy_ddi_translations_dp_hbr; 1277 } 1278 } 1279 } 1280 1281 static const struct cnl_ddi_buf_trans * 1282 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1283 const struct intel_crtc_state *crtc_state, 1284 int *n_entries) 1285 { 1286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1287 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1288 1289 if (crtc_state->port_clock > 540000) { 1290 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1291 return icl_combo_phy_ddi_translations_edp_hbr3; 1292 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1293 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); 1294 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1295 } else if (dev_priv->vbt.edp.low_vswing) { 1296 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1297 return icl_combo_phy_ddi_translations_edp_hbr2; 1298 } 1299 1300 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1301 } 1302 1303 const struct cnl_ddi_buf_trans * 1304 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1305 const struct intel_crtc_state *crtc_state, 1306 int *n_entries) 1307 { 1308 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1309 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1310 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1311 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1312 else 1313 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1314 } 1315 1316 static const struct tgl_dkl_phy_ddi_buf_trans * 1317 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, 1318 const struct intel_crtc_state *crtc_state, 1319 int *n_entries) 1320 { 1321 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1322 return tgl_dkl_phy_hdmi_ddi_trans; 1323 } 1324 1325 static const struct tgl_dkl_phy_ddi_buf_trans * 1326 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1327 const struct intel_crtc_state *crtc_state, 1328 int *n_entries) 1329 { 1330 if (crtc_state->port_clock > 270000) { 1331 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1332 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1333 } else { 1334 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1335 return tgl_dkl_phy_dp_ddi_trans; 1336 } 1337 } 1338 1339 const struct tgl_dkl_phy_ddi_buf_trans * 1340 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1341 const struct intel_crtc_state *crtc_state, 1342 int *n_entries) 1343 { 1344 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1345 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); 1346 else 1347 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1348 } 1349 1350 int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, 1351 const struct intel_crtc_state *crtc_state, 1352 int *default_entry) 1353 { 1354 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1355 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1356 int n_entries; 1357 1358 if (DISPLAY_VER(dev_priv) >= 12) { 1359 if (intel_phy_is_combo(dev_priv, phy)) 1360 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1361 else 1362 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1363 *default_entry = n_entries - 1; 1364 } else if (IS_DISPLAY_VER(dev_priv, 11)) { 1365 if (intel_phy_is_combo(dev_priv, phy)) 1366 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1367 else 1368 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1369 *default_entry = n_entries - 1; 1370 } else if (IS_CANNONLAKE(dev_priv)) { 1371 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1372 *default_entry = n_entries - 1; 1373 } else if (IS_GEN9_LP(dev_priv)) { 1374 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1375 *default_entry = n_entries - 1; 1376 } else if (IS_GEN9_BC(dev_priv)) { 1377 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1378 *default_entry = 8; 1379 } else if (IS_BROADWELL(dev_priv)) { 1380 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1381 *default_entry = 7; 1382 } else if (IS_HASWELL(dev_priv)) { 1383 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1384 *default_entry = 6; 1385 } else { 1386 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1387 return 0; 1388 } 1389 1390 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1391 return 0; 1392 1393 return n_entries; 1394 } 1395