1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_ddi.h" 8 #include "intel_ddi_buf_trans.h" 9 #include "intel_de.h" 10 #include "intel_display_types.h" 11 12 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 13 * them for both DP and FDI transports, allowing those ports to 14 * automatically adapt to HDMI connections as well 15 */ 16 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 17 { 0x00FFFFFF, 0x0006000E, 0x0 }, 18 { 0x00D75FFF, 0x0005000A, 0x0 }, 19 { 0x00C30FFF, 0x00040006, 0x0 }, 20 { 0x80AAAFFF, 0x000B0000, 0x0 }, 21 { 0x00FFFFFF, 0x0005000A, 0x0 }, 22 { 0x00D75FFF, 0x000C0004, 0x0 }, 23 { 0x80C30FFF, 0x000B0000, 0x0 }, 24 { 0x00FFFFFF, 0x00040006, 0x0 }, 25 { 0x80D75FFF, 0x000B0000, 0x0 }, 26 }; 27 28 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 29 { 0x00FFFFFF, 0x0007000E, 0x0 }, 30 { 0x00D75FFF, 0x000F000A, 0x0 }, 31 { 0x00C30FFF, 0x00060006, 0x0 }, 32 { 0x00AAAFFF, 0x001E0000, 0x0 }, 33 { 0x00FFFFFF, 0x000F000A, 0x0 }, 34 { 0x00D75FFF, 0x00160004, 0x0 }, 35 { 0x00C30FFF, 0x001E0000, 0x0 }, 36 { 0x00FFFFFF, 0x00060006, 0x0 }, 37 { 0x00D75FFF, 0x001E0000, 0x0 }, 38 }; 39 40 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 41 /* Idx NT mV d T mV d db */ 42 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 43 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 44 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 45 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 46 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 47 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 48 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 49 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 50 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 51 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 52 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 53 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 54 }; 55 56 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 57 { 0x00FFFFFF, 0x00000012, 0x0 }, 58 { 0x00EBAFFF, 0x00020011, 0x0 }, 59 { 0x00C71FFF, 0x0006000F, 0x0 }, 60 { 0x00AAAFFF, 0x000E000A, 0x0 }, 61 { 0x00FFFFFF, 0x00020011, 0x0 }, 62 { 0x00DB6FFF, 0x0005000F, 0x0 }, 63 { 0x00BEEFFF, 0x000A000C, 0x0 }, 64 { 0x00FFFFFF, 0x0005000F, 0x0 }, 65 { 0x00DB6FFF, 0x000A000C, 0x0 }, 66 }; 67 68 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 69 { 0x00FFFFFF, 0x0007000E, 0x0 }, 70 { 0x00D75FFF, 0x000E000A, 0x0 }, 71 { 0x00BEFFFF, 0x00140006, 0x0 }, 72 { 0x80B2CFFF, 0x001B0002, 0x0 }, 73 { 0x00FFFFFF, 0x000E000A, 0x0 }, 74 { 0x00DB6FFF, 0x00160005, 0x0 }, 75 { 0x80C71FFF, 0x001A0002, 0x0 }, 76 { 0x00F7DFFF, 0x00180004, 0x0 }, 77 { 0x80D75FFF, 0x001B0002, 0x0 }, 78 }; 79 80 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 81 { 0x00FFFFFF, 0x0001000E, 0x0 }, 82 { 0x00D75FFF, 0x0004000A, 0x0 }, 83 { 0x00C30FFF, 0x00070006, 0x0 }, 84 { 0x00AAAFFF, 0x000C0000, 0x0 }, 85 { 0x00FFFFFF, 0x0004000A, 0x0 }, 86 { 0x00D75FFF, 0x00090004, 0x0 }, 87 { 0x00C30FFF, 0x000C0000, 0x0 }, 88 { 0x00FFFFFF, 0x00070006, 0x0 }, 89 { 0x00D75FFF, 0x000C0000, 0x0 }, 90 }; 91 92 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 93 /* Idx NT mV d T mV df db */ 94 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 95 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 96 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 97 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 98 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 99 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 100 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 101 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 102 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 103 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 104 }; 105 106 /* Skylake H and S */ 107 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 108 { 0x00002016, 0x000000A0, 0x0 }, 109 { 0x00005012, 0x0000009B, 0x0 }, 110 { 0x00007011, 0x00000088, 0x0 }, 111 { 0x80009010, 0x000000C0, 0x1 }, 112 { 0x00002016, 0x0000009B, 0x0 }, 113 { 0x00005012, 0x00000088, 0x0 }, 114 { 0x80007011, 0x000000C0, 0x1 }, 115 { 0x00002016, 0x000000DF, 0x0 }, 116 { 0x80005012, 0x000000C0, 0x1 }, 117 }; 118 119 /* Skylake U */ 120 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 121 { 0x0000201B, 0x000000A2, 0x0 }, 122 { 0x00005012, 0x00000088, 0x0 }, 123 { 0x80007011, 0x000000CD, 0x1 }, 124 { 0x80009010, 0x000000C0, 0x1 }, 125 { 0x0000201B, 0x0000009D, 0x0 }, 126 { 0x80005012, 0x000000C0, 0x1 }, 127 { 0x80007011, 0x000000C0, 0x1 }, 128 { 0x00002016, 0x00000088, 0x0 }, 129 { 0x80005012, 0x000000C0, 0x1 }, 130 }; 131 132 /* Skylake Y */ 133 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 134 { 0x00000018, 0x000000A2, 0x0 }, 135 { 0x00005012, 0x00000088, 0x0 }, 136 { 0x80007011, 0x000000CD, 0x3 }, 137 { 0x80009010, 0x000000C0, 0x3 }, 138 { 0x00000018, 0x0000009D, 0x0 }, 139 { 0x80005012, 0x000000C0, 0x3 }, 140 { 0x80007011, 0x000000C0, 0x3 }, 141 { 0x00000018, 0x00000088, 0x0 }, 142 { 0x80005012, 0x000000C0, 0x3 }, 143 }; 144 145 /* Kabylake H and S */ 146 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 147 { 0x00002016, 0x000000A0, 0x0 }, 148 { 0x00005012, 0x0000009B, 0x0 }, 149 { 0x00007011, 0x00000088, 0x0 }, 150 { 0x80009010, 0x000000C0, 0x1 }, 151 { 0x00002016, 0x0000009B, 0x0 }, 152 { 0x00005012, 0x00000088, 0x0 }, 153 { 0x80007011, 0x000000C0, 0x1 }, 154 { 0x00002016, 0x00000097, 0x0 }, 155 { 0x80005012, 0x000000C0, 0x1 }, 156 }; 157 158 /* Kabylake U */ 159 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 160 { 0x0000201B, 0x000000A1, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x80007011, 0x000000CD, 0x3 }, 163 { 0x80009010, 0x000000C0, 0x3 }, 164 { 0x0000201B, 0x0000009D, 0x0 }, 165 { 0x80005012, 0x000000C0, 0x3 }, 166 { 0x80007011, 0x000000C0, 0x3 }, 167 { 0x00002016, 0x0000004F, 0x0 }, 168 { 0x80005012, 0x000000C0, 0x3 }, 169 }; 170 171 /* Kabylake Y */ 172 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 173 { 0x00001017, 0x000000A1, 0x0 }, 174 { 0x00005012, 0x00000088, 0x0 }, 175 { 0x80007011, 0x000000CD, 0x3 }, 176 { 0x8000800F, 0x000000C0, 0x3 }, 177 { 0x00001017, 0x0000009D, 0x0 }, 178 { 0x80005012, 0x000000C0, 0x3 }, 179 { 0x80007011, 0x000000C0, 0x3 }, 180 { 0x00001017, 0x0000004C, 0x0 }, 181 { 0x80005012, 0x000000C0, 0x3 }, 182 }; 183 184 /* 185 * Skylake/Kabylake H and S 186 * eDP 1.4 low vswing translation parameters 187 */ 188 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 189 { 0x00000018, 0x000000A8, 0x0 }, 190 { 0x00004013, 0x000000A9, 0x0 }, 191 { 0x00007011, 0x000000A2, 0x0 }, 192 { 0x00009010, 0x0000009C, 0x0 }, 193 { 0x00000018, 0x000000A9, 0x0 }, 194 { 0x00006013, 0x000000A2, 0x0 }, 195 { 0x00007011, 0x000000A6, 0x0 }, 196 { 0x00000018, 0x000000AB, 0x0 }, 197 { 0x00007013, 0x0000009F, 0x0 }, 198 { 0x00000018, 0x000000DF, 0x0 }, 199 }; 200 201 /* 202 * Skylake/Kabylake U 203 * eDP 1.4 low vswing translation parameters 204 */ 205 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 206 { 0x00000018, 0x000000A8, 0x0 }, 207 { 0x00004013, 0x000000A9, 0x0 }, 208 { 0x00007011, 0x000000A2, 0x0 }, 209 { 0x00009010, 0x0000009C, 0x0 }, 210 { 0x00000018, 0x000000A9, 0x0 }, 211 { 0x00006013, 0x000000A2, 0x0 }, 212 { 0x00007011, 0x000000A6, 0x0 }, 213 { 0x00002016, 0x000000AB, 0x0 }, 214 { 0x00005013, 0x0000009F, 0x0 }, 215 { 0x00000018, 0x000000DF, 0x0 }, 216 }; 217 218 /* 219 * Skylake/Kabylake Y 220 * eDP 1.4 low vswing translation parameters 221 */ 222 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 223 { 0x00000018, 0x000000A8, 0x0 }, 224 { 0x00004013, 0x000000AB, 0x0 }, 225 { 0x00007011, 0x000000A4, 0x0 }, 226 { 0x00009010, 0x000000DF, 0x0 }, 227 { 0x00000018, 0x000000AA, 0x0 }, 228 { 0x00006013, 0x000000A4, 0x0 }, 229 { 0x00007011, 0x0000009D, 0x0 }, 230 { 0x00000018, 0x000000A0, 0x0 }, 231 { 0x00006012, 0x000000DF, 0x0 }, 232 { 0x00000018, 0x0000008A, 0x0 }, 233 }; 234 235 /* Skylake/Kabylake U, H and S */ 236 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 237 { 0x00000018, 0x000000AC, 0x0 }, 238 { 0x00005012, 0x0000009D, 0x0 }, 239 { 0x00007011, 0x00000088, 0x0 }, 240 { 0x00000018, 0x000000A1, 0x0 }, 241 { 0x00000018, 0x00000098, 0x0 }, 242 { 0x00004013, 0x00000088, 0x0 }, 243 { 0x80006012, 0x000000CD, 0x1 }, 244 { 0x00000018, 0x000000DF, 0x0 }, 245 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 246 { 0x80003015, 0x000000C0, 0x1 }, 247 { 0x80000018, 0x000000C0, 0x1 }, 248 }; 249 250 /* Skylake/Kabylake Y */ 251 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 252 { 0x00000018, 0x000000A1, 0x0 }, 253 { 0x00005012, 0x000000DF, 0x0 }, 254 { 0x80007011, 0x000000CB, 0x3 }, 255 { 0x00000018, 0x000000A4, 0x0 }, 256 { 0x00000018, 0x0000009D, 0x0 }, 257 { 0x00004013, 0x00000080, 0x0 }, 258 { 0x80006013, 0x000000C0, 0x3 }, 259 { 0x00000018, 0x0000008A, 0x0 }, 260 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 261 { 0x80003015, 0x000000C0, 0x3 }, 262 { 0x80000018, 0x000000C0, 0x3 }, 263 }; 264 265 266 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 267 /* Idx NT mV diff db */ 268 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 269 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 270 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 271 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 272 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 273 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 274 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 275 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 276 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 277 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 278 }; 279 280 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 281 /* Idx NT mV diff db */ 282 { 26, 0, 0, 128, }, /* 0: 200 0 */ 283 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 284 { 48, 0, 0, 96, }, /* 2: 200 4 */ 285 { 54, 0, 0, 69, }, /* 3: 200 6 */ 286 { 32, 0, 0, 128, }, /* 4: 250 0 */ 287 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 288 { 54, 0, 0, 85, }, /* 6: 250 4 */ 289 { 43, 0, 0, 128, }, /* 7: 300 0 */ 290 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 291 { 48, 0, 0, 128, }, /* 9: 300 0 */ 292 }; 293 294 /* BSpec has 2 recommended values - entries 0 and 8. 295 * Using the entry with higher vswing. 296 */ 297 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 298 /* Idx NT mV diff db */ 299 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 300 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 301 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 302 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 303 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 304 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 305 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 306 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 307 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 308 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 309 }; 310 311 /* Voltage Swing Programming for VccIO 0.85V for DP */ 312 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 313 /* NT mV Trans mV db */ 314 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 315 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 316 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 317 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 318 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 319 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 320 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 321 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 322 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 323 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 324 }; 325 326 /* Voltage Swing Programming for VccIO 0.85V for HDMI */ 327 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 328 /* NT mV Trans mV db */ 329 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 330 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 331 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 332 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 333 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 334 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 335 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 336 }; 337 338 /* Voltage Swing Programming for VccIO 0.85V for eDP */ 339 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 340 /* NT mV Trans mV db */ 341 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 342 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 343 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 344 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 345 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 346 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 347 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 348 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 349 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 350 }; 351 352 /* Voltage Swing Programming for VccIO 0.95V for DP */ 353 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 354 /* NT mV Trans mV db */ 355 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 356 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 357 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 358 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 359 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 360 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 361 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 362 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 363 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 364 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 365 }; 366 367 /* Voltage Swing Programming for VccIO 0.95V for HDMI */ 368 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 369 /* NT mV Trans mV db */ 370 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 371 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 372 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 373 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 374 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 375 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 376 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 377 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 378 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 379 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 380 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 381 }; 382 383 /* Voltage Swing Programming for VccIO 0.95V for eDP */ 384 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 385 /* NT mV Trans mV db */ 386 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 387 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 388 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 389 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 390 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 391 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 392 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 393 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 394 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 395 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 396 }; 397 398 /* Voltage Swing Programming for VccIO 1.05V for DP */ 399 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 400 /* NT mV Trans mV db */ 401 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 402 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 403 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 404 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 405 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 406 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 407 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 408 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 409 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 410 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 411 }; 412 413 /* Voltage Swing Programming for VccIO 1.05V for HDMI */ 414 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 415 /* NT mV Trans mV db */ 416 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 417 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 418 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 419 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 420 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 421 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 422 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 423 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 424 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 425 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 426 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 427 }; 428 429 /* Voltage Swing Programming for VccIO 1.05V for eDP */ 430 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 431 /* NT mV Trans mV db */ 432 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 433 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 434 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 435 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 436 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 437 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 438 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 439 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 440 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 441 }; 442 443 /* icl_combo_phy_ddi_translations */ 444 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 445 /* NT mV Trans mV db */ 446 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 447 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 448 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 449 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 450 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 451 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 452 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 453 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 454 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 455 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 456 }; 457 458 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 459 /* NT mV Trans mV db */ 460 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 461 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 462 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 463 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 464 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 465 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 466 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 467 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 468 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 469 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 470 }; 471 472 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 473 /* NT mV Trans mV db */ 474 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 475 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 476 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 477 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 478 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 479 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 480 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 481 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 482 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 483 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 484 }; 485 486 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 487 /* NT mV Trans mV db */ 488 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 489 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 490 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 491 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 492 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 493 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 494 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 495 }; 496 497 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 498 /* NT mV Trans mV db */ 499 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 500 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 501 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ 502 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ 503 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 504 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 505 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 506 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 507 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ 508 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 509 }; 510 511 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = { 512 /* NT mV Trans mV db */ 513 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 514 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 515 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 516 { 0xA, 0x35, 0x36, 0x00, 0x09 }, /* 200 350 4.9 */ 517 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 518 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 519 { 0xA, 0x35, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 520 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 521 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 522 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 523 }; 524 525 static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = { 526 /* NT mV Trans mV db */ 527 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 528 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 250 1.9 */ 529 { 0x1, 0x7F, 0x3D, 0x00, 0x02 }, /* 200 300 3.5 */ 530 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 200 350 4.9 */ 531 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 532 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 300 1.6 */ 533 { 0xA, 0x35, 0x3A, 0x00, 0x05 }, /* 250 350 2.9 */ 534 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 535 { 0xA, 0x35, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 536 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 537 }; 538 539 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_rbr_hbr[] = { 540 /* NT mV Trans mV db */ 541 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 542 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 543 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 544 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 545 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 546 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 547 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 548 { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 549 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ 550 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 551 }; 552 553 static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 554 /* NT mV Trans mV db */ 555 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 556 { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ 557 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 558 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ 559 { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 560 { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 561 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 562 { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 563 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 564 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 565 }; 566 567 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 568 /* Voltage swing pre-emphasis */ 569 { 0x18, 0x00, 0x00 }, /* 0 0 */ 570 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 571 { 0x24, 0x00, 0x0C }, /* 0 2 */ 572 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 573 { 0x21, 0x00, 0x00 }, /* 1 0 */ 574 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 575 { 0x30, 0x00, 0x0F }, /* 1 2 */ 576 { 0x31, 0x00, 0x03 }, /* 2 0 */ 577 { 0x34, 0x00, 0x0B }, /* 2 1 */ 578 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 579 }; 580 581 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 582 /* Voltage swing pre-emphasis */ 583 { 0x18, 0x00, 0x00 }, /* 0 0 */ 584 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 585 { 0x24, 0x00, 0x0C }, /* 0 2 */ 586 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 587 { 0x26, 0x00, 0x00 }, /* 1 0 */ 588 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 589 { 0x33, 0x00, 0x0C }, /* 1 2 */ 590 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 591 { 0x36, 0x00, 0x09 }, /* 2 1 */ 592 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 593 }; 594 595 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 596 /* HDMI Preset VS Pre-emph */ 597 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 598 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 599 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 600 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 601 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 602 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 603 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 604 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 605 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 606 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 607 }; 608 609 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 610 /* VS pre-emp Non-trans mV Pre-emph dB */ 611 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 612 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 613 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 614 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 615 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 616 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 617 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 618 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 619 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 620 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 621 }; 622 623 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 624 /* VS pre-emp Non-trans mV Pre-emph dB */ 625 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 626 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 627 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 628 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 629 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 630 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 631 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 632 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 633 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 634 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 635 }; 636 637 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 638 /* HDMI Preset VS Pre-emph */ 639 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 640 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 641 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 642 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 643 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 644 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 645 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 646 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 647 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 648 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 649 }; 650 651 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 652 /* NT mV Trans mV db */ 653 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 654 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 655 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 656 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 657 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 658 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 659 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 660 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 661 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 662 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 663 }; 664 665 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 666 /* NT mV Trans mV db */ 667 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 668 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 669 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 670 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 671 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 672 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 673 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 674 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 675 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 676 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 677 }; 678 679 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 680 /* NT mV Trans mV db */ 681 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 682 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 683 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 684 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 685 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 686 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 687 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 688 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 689 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 690 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 691 }; 692 693 /* 694 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 695 * that DisplayPort specification requires 696 */ 697 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 698 /* VS pre-emp */ 699 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ 700 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ 701 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ 702 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ 703 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ 704 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ 705 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ 707 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ 708 }; 709 710 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr[] = { 711 /* NT mV Trans mV db */ 712 { 0xA, 0x2F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 713 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 714 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 715 { 0x6, 0x7D, 0x2A, 0x00, 0x15 }, /* 350 900 8.2 */ 716 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 717 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 718 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 719 { 0xC, 0x6E, 0x3E, 0x00, 0x01 }, /* 650 700 0.6 */ 720 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 721 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 722 }; 723 724 static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr3[] = { 725 /* NT mV Trans mV db */ 726 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 727 { 0xA, 0x50, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 728 { 0xC, 0x61, 0x33, 0x00, 0x0C }, /* 350 700 6.0 */ 729 { 0x6, 0x7F, 0x2E, 0x00, 0x11 }, /* 350 900 8.2 */ 730 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 731 { 0xC, 0x5F, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 732 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 733 { 0xC, 0x5F, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 734 { 0x6, 0x7E, 0x36, 0x00, 0x09 }, /* 600 900 3.5 */ 735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 736 }; 737 738 static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = { 739 /* VS pre-emp Non-trans mV Pre-emph dB */ 740 { 0x7, 0x0, 0x01 }, /* 0 0 400mV 0 dB */ 741 { 0x5, 0x0, 0x06 }, /* 0 1 400mV 3.5 dB */ 742 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 743 { 0x0, 0x0, 0x17 }, /* 0 3 400mV 9.5 dB */ 744 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 745 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 746 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 747 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 748 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 749 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */ 750 }; 751 752 static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = { 753 /* VS pre-emp Non-trans mV Pre-emph dB */ 754 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 755 { 0x5, 0x0, 0x04 }, /* 0 1 400mV 3.5 dB */ 756 { 0x2, 0x0, 0x0A }, /* 0 2 400mV 6 dB */ 757 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 758 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 759 { 0x2, 0x0, 0x06 }, /* 1 1 600mV 3.5 dB */ 760 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 761 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 762 { 0x0, 0x0, 0x09 }, /* 2 1 800mV 3.5 dB */ 763 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB */ 764 }; 765 766 bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) 767 { 768 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 769 } 770 771 static const struct ddi_buf_trans * 772 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 773 { 774 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 775 776 if (dev_priv->vbt.edp.low_vswing) { 777 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 778 return bdw_ddi_translations_edp; 779 } else { 780 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 781 return bdw_ddi_translations_dp; 782 } 783 } 784 785 static const struct ddi_buf_trans * 786 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 787 { 788 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 789 790 if (IS_SKL_ULX(dev_priv)) { 791 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 792 return skl_y_ddi_translations_dp; 793 } else if (IS_SKL_ULT(dev_priv)) { 794 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 795 return skl_u_ddi_translations_dp; 796 } else { 797 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 798 return skl_ddi_translations_dp; 799 } 800 } 801 802 static const struct ddi_buf_trans * 803 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 804 { 805 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 806 807 if (IS_KBL_ULX(dev_priv) || 808 IS_CFL_ULX(dev_priv) || 809 IS_CML_ULX(dev_priv)) { 810 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 811 return kbl_y_ddi_translations_dp; 812 } else if (IS_KBL_ULT(dev_priv) || 813 IS_CFL_ULT(dev_priv) || 814 IS_CML_ULT(dev_priv)) { 815 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 816 return kbl_u_ddi_translations_dp; 817 } else { 818 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 819 return kbl_ddi_translations_dp; 820 } 821 } 822 823 static const struct ddi_buf_trans * 824 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 825 { 826 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 827 828 if (dev_priv->vbt.edp.low_vswing) { 829 if (IS_SKL_ULX(dev_priv) || 830 IS_KBL_ULX(dev_priv) || 831 IS_CFL_ULX(dev_priv) || 832 IS_CML_ULX(dev_priv)) { 833 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 834 return skl_y_ddi_translations_edp; 835 } else if (IS_SKL_ULT(dev_priv) || 836 IS_KBL_ULT(dev_priv) || 837 IS_CFL_ULT(dev_priv) || 838 IS_CML_ULT(dev_priv)) { 839 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 840 return skl_u_ddi_translations_edp; 841 } else { 842 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 843 return skl_ddi_translations_edp; 844 } 845 } 846 847 if (IS_KABYLAKE(dev_priv) || 848 IS_COFFEELAKE(dev_priv) || 849 IS_COMETLAKE(dev_priv)) 850 return kbl_get_buf_trans_dp(encoder, n_entries); 851 else 852 return skl_get_buf_trans_dp(encoder, n_entries); 853 } 854 855 static const struct ddi_buf_trans * 856 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 857 { 858 if (IS_SKL_ULX(dev_priv) || 859 IS_KBL_ULX(dev_priv) || 860 IS_CFL_ULX(dev_priv) || 861 IS_CML_ULX(dev_priv)) { 862 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 863 return skl_y_ddi_translations_hdmi; 864 } else { 865 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 866 return skl_ddi_translations_hdmi; 867 } 868 } 869 870 static int skl_buf_trans_num_entries(enum port port, int n_entries) 871 { 872 /* Only DDIA and DDIE can select the 10th register with DP */ 873 if (port == PORT_A || port == PORT_E) 874 return min(n_entries, 10); 875 else 876 return min(n_entries, 9); 877 } 878 879 const struct ddi_buf_trans * 880 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 881 { 882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 883 884 if (IS_KABYLAKE(dev_priv) || 885 IS_COFFEELAKE(dev_priv) || 886 IS_COMETLAKE(dev_priv)) { 887 const struct ddi_buf_trans *ddi_translations = 888 kbl_get_buf_trans_dp(encoder, n_entries); 889 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 890 return ddi_translations; 891 } else if (IS_SKYLAKE(dev_priv)) { 892 const struct ddi_buf_trans *ddi_translations = 893 skl_get_buf_trans_dp(encoder, n_entries); 894 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 895 return ddi_translations; 896 } else if (IS_BROADWELL(dev_priv)) { 897 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 898 return bdw_ddi_translations_dp; 899 } else if (IS_HASWELL(dev_priv)) { 900 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 901 return hsw_ddi_translations_dp; 902 } 903 904 *n_entries = 0; 905 return NULL; 906 } 907 908 const struct ddi_buf_trans * 909 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 910 { 911 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 912 913 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 914 const struct ddi_buf_trans *ddi_translations = 915 skl_get_buf_trans_edp(encoder, n_entries); 916 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 917 return ddi_translations; 918 } else if (IS_BROADWELL(dev_priv)) { 919 return bdw_get_buf_trans_edp(encoder, n_entries); 920 } else if (IS_HASWELL(dev_priv)) { 921 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 922 return hsw_ddi_translations_dp; 923 } 924 925 *n_entries = 0; 926 return NULL; 927 } 928 929 const struct ddi_buf_trans * 930 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 931 int *n_entries) 932 { 933 if (IS_BROADWELL(dev_priv)) { 934 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 935 return bdw_ddi_translations_fdi; 936 } else if (IS_HASWELL(dev_priv)) { 937 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 938 return hsw_ddi_translations_fdi; 939 } 940 941 *n_entries = 0; 942 return NULL; 943 } 944 945 const struct ddi_buf_trans * 946 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 947 int *n_entries) 948 { 949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 950 951 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 952 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 953 } else if (IS_BROADWELL(dev_priv)) { 954 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 955 return bdw_ddi_translations_hdmi; 956 } else if (IS_HASWELL(dev_priv)) { 957 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 958 return hsw_ddi_translations_hdmi; 959 } 960 961 *n_entries = 0; 962 return NULL; 963 } 964 965 static const struct bxt_ddi_buf_trans * 966 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 967 { 968 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 969 return bxt_ddi_translations_dp; 970 } 971 972 static const struct bxt_ddi_buf_trans * 973 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 974 { 975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 976 977 if (dev_priv->vbt.edp.low_vswing) { 978 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 979 return bxt_ddi_translations_edp; 980 } 981 982 return bxt_get_buf_trans_dp(encoder, n_entries); 983 } 984 985 static const struct bxt_ddi_buf_trans * 986 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 987 { 988 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 989 return bxt_ddi_translations_hdmi; 990 } 991 992 const struct bxt_ddi_buf_trans * 993 bxt_get_buf_trans(struct intel_encoder *encoder, 994 const struct intel_crtc_state *crtc_state, 995 int *n_entries) 996 { 997 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 998 return bxt_get_buf_trans_hdmi(encoder, n_entries); 999 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1000 return bxt_get_buf_trans_edp(encoder, n_entries); 1001 return bxt_get_buf_trans_dp(encoder, n_entries); 1002 } 1003 1004 static const struct cnl_ddi_buf_trans * 1005 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 1006 { 1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1008 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1009 1010 if (voltage == VOLTAGE_INFO_0_85V) { 1011 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 1012 return cnl_ddi_translations_hdmi_0_85V; 1013 } else if (voltage == VOLTAGE_INFO_0_95V) { 1014 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 1015 return cnl_ddi_translations_hdmi_0_95V; 1016 } else if (voltage == VOLTAGE_INFO_1_05V) { 1017 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 1018 return cnl_ddi_translations_hdmi_1_05V; 1019 } else { 1020 *n_entries = 1; /* shut up gcc */ 1021 MISSING_CASE(voltage); 1022 } 1023 return NULL; 1024 } 1025 1026 static const struct cnl_ddi_buf_trans * 1027 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 1028 { 1029 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1030 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1031 1032 if (voltage == VOLTAGE_INFO_0_85V) { 1033 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 1034 return cnl_ddi_translations_dp_0_85V; 1035 } else if (voltage == VOLTAGE_INFO_0_95V) { 1036 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 1037 return cnl_ddi_translations_dp_0_95V; 1038 } else if (voltage == VOLTAGE_INFO_1_05V) { 1039 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 1040 return cnl_ddi_translations_dp_1_05V; 1041 } else { 1042 *n_entries = 1; /* shut up gcc */ 1043 MISSING_CASE(voltage); 1044 } 1045 return NULL; 1046 } 1047 1048 static const struct cnl_ddi_buf_trans * 1049 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1050 { 1051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1052 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1053 1054 if (dev_priv->vbt.edp.low_vswing) { 1055 if (voltage == VOLTAGE_INFO_0_85V) { 1056 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 1057 return cnl_ddi_translations_edp_0_85V; 1058 } else if (voltage == VOLTAGE_INFO_0_95V) { 1059 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 1060 return cnl_ddi_translations_edp_0_95V; 1061 } else if (voltage == VOLTAGE_INFO_1_05V) { 1062 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 1063 return cnl_ddi_translations_edp_1_05V; 1064 } else { 1065 *n_entries = 1; /* shut up gcc */ 1066 MISSING_CASE(voltage); 1067 } 1068 return NULL; 1069 } else { 1070 return cnl_get_buf_trans_dp(encoder, n_entries); 1071 } 1072 } 1073 1074 const struct cnl_ddi_buf_trans * 1075 cnl_get_buf_trans(struct intel_encoder *encoder, 1076 const struct intel_crtc_state *crtc_state, 1077 int *n_entries) 1078 { 1079 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1080 return cnl_get_buf_trans_hdmi(encoder, n_entries); 1081 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1082 return cnl_get_buf_trans_edp(encoder, n_entries); 1083 return cnl_get_buf_trans_dp(encoder, n_entries); 1084 } 1085 1086 static const struct cnl_ddi_buf_trans * 1087 icl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1088 const struct intel_crtc_state *crtc_state, 1089 int *n_entries) 1090 { 1091 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1092 return icl_combo_phy_ddi_translations_hdmi; 1093 } 1094 1095 static const struct cnl_ddi_buf_trans * 1096 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1097 const struct intel_crtc_state *crtc_state, 1098 int *n_entries) 1099 { 1100 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1101 return icl_combo_phy_ddi_translations_dp_hbr2; 1102 } 1103 1104 static const struct cnl_ddi_buf_trans * 1105 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1106 const struct intel_crtc_state *crtc_state, 1107 int *n_entries) 1108 { 1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1110 1111 if (crtc_state->port_clock > 540000) { 1112 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1113 return icl_combo_phy_ddi_translations_edp_hbr3; 1114 } else if (dev_priv->vbt.edp.low_vswing) { 1115 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1116 return icl_combo_phy_ddi_translations_edp_hbr2; 1117 } else if (IS_DG1(dev_priv) && crtc_state->port_clock > 270000) { 1118 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2_hbr3); 1119 return dg1_combo_phy_ddi_translations_dp_hbr2_hbr3; 1120 } else if (IS_DG1(dev_priv)) { 1121 *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_rbr_hbr); 1122 return dg1_combo_phy_ddi_translations_dp_rbr_hbr; 1123 } 1124 1125 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1126 } 1127 1128 const struct cnl_ddi_buf_trans * 1129 icl_get_combo_buf_trans(struct intel_encoder *encoder, 1130 const struct intel_crtc_state *crtc_state, 1131 int *n_entries) 1132 { 1133 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1134 return icl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1135 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1136 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1137 else 1138 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1139 } 1140 1141 static const struct icl_mg_phy_ddi_buf_trans * 1142 icl_get_mg_buf_trans_hdmi(struct intel_encoder *encoder, 1143 const struct intel_crtc_state *crtc_state, 1144 int *n_entries) 1145 { 1146 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1147 return icl_mg_phy_ddi_translations_hdmi; 1148 } 1149 1150 static const struct icl_mg_phy_ddi_buf_trans * 1151 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder, 1152 const struct intel_crtc_state *crtc_state, 1153 int *n_entries) 1154 { 1155 if (crtc_state->port_clock > 270000) { 1156 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1157 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1158 } else { 1159 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1160 return icl_mg_phy_ddi_translations_rbr_hbr; 1161 } 1162 } 1163 1164 const struct icl_mg_phy_ddi_buf_trans * 1165 icl_get_mg_buf_trans(struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state, 1167 int *n_entries) 1168 { 1169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1170 return icl_get_mg_buf_trans_hdmi(encoder, crtc_state, n_entries); 1171 else 1172 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries); 1173 } 1174 1175 static const struct cnl_ddi_buf_trans * 1176 ehl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1177 const struct intel_crtc_state *crtc_state, 1178 int *n_entries) 1179 { 1180 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1181 return icl_combo_phy_ddi_translations_hdmi; 1182 } 1183 1184 static const struct cnl_ddi_buf_trans * 1185 ehl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1186 const struct intel_crtc_state *crtc_state, 1187 int *n_entries) 1188 { 1189 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1190 return ehl_combo_phy_ddi_translations_dp; 1191 } 1192 1193 static const struct cnl_ddi_buf_trans * 1194 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1195 const struct intel_crtc_state *crtc_state, 1196 int *n_entries) 1197 { 1198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1199 1200 if (dev_priv->vbt.edp.low_vswing) { 1201 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1202 return icl_combo_phy_ddi_translations_edp_hbr2; 1203 } 1204 1205 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1206 } 1207 1208 const struct cnl_ddi_buf_trans * 1209 ehl_get_combo_buf_trans(struct intel_encoder *encoder, 1210 const struct intel_crtc_state *crtc_state, 1211 int *n_entries) 1212 { 1213 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1214 return ehl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1215 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1216 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1217 else 1218 return ehl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1219 } 1220 1221 static const struct cnl_ddi_buf_trans * 1222 jsl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1223 const struct intel_crtc_state *crtc_state, 1224 int *n_entries) 1225 { 1226 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1227 return icl_combo_phy_ddi_translations_hdmi; 1228 } 1229 1230 static const struct cnl_ddi_buf_trans * 1231 jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1232 const struct intel_crtc_state *crtc_state, 1233 int *n_entries) 1234 { 1235 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1236 return icl_combo_phy_ddi_translations_dp_hbr2; 1237 } 1238 1239 static const struct cnl_ddi_buf_trans * 1240 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1241 const struct intel_crtc_state *crtc_state, 1242 int *n_entries) 1243 { 1244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1245 1246 if (dev_priv->vbt.edp.low_vswing) { 1247 if (crtc_state->port_clock > 270000) { 1248 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2); 1249 return jsl_combo_phy_ddi_translations_edp_hbr2; 1250 } else { 1251 *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr); 1252 return jsl_combo_phy_ddi_translations_edp_hbr; 1253 } 1254 } 1255 1256 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1257 } 1258 1259 const struct cnl_ddi_buf_trans * 1260 jsl_get_combo_buf_trans(struct intel_encoder *encoder, 1261 const struct intel_crtc_state *crtc_state, 1262 int *n_entries) 1263 { 1264 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1265 return jsl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1266 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1267 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1268 else 1269 return jsl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1270 } 1271 1272 static const struct cnl_ddi_buf_trans * 1273 tgl_get_combo_buf_trans_hdmi(struct intel_encoder *encoder, 1274 const struct intel_crtc_state *crtc_state, 1275 int *n_entries) 1276 { 1277 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1278 return icl_combo_phy_ddi_translations_hdmi; 1279 } 1280 1281 static const struct cnl_ddi_buf_trans * 1282 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, 1283 const struct intel_crtc_state *crtc_state, 1284 int *n_entries) 1285 { 1286 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1287 1288 if (crtc_state->port_clock > 270000) { 1289 if (IS_ROCKETLAKE(dev_priv)) { 1290 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr2_hbr3); 1291 return rkl_combo_phy_ddi_translations_dp_hbr2_hbr3; 1292 } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1293 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); 1294 return tgl_uy_combo_phy_ddi_translations_dp_hbr2; 1295 } else { 1296 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1297 return tgl_combo_phy_ddi_translations_dp_hbr2; 1298 } 1299 } else { 1300 if (IS_ROCKETLAKE(dev_priv)) { 1301 *n_entries = ARRAY_SIZE(rkl_combo_phy_ddi_translations_dp_hbr); 1302 return rkl_combo_phy_ddi_translations_dp_hbr; 1303 } else { 1304 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1305 return tgl_combo_phy_ddi_translations_dp_hbr; 1306 } 1307 } 1308 } 1309 1310 static const struct cnl_ddi_buf_trans * 1311 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder, 1312 const struct intel_crtc_state *crtc_state, 1313 int *n_entries) 1314 { 1315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1317 1318 if (crtc_state->port_clock > 540000) { 1319 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1320 return icl_combo_phy_ddi_translations_edp_hbr3; 1321 } else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) { 1322 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); 1323 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1324 } else if (dev_priv->vbt.edp.low_vswing) { 1325 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1326 return icl_combo_phy_ddi_translations_edp_hbr2; 1327 } 1328 1329 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1330 } 1331 1332 const struct cnl_ddi_buf_trans * 1333 tgl_get_combo_buf_trans(struct intel_encoder *encoder, 1334 const struct intel_crtc_state *crtc_state, 1335 int *n_entries) 1336 { 1337 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1338 return tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, n_entries); 1339 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1340 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries); 1341 else 1342 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries); 1343 } 1344 1345 static const struct tgl_dkl_phy_ddi_buf_trans * 1346 tgl_get_dkl_buf_trans_hdmi(struct intel_encoder *encoder, 1347 const struct intel_crtc_state *crtc_state, 1348 int *n_entries) 1349 { 1350 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1351 return tgl_dkl_phy_hdmi_ddi_trans; 1352 } 1353 1354 static const struct tgl_dkl_phy_ddi_buf_trans * 1355 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1356 const struct intel_crtc_state *crtc_state, 1357 int *n_entries) 1358 { 1359 if (crtc_state->port_clock > 270000) { 1360 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1361 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1362 } else { 1363 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1364 return tgl_dkl_phy_dp_ddi_trans; 1365 } 1366 } 1367 1368 const struct tgl_dkl_phy_ddi_buf_trans * 1369 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, 1370 const struct intel_crtc_state *crtc_state, 1371 int *n_entries) 1372 { 1373 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1374 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); 1375 else 1376 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1377 } 1378 1379 static const struct tgl_dkl_phy_ddi_buf_trans * 1380 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder, 1381 const struct intel_crtc_state *crtc_state, 1382 int *n_entries) 1383 { 1384 if (crtc_state->port_clock > 270000) { 1385 *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3); 1386 return adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3; 1387 } 1388 1389 *n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr); 1390 return adlp_dkl_phy_dp_ddi_trans_hbr; 1391 } 1392 1393 const struct tgl_dkl_phy_ddi_buf_trans * 1394 adlp_get_dkl_buf_trans(struct intel_encoder *encoder, 1395 const struct intel_crtc_state *crtc_state, 1396 int *n_entries) 1397 { 1398 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1399 return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries); 1400 else 1401 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries); 1402 } 1403 1404 int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, 1405 const struct intel_crtc_state *crtc_state, 1406 int *default_entry) 1407 { 1408 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1409 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1410 int n_entries; 1411 1412 if (DISPLAY_VER(dev_priv) >= 12) { 1413 if (intel_phy_is_combo(dev_priv, phy)) 1414 tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1415 else 1416 tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1417 *default_entry = n_entries - 1; 1418 } else if (DISPLAY_VER(dev_priv) == 11) { 1419 if (intel_phy_is_combo(dev_priv, phy)) 1420 icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1421 else 1422 icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); 1423 *default_entry = n_entries - 1; 1424 } else if (IS_CANNONLAKE(dev_priv)) { 1425 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1426 *default_entry = n_entries - 1; 1427 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 1428 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1429 *default_entry = n_entries - 1; 1430 } else if (DISPLAY_VER(dev_priv) == 9) { 1431 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1432 *default_entry = 8; 1433 } else if (IS_BROADWELL(dev_priv)) { 1434 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1435 *default_entry = 7; 1436 } else if (IS_HASWELL(dev_priv)) { 1437 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1438 *default_entry = 6; 1439 } else { 1440 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1441 return 0; 1442 } 1443 1444 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1445 return 0; 1446 1447 return n_entries; 1448 } 1449