1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/gpio.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 19 #include <drm/bridge/analogix_dp.h> 20 21 #include "analogix_dp_core.h" 22 #include "analogix_dp_reg.h" 23 24 #define COMMON_INT_MASK_1 0 25 #define COMMON_INT_MASK_2 0 26 #define COMMON_INT_MASK_3 0 27 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 28 #define INT_STA_MASK INT_HPD 29 30 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 31 { 32 u32 reg; 33 34 if (enable) { 35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 36 reg |= HDCP_VIDEO_MUTE; 37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 38 } else { 39 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 40 reg &= ~HDCP_VIDEO_MUTE; 41 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 42 } 43 } 44 45 void analogix_dp_stop_video(struct analogix_dp_device *dp) 46 { 47 u32 reg; 48 49 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 50 reg &= ~VIDEO_EN; 51 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 52 } 53 54 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 55 { 56 u32 reg; 57 58 if (enable) 59 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 60 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 61 else 62 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 63 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 64 65 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); 66 } 67 68 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 69 { 70 u32 reg; 71 72 reg = TX_TERMINAL_CTRL_50_OHM; 73 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); 74 75 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 76 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); 77 78 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { 79 reg = REF_CLK_24M; 80 if (dp->plat_data->dev_type == RK3288_DP) 81 reg ^= REF_CLK_MASK; 82 83 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); 84 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); 85 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); 86 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); 87 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); 88 } 89 90 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 91 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); 92 93 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 94 TX_CUR1_2X | TX_CUR_16_MA; 95 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); 96 97 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 98 CH1_AMP_400_MV | CH0_AMP_400_MV; 99 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); 100 } 101 102 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 103 { 104 /* Set interrupt pin assertion polarity as high */ 105 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); 106 107 /* Clear pending regisers */ 108 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 109 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); 110 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); 111 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 112 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); 113 114 /* 0:mask,1: unmask */ 115 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 116 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 117 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 118 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 119 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 120 } 121 122 void analogix_dp_reset(struct analogix_dp_device *dp) 123 { 124 u32 reg; 125 126 analogix_dp_stop_video(dp); 127 analogix_dp_enable_video_mute(dp, 0); 128 129 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 130 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 131 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 132 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 133 134 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 135 SERDES_FIFO_FUNC_EN_N | 136 LS_CLK_DOMAIN_FUNC_EN_N; 137 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 138 139 usleep_range(20, 30); 140 141 analogix_dp_lane_swap(dp, 0); 142 143 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 144 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 145 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 146 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 147 148 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 149 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); 150 151 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); 152 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); 153 154 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); 155 156 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); 157 158 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); 159 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); 160 161 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); 162 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); 163 164 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 165 } 166 167 void analogix_dp_swreset(struct analogix_dp_device *dp) 168 { 169 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); 170 } 171 172 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 173 { 174 u32 reg; 175 176 /* 0: mask, 1: unmask */ 177 reg = COMMON_INT_MASK_1; 178 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 179 180 reg = COMMON_INT_MASK_2; 181 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 182 183 reg = COMMON_INT_MASK_3; 184 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 185 186 reg = COMMON_INT_MASK_4; 187 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 188 189 reg = INT_STA_MASK; 190 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 191 } 192 193 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 194 { 195 u32 reg; 196 197 /* 0: mask, 1: unmask */ 198 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 199 reg &= ~COMMON_INT_MASK_4; 200 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 201 202 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 203 reg &= ~INT_STA_MASK; 204 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 205 } 206 207 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 208 { 209 u32 reg; 210 211 /* 0: mask, 1: unmask */ 212 reg = COMMON_INT_MASK_4; 213 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 214 215 reg = INT_STA_MASK; 216 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 217 } 218 219 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 220 { 221 u32 reg; 222 223 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 224 if (reg & PLL_LOCK) 225 return PLL_LOCKED; 226 else 227 return PLL_UNLOCKED; 228 } 229 230 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 231 { 232 u32 reg; 233 234 if (enable) { 235 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 236 reg |= DP_PLL_PD; 237 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 238 } else { 239 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 240 reg &= ~DP_PLL_PD; 241 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 242 } 243 } 244 245 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 246 enum analog_power_block block, 247 bool enable) 248 { 249 u32 reg; 250 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 251 u32 mask; 252 253 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 254 phy_pd_addr = ANALOGIX_DP_PD; 255 256 switch (block) { 257 case AUX_BLOCK: 258 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 259 mask = RK_AUX_PD; 260 else 261 mask = AUX_PD; 262 263 reg = readl(dp->reg_base + phy_pd_addr); 264 if (enable) 265 reg |= mask; 266 else 267 reg &= ~mask; 268 writel(reg, dp->reg_base + phy_pd_addr); 269 break; 270 case CH0_BLOCK: 271 mask = CH0_PD; 272 reg = readl(dp->reg_base + phy_pd_addr); 273 274 if (enable) 275 reg |= mask; 276 else 277 reg &= ~mask; 278 writel(reg, dp->reg_base + phy_pd_addr); 279 break; 280 case CH1_BLOCK: 281 mask = CH1_PD; 282 reg = readl(dp->reg_base + phy_pd_addr); 283 284 if (enable) 285 reg |= mask; 286 else 287 reg &= ~mask; 288 writel(reg, dp->reg_base + phy_pd_addr); 289 break; 290 case CH2_BLOCK: 291 mask = CH2_PD; 292 reg = readl(dp->reg_base + phy_pd_addr); 293 294 if (enable) 295 reg |= mask; 296 else 297 reg &= ~mask; 298 writel(reg, dp->reg_base + phy_pd_addr); 299 break; 300 case CH3_BLOCK: 301 mask = CH3_PD; 302 reg = readl(dp->reg_base + phy_pd_addr); 303 304 if (enable) 305 reg |= mask; 306 else 307 reg &= ~mask; 308 writel(reg, dp->reg_base + phy_pd_addr); 309 break; 310 case ANALOG_TOTAL: 311 /* 312 * There is no bit named DP_PHY_PD, so We used DP_INC_BG 313 * to power off everything instead of DP_PHY_PD in 314 * Rockchip 315 */ 316 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 317 mask = DP_INC_BG; 318 else 319 mask = DP_PHY_PD; 320 321 reg = readl(dp->reg_base + phy_pd_addr); 322 if (enable) 323 reg |= mask; 324 else 325 reg &= ~mask; 326 327 writel(reg, dp->reg_base + phy_pd_addr); 328 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 329 usleep_range(10, 15); 330 break; 331 case POWER_ALL: 332 if (enable) { 333 reg = DP_ALL_PD; 334 writel(reg, dp->reg_base + phy_pd_addr); 335 } else { 336 reg = DP_ALL_PD; 337 writel(reg, dp->reg_base + phy_pd_addr); 338 usleep_range(10, 15); 339 reg &= ~DP_INC_BG; 340 writel(reg, dp->reg_base + phy_pd_addr); 341 usleep_range(10, 15); 342 343 writel(0x00, dp->reg_base + phy_pd_addr); 344 } 345 break; 346 default: 347 break; 348 } 349 } 350 351 int analogix_dp_init_analog_func(struct analogix_dp_device *dp) 352 { 353 u32 reg; 354 int timeout_loop = 0; 355 356 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 357 358 reg = PLL_LOCK_CHG; 359 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 360 361 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 362 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 363 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 364 365 /* Power up PLL */ 366 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 367 analogix_dp_set_pll_power_down(dp, 0); 368 369 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 370 timeout_loop++; 371 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 372 dev_err(dp->dev, "failed to get pll lock status\n"); 373 return -ETIMEDOUT; 374 } 375 usleep_range(10, 20); 376 } 377 } 378 379 /* Enable Serdes FIFO function and Link symbol clock domain module */ 380 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 381 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 382 | AUX_FUNC_EN_N); 383 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 384 return 0; 385 } 386 387 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 388 { 389 u32 reg; 390 391 if (gpio_is_valid(dp->hpd_gpio)) 392 return; 393 394 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 395 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 396 397 reg = INT_HPD; 398 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 399 } 400 401 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 402 { 403 u32 reg; 404 405 if (gpio_is_valid(dp->hpd_gpio)) 406 return; 407 408 analogix_dp_clear_hotplug_interrupts(dp); 409 410 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 411 reg &= ~(F_HPD | HPD_CTRL); 412 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 413 } 414 415 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 416 { 417 u32 reg; 418 419 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 420 reg = (F_HPD | HPD_CTRL); 421 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 422 } 423 424 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 425 { 426 u32 reg; 427 428 if (gpio_is_valid(dp->hpd_gpio)) { 429 reg = gpio_get_value(dp->hpd_gpio); 430 if (reg) 431 return DP_IRQ_TYPE_HP_CABLE_IN; 432 else 433 return DP_IRQ_TYPE_HP_CABLE_OUT; 434 } else { 435 /* Parse hotplug interrupt status register */ 436 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 437 438 if (reg & PLUG) 439 return DP_IRQ_TYPE_HP_CABLE_IN; 440 441 if (reg & HPD_LOST) 442 return DP_IRQ_TYPE_HP_CABLE_OUT; 443 444 if (reg & HOTPLUG_CHG) 445 return DP_IRQ_TYPE_HP_CHANGE; 446 447 return DP_IRQ_TYPE_UNKNOWN; 448 } 449 } 450 451 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 452 { 453 u32 reg; 454 455 /* Disable AUX channel module */ 456 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 457 reg |= AUX_FUNC_EN_N; 458 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 459 } 460 461 void analogix_dp_init_aux(struct analogix_dp_device *dp) 462 { 463 u32 reg; 464 465 /* Clear inerrupts related to AUX channel */ 466 reg = RPLY_RECEIV | AUX_ERR; 467 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 468 469 analogix_dp_reset_aux(dp); 470 471 /* Disable AUX transaction H/W retry */ 472 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 473 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 474 AUX_HW_RETRY_COUNT_SEL(3) | 475 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 476 else 477 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 478 AUX_HW_RETRY_COUNT_SEL(0) | 479 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 480 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); 481 482 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 483 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 484 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); 485 486 /* Enable AUX channel module */ 487 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 488 reg &= ~AUX_FUNC_EN_N; 489 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 490 } 491 492 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 493 { 494 u32 reg; 495 496 if (gpio_is_valid(dp->hpd_gpio)) { 497 if (gpio_get_value(dp->hpd_gpio)) 498 return 0; 499 } else { 500 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 501 if (reg & HPD_STATUS) 502 return 0; 503 } 504 505 return -EINVAL; 506 } 507 508 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 509 { 510 u32 reg; 511 512 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 513 reg &= ~SW_FUNC_EN_N; 514 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 515 } 516 517 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 518 { 519 int reg; 520 int retval = 0; 521 int timeout_loop = 0; 522 523 /* Enable AUX CH operation */ 524 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 525 reg |= AUX_EN; 526 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 527 528 /* Is AUX CH command reply received? */ 529 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 530 while (!(reg & RPLY_RECEIV)) { 531 timeout_loop++; 532 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 533 dev_err(dp->dev, "AUX CH command reply failed!\n"); 534 return -ETIMEDOUT; 535 } 536 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 537 usleep_range(10, 11); 538 } 539 540 /* Clear interrupt source for AUX CH command reply */ 541 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); 542 543 /* Clear interrupt source for AUX CH access error */ 544 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 545 if (reg & AUX_ERR) { 546 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); 547 return -EREMOTEIO; 548 } 549 550 /* Check AUX CH error access status */ 551 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); 552 if ((reg & AUX_STATUS_MASK) != 0) { 553 dev_err(dp->dev, "AUX CH error happens: %d\n\n", 554 reg & AUX_STATUS_MASK); 555 return -EREMOTEIO; 556 } 557 558 return retval; 559 } 560 561 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 562 unsigned int reg_addr, 563 unsigned char data) 564 { 565 u32 reg; 566 int i; 567 int retval; 568 569 for (i = 0; i < 3; i++) { 570 /* Clear AUX CH data buffer */ 571 reg = BUF_CLR; 572 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 573 574 /* Select DPCD device address */ 575 reg = AUX_ADDR_7_0(reg_addr); 576 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 577 reg = AUX_ADDR_15_8(reg_addr); 578 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 579 reg = AUX_ADDR_19_16(reg_addr); 580 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 581 582 /* Write data buffer */ 583 reg = (unsigned int)data; 584 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 585 586 /* 587 * Set DisplayPort transaction and write 1 byte 588 * If bit 3 is 1, DisplayPort transaction. 589 * If Bit 3 is 0, I2C transaction. 590 */ 591 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 592 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 593 594 /* Start AUX transaction */ 595 retval = analogix_dp_start_aux_transaction(dp); 596 if (retval == 0) 597 break; 598 599 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); 600 } 601 602 return retval; 603 } 604 605 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 606 { 607 u32 reg; 608 609 reg = bwtype; 610 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 611 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 612 } 613 614 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 615 { 616 u32 reg; 617 618 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 619 *bwtype = reg; 620 } 621 622 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 623 { 624 u32 reg; 625 626 reg = count; 627 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 628 } 629 630 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 631 { 632 u32 reg; 633 634 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 635 *count = reg; 636 } 637 638 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 639 bool enable) 640 { 641 u32 reg; 642 643 if (enable) { 644 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 645 reg |= ENHANCED; 646 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 647 } else { 648 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 649 reg &= ~ENHANCED; 650 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 651 } 652 } 653 654 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 655 enum pattern_set pattern) 656 { 657 u32 reg; 658 659 switch (pattern) { 660 case PRBS7: 661 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 662 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 663 break; 664 case D10_2: 665 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 666 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 667 break; 668 case TRAINING_PTN1: 669 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 670 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 671 break; 672 case TRAINING_PTN2: 673 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 674 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 675 break; 676 case DP_NONE: 677 reg = SCRAMBLING_ENABLE | 678 LINK_QUAL_PATTERN_SET_DISABLE | 679 SW_TRAINING_PATTERN_SET_NORMAL; 680 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 681 break; 682 default: 683 break; 684 } 685 } 686 687 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 688 u32 level) 689 { 690 u32 reg; 691 692 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 693 reg &= ~PRE_EMPHASIS_SET_MASK; 694 reg |= level << PRE_EMPHASIS_SET_SHIFT; 695 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 696 } 697 698 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 699 u32 level) 700 { 701 u32 reg; 702 703 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 704 reg &= ~PRE_EMPHASIS_SET_MASK; 705 reg |= level << PRE_EMPHASIS_SET_SHIFT; 706 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 707 } 708 709 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 710 u32 level) 711 { 712 u32 reg; 713 714 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 715 reg &= ~PRE_EMPHASIS_SET_MASK; 716 reg |= level << PRE_EMPHASIS_SET_SHIFT; 717 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 718 } 719 720 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 721 u32 level) 722 { 723 u32 reg; 724 725 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 726 reg &= ~PRE_EMPHASIS_SET_MASK; 727 reg |= level << PRE_EMPHASIS_SET_SHIFT; 728 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 729 } 730 731 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 732 u32 training_lane) 733 { 734 u32 reg; 735 736 reg = training_lane; 737 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 738 } 739 740 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 741 u32 training_lane) 742 { 743 u32 reg; 744 745 reg = training_lane; 746 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 747 } 748 749 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 750 u32 training_lane) 751 { 752 u32 reg; 753 754 reg = training_lane; 755 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 756 } 757 758 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 759 u32 training_lane) 760 { 761 u32 reg; 762 763 reg = training_lane; 764 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 765 } 766 767 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) 768 { 769 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 770 } 771 772 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) 773 { 774 return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 775 } 776 777 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) 778 { 779 return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 780 } 781 782 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) 783 { 784 return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 785 } 786 787 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 788 { 789 u32 reg; 790 791 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); 792 reg |= MACRO_RST; 793 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 794 795 /* 10 us is the minimum reset time. */ 796 usleep_range(10, 20); 797 798 reg &= ~MACRO_RST; 799 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 800 } 801 802 void analogix_dp_init_video(struct analogix_dp_device *dp) 803 { 804 u32 reg; 805 806 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 807 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 808 809 reg = 0x0; 810 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 811 812 reg = CHA_CRI(4) | CHA_CTRL; 813 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 814 815 reg = 0x0; 816 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 817 818 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 819 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); 820 } 821 822 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 823 { 824 u32 reg; 825 826 /* Configure the input color depth, color space, dynamic range */ 827 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 828 (dp->video_info.color_depth << IN_BPC_SHIFT) | 829 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 830 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); 831 832 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 833 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 834 reg &= ~IN_YC_COEFFI_MASK; 835 if (dp->video_info.ycbcr_coeff) 836 reg |= IN_YC_COEFFI_ITU709; 837 else 838 reg |= IN_YC_COEFFI_ITU601; 839 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 840 } 841 842 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 843 { 844 u32 reg; 845 846 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 847 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 848 849 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 850 851 if (!(reg & DET_STA)) { 852 dev_dbg(dp->dev, "Input stream clock not detected.\n"); 853 return -EINVAL; 854 } 855 856 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 857 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 858 859 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 860 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); 861 862 if (reg & CHA_STA) { 863 dev_dbg(dp->dev, "Input stream clk is changing\n"); 864 return -EINVAL; 865 } 866 867 return 0; 868 } 869 870 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 871 enum clock_recovery_m_value_type type, 872 u32 m_value, u32 n_value) 873 { 874 u32 reg; 875 876 if (type == REGISTER_M) { 877 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 878 reg |= FIX_M_VID; 879 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 880 reg = m_value & 0xff; 881 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); 882 reg = (m_value >> 8) & 0xff; 883 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); 884 reg = (m_value >> 16) & 0xff; 885 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); 886 887 reg = n_value & 0xff; 888 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); 889 reg = (n_value >> 8) & 0xff; 890 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); 891 reg = (n_value >> 16) & 0xff; 892 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); 893 } else { 894 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 895 reg &= ~FIX_M_VID; 896 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 897 898 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); 899 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); 900 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); 901 } 902 } 903 904 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 905 { 906 u32 reg; 907 908 if (type == VIDEO_TIMING_FROM_CAPTURE) { 909 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 910 reg &= ~FORMAT_SEL; 911 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 912 } else { 913 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 914 reg |= FORMAT_SEL; 915 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 916 } 917 } 918 919 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 920 { 921 u32 reg; 922 923 if (enable) { 924 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 925 reg &= ~VIDEO_MODE_MASK; 926 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 927 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 928 } else { 929 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 930 reg &= ~VIDEO_MODE_MASK; 931 reg |= VIDEO_MODE_SLAVE_MODE; 932 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 933 } 934 } 935 936 void analogix_dp_start_video(struct analogix_dp_device *dp) 937 { 938 u32 reg; 939 940 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 941 reg |= VIDEO_EN; 942 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 943 } 944 945 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 946 { 947 u32 reg; 948 949 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 950 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 951 952 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 953 if (!(reg & STRM_VALID)) { 954 dev_dbg(dp->dev, "Input video stream is not detected.\n"); 955 return -EINVAL; 956 } 957 958 return 0; 959 } 960 961 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 962 { 963 u32 reg; 964 965 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 966 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 967 reg |= MASTER_VID_FUNC_EN_N; 968 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 969 970 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 971 reg &= ~INTERACE_SCAN_CFG; 972 reg |= (dp->video_info.interlaced << 2); 973 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 974 975 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 976 reg &= ~VSYNC_POLARITY_CFG; 977 reg |= (dp->video_info.v_sync_polarity << 1); 978 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 979 980 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 981 reg &= ~HSYNC_POLARITY_CFG; 982 reg |= (dp->video_info.h_sync_polarity << 0); 983 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 984 985 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 986 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 987 } 988 989 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 990 { 991 u32 reg; 992 993 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 994 reg &= ~SCRAMBLING_DISABLE; 995 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 996 } 997 998 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 999 { 1000 u32 reg; 1001 1002 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1003 reg |= SCRAMBLING_DISABLE; 1004 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1005 } 1006 1007 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp) 1008 { 1009 writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON); 1010 } 1011 1012 static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp) 1013 { 1014 ssize_t val; 1015 u8 status; 1016 1017 val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status); 1018 if (val < 0) { 1019 dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val); 1020 return val; 1021 } 1022 return status; 1023 } 1024 1025 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 1026 struct edp_vsc_psr *vsc, bool blocking) 1027 { 1028 unsigned int val; 1029 int ret; 1030 ssize_t psr_status; 1031 1032 /* don't send info frame */ 1033 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1034 val &= ~IF_EN; 1035 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1036 1037 /* configure single frame update mode */ 1038 writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE, 1039 dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); 1040 1041 /* configure VSC HB0~HB3 */ 1042 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); 1043 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); 1044 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); 1045 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); 1046 1047 /* configure reused VSC PB0~PB3, magic number from vendor */ 1048 writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0); 1049 writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1); 1050 writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2); 1051 writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3); 1052 1053 /* configure DB0 / DB1 values */ 1054 writel(vsc->DB0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); 1055 writel(vsc->DB1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); 1056 1057 /* set reuse spd inforframe */ 1058 val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1059 val |= REUSE_SPD_EN; 1060 writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1061 1062 /* mark info frame update */ 1063 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1064 val = (val | IF_UP) & ~IF_EN; 1065 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1066 1067 /* send info frame */ 1068 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1069 val |= IF_EN; 1070 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 1071 1072 if (!blocking) 1073 return 0; 1074 1075 ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status, 1076 psr_status >= 0 && 1077 ((vsc->DB1 && psr_status == DP_PSR_SINK_ACTIVE_RFB) || 1078 (!vsc->DB1 && psr_status == DP_PSR_SINK_INACTIVE)), 1500, 1079 DP_TIMEOUT_PSR_LOOP_MS * 1000); 1080 if (ret) { 1081 dev_warn(dp->dev, "Failed to apply PSR %d\n", ret); 1082 return ret; 1083 } 1084 return 0; 1085 } 1086 1087 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, 1088 struct drm_dp_aux_msg *msg) 1089 { 1090 u32 reg; 1091 u8 *buffer = msg->buffer; 1092 unsigned int i; 1093 int num_transferred = 0; 1094 int ret; 1095 1096 /* Buffer size of AUX CH is 16 bytes */ 1097 if (WARN_ON(msg->size > 16)) 1098 return -E2BIG; 1099 1100 /* Clear AUX CH data buffer */ 1101 reg = BUF_CLR; 1102 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 1103 1104 switch (msg->request & ~DP_AUX_I2C_MOT) { 1105 case DP_AUX_I2C_WRITE: 1106 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION; 1107 if (msg->request & DP_AUX_I2C_MOT) 1108 reg |= AUX_TX_COMM_MOT; 1109 break; 1110 1111 case DP_AUX_I2C_READ: 1112 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION; 1113 if (msg->request & DP_AUX_I2C_MOT) 1114 reg |= AUX_TX_COMM_MOT; 1115 break; 1116 1117 case DP_AUX_NATIVE_WRITE: 1118 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION; 1119 break; 1120 1121 case DP_AUX_NATIVE_READ: 1122 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION; 1123 break; 1124 1125 default: 1126 return -EINVAL; 1127 } 1128 1129 reg |= AUX_LENGTH(msg->size); 1130 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 1131 1132 /* Select DPCD device address */ 1133 reg = AUX_ADDR_7_0(msg->address); 1134 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 1135 reg = AUX_ADDR_15_8(msg->address); 1136 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 1137 reg = AUX_ADDR_19_16(msg->address); 1138 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 1139 1140 if (!(msg->request & DP_AUX_I2C_READ)) { 1141 for (i = 0; i < msg->size; i++) { 1142 reg = buffer[i]; 1143 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + 1144 4 * i); 1145 num_transferred++; 1146 } 1147 } 1148 1149 /* Enable AUX CH operation */ 1150 reg = AUX_EN; 1151 1152 /* Zero-sized messages specify address-only transactions. */ 1153 if (msg->size < 1) 1154 reg |= ADDR_ONLY; 1155 1156 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 1157 1158 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2, 1159 reg, !(reg & AUX_EN), 25, 500 * 1000); 1160 if (ret) { 1161 dev_err(dp->dev, "AUX CH enable timeout!\n"); 1162 return -ETIMEDOUT; 1163 } 1164 1165 /* TODO: Wait for an interrupt instead of looping? */ 1166 /* Is AUX CH command reply received? */ 1167 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA, 1168 reg, reg & RPLY_RECEIV, 10, 20 * 1000); 1169 if (ret) { 1170 dev_err(dp->dev, "AUX CH cmd reply timeout!\n"); 1171 return -ETIMEDOUT; 1172 } 1173 1174 /* Clear interrupt source for AUX CH command reply */ 1175 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); 1176 1177 /* Clear interrupt source for AUX CH access error */ 1178 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 1179 if (reg & AUX_ERR) { 1180 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); 1181 return -EREMOTEIO; 1182 } 1183 1184 /* Check AUX CH error access status */ 1185 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); 1186 if ((reg & AUX_STATUS_MASK)) { 1187 dev_err(dp->dev, "AUX CH error happened: %d\n\n", 1188 reg & AUX_STATUS_MASK); 1189 return -EREMOTEIO; 1190 } 1191 1192 if (msg->request & DP_AUX_I2C_READ) { 1193 for (i = 0; i < msg->size; i++) { 1194 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + 1195 4 * i); 1196 buffer[i] = (unsigned char)reg; 1197 num_transferred++; 1198 } 1199 } 1200 1201 /* Check if Rx sends defer */ 1202 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); 1203 if (reg == AUX_RX_COMM_AUX_DEFER) 1204 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; 1205 else if (reg == AUX_RX_COMM_I2C_DEFER) 1206 msg->reply = DP_AUX_I2C_REPLY_DEFER; 1207 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || 1208 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) 1209 msg->reply = DP_AUX_I2C_REPLY_ACK; 1210 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || 1211 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) 1212 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 1213 1214 return num_transferred > 0 ? num_transferred : -EBUSY; 1215 } 1216