1 /*
2  * Analogix DP (Display port) core register interface driver.
3  *
4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5  * Author: Jingoo Han <jg1.han@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms of the GNU General Public License as published by the
9  * Free Software Foundation; either version 2 of the License, or (at your
10  * option) any later version.
11  */
12 
13 #include <linux/device.h>
14 #include <linux/io.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 
18 #include <drm/bridge/analogix_dp.h>
19 
20 #include "analogix_dp_core.h"
21 #include "analogix_dp_reg.h"
22 
23 #define COMMON_INT_MASK_1	0
24 #define COMMON_INT_MASK_2	0
25 #define COMMON_INT_MASK_3	0
26 #define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
27 #define INT_STA_MASK		INT_HPD
28 
29 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
30 {
31 	u32 reg;
32 
33 	if (enable) {
34 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
35 		reg |= HDCP_VIDEO_MUTE;
36 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
37 	} else {
38 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
39 		reg &= ~HDCP_VIDEO_MUTE;
40 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
41 	}
42 }
43 
44 void analogix_dp_stop_video(struct analogix_dp_device *dp)
45 {
46 	u32 reg;
47 
48 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
49 	reg &= ~VIDEO_EN;
50 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
51 }
52 
53 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
54 {
55 	u32 reg;
56 
57 	if (enable)
58 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
59 		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
60 	else
61 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
62 		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
63 
64 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
65 }
66 
67 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
68 {
69 	u32 reg;
70 
71 	reg = TX_TERMINAL_CTRL_50_OHM;
72 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
73 
74 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
75 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
76 
77 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
78 		reg = REF_CLK_24M;
79 		if (dp->plat_data->dev_type == RK3288_DP)
80 			reg ^= REF_CLK_MASK;
81 
82 		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
83 		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
84 		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
85 		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
86 		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
87 	}
88 
89 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
90 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
91 
92 	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
93 		TX_CUR1_2X | TX_CUR_16_MA;
94 	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
95 
96 	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
97 		CH1_AMP_400_MV | CH0_AMP_400_MV;
98 	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
99 }
100 
101 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
102 {
103 	/* Set interrupt pin assertion polarity as high */
104 	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
105 
106 	/* Clear pending regisers */
107 	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
108 	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
109 	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
110 	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
111 	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
112 
113 	/* 0:mask,1: unmask */
114 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
115 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
116 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
117 	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
118 	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
119 }
120 
121 void analogix_dp_reset(struct analogix_dp_device *dp)
122 {
123 	u32 reg;
124 
125 	analogix_dp_stop_video(dp);
126 	analogix_dp_enable_video_mute(dp, 0);
127 
128 	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
129 		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
130 		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
131 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
132 
133 	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
134 		SERDES_FIFO_FUNC_EN_N |
135 		LS_CLK_DOMAIN_FUNC_EN_N;
136 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
137 
138 	usleep_range(20, 30);
139 
140 	analogix_dp_lane_swap(dp, 0);
141 
142 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
143 	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
144 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
145 	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
146 
147 	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
148 	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
149 
150 	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
151 	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
152 
153 	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
154 
155 	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
156 
157 	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
158 	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
159 
160 	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
161 	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
162 
163 	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
164 }
165 
166 void analogix_dp_swreset(struct analogix_dp_device *dp)
167 {
168 	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
169 }
170 
171 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
172 {
173 	u32 reg;
174 
175 	/* 0: mask, 1: unmask */
176 	reg = COMMON_INT_MASK_1;
177 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
178 
179 	reg = COMMON_INT_MASK_2;
180 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
181 
182 	reg = COMMON_INT_MASK_3;
183 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
184 
185 	reg = COMMON_INT_MASK_4;
186 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
187 
188 	reg = INT_STA_MASK;
189 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
190 }
191 
192 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
193 {
194 	u32 reg;
195 
196 	/* 0: mask, 1: unmask */
197 	reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
198 	reg &= ~COMMON_INT_MASK_4;
199 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
200 
201 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
202 	reg &= ~INT_STA_MASK;
203 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
204 }
205 
206 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
207 {
208 	u32 reg;
209 
210 	/* 0: mask, 1: unmask */
211 	reg = COMMON_INT_MASK_4;
212 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
213 
214 	reg = INT_STA_MASK;
215 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
216 }
217 
218 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
219 {
220 	u32 reg;
221 
222 	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
223 	if (reg & PLL_LOCK)
224 		return PLL_LOCKED;
225 	else
226 		return PLL_UNLOCKED;
227 }
228 
229 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
230 {
231 	u32 reg;
232 
233 	if (enable) {
234 		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
235 		reg |= DP_PLL_PD;
236 		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
237 	} else {
238 		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
239 		reg &= ~DP_PLL_PD;
240 		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
241 	}
242 }
243 
244 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
245 				       enum analog_power_block block,
246 				       bool enable)
247 {
248 	u32 reg;
249 	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
250 
251 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
252 		phy_pd_addr = ANALOGIX_DP_PD;
253 
254 	switch (block) {
255 	case AUX_BLOCK:
256 		if (enable) {
257 			reg = readl(dp->reg_base + phy_pd_addr);
258 			reg |= AUX_PD;
259 			writel(reg, dp->reg_base + phy_pd_addr);
260 		} else {
261 			reg = readl(dp->reg_base + phy_pd_addr);
262 			reg &= ~AUX_PD;
263 			writel(reg, dp->reg_base + phy_pd_addr);
264 		}
265 		break;
266 	case CH0_BLOCK:
267 		if (enable) {
268 			reg = readl(dp->reg_base + phy_pd_addr);
269 			reg |= CH0_PD;
270 			writel(reg, dp->reg_base + phy_pd_addr);
271 		} else {
272 			reg = readl(dp->reg_base + phy_pd_addr);
273 			reg &= ~CH0_PD;
274 			writel(reg, dp->reg_base + phy_pd_addr);
275 		}
276 		break;
277 	case CH1_BLOCK:
278 		if (enable) {
279 			reg = readl(dp->reg_base + phy_pd_addr);
280 			reg |= CH1_PD;
281 			writel(reg, dp->reg_base + phy_pd_addr);
282 		} else {
283 			reg = readl(dp->reg_base + phy_pd_addr);
284 			reg &= ~CH1_PD;
285 			writel(reg, dp->reg_base + phy_pd_addr);
286 		}
287 		break;
288 	case CH2_BLOCK:
289 		if (enable) {
290 			reg = readl(dp->reg_base + phy_pd_addr);
291 			reg |= CH2_PD;
292 			writel(reg, dp->reg_base + phy_pd_addr);
293 		} else {
294 			reg = readl(dp->reg_base + phy_pd_addr);
295 			reg &= ~CH2_PD;
296 			writel(reg, dp->reg_base + phy_pd_addr);
297 		}
298 		break;
299 	case CH3_BLOCK:
300 		if (enable) {
301 			reg = readl(dp->reg_base + phy_pd_addr);
302 			reg |= CH3_PD;
303 			writel(reg, dp->reg_base + phy_pd_addr);
304 		} else {
305 			reg = readl(dp->reg_base + phy_pd_addr);
306 			reg &= ~CH3_PD;
307 			writel(reg, dp->reg_base + phy_pd_addr);
308 		}
309 		break;
310 	case ANALOG_TOTAL:
311 		if (enable) {
312 			reg = readl(dp->reg_base + phy_pd_addr);
313 			reg |= DP_PHY_PD;
314 			writel(reg, dp->reg_base + phy_pd_addr);
315 		} else {
316 			reg = readl(dp->reg_base + phy_pd_addr);
317 			reg &= ~DP_PHY_PD;
318 			writel(reg, dp->reg_base + phy_pd_addr);
319 		}
320 		break;
321 	case POWER_ALL:
322 		if (enable) {
323 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
324 				CH1_PD | CH0_PD;
325 			writel(reg, dp->reg_base + phy_pd_addr);
326 		} else {
327 			writel(0x00, dp->reg_base + phy_pd_addr);
328 		}
329 		break;
330 	default:
331 		break;
332 	}
333 }
334 
335 void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
336 {
337 	u32 reg;
338 	int timeout_loop = 0;
339 
340 	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
341 
342 	reg = PLL_LOCK_CHG;
343 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
344 
345 	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
346 	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
347 	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
348 
349 	/* Power up PLL */
350 	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
351 		analogix_dp_set_pll_power_down(dp, 0);
352 
353 		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
354 			timeout_loop++;
355 			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
356 				dev_err(dp->dev, "failed to get pll lock status\n");
357 				return;
358 			}
359 			usleep_range(10, 20);
360 		}
361 	}
362 
363 	/* Enable Serdes FIFO function and Link symbol clock domain module */
364 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
365 	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
366 		| AUX_FUNC_EN_N);
367 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
368 }
369 
370 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
371 {
372 	u32 reg;
373 
374 	if (gpio_is_valid(dp->hpd_gpio))
375 		return;
376 
377 	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
378 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
379 
380 	reg = INT_HPD;
381 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
382 }
383 
384 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
385 {
386 	u32 reg;
387 
388 	if (gpio_is_valid(dp->hpd_gpio))
389 		return;
390 
391 	analogix_dp_clear_hotplug_interrupts(dp);
392 
393 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
394 	reg &= ~(F_HPD | HPD_CTRL);
395 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
396 }
397 
398 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
399 {
400 	u32 reg;
401 
402 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
403 	reg = (F_HPD | HPD_CTRL);
404 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
405 }
406 
407 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
408 {
409 	u32 reg;
410 
411 	if (gpio_is_valid(dp->hpd_gpio)) {
412 		reg = gpio_get_value(dp->hpd_gpio);
413 		if (reg)
414 			return DP_IRQ_TYPE_HP_CABLE_IN;
415 		else
416 			return DP_IRQ_TYPE_HP_CABLE_OUT;
417 	} else {
418 		/* Parse hotplug interrupt status register */
419 		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
420 
421 		if (reg & PLUG)
422 			return DP_IRQ_TYPE_HP_CABLE_IN;
423 
424 		if (reg & HPD_LOST)
425 			return DP_IRQ_TYPE_HP_CABLE_OUT;
426 
427 		if (reg & HOTPLUG_CHG)
428 			return DP_IRQ_TYPE_HP_CHANGE;
429 
430 		return DP_IRQ_TYPE_UNKNOWN;
431 	}
432 }
433 
434 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
435 {
436 	u32 reg;
437 
438 	/* Disable AUX channel module */
439 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
440 	reg |= AUX_FUNC_EN_N;
441 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
442 }
443 
444 void analogix_dp_init_aux(struct analogix_dp_device *dp)
445 {
446 	u32 reg;
447 
448 	/* Clear inerrupts related to AUX channel */
449 	reg = RPLY_RECEIV | AUX_ERR;
450 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
451 
452 	analogix_dp_reset_aux(dp);
453 
454 	/* Disable AUX transaction H/W retry */
455 	if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
456 		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
457 		      AUX_HW_RETRY_COUNT_SEL(3) |
458 		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
459 	else
460 		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
461 		      AUX_HW_RETRY_COUNT_SEL(0) |
462 		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
463 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
464 
465 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
466 	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
467 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
468 
469 	/* Enable AUX channel module */
470 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
471 	reg &= ~AUX_FUNC_EN_N;
472 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
473 }
474 
475 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
476 {
477 	u32 reg;
478 
479 	if (gpio_is_valid(dp->hpd_gpio)) {
480 		if (gpio_get_value(dp->hpd_gpio))
481 			return 0;
482 	} else {
483 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
484 		if (reg & HPD_STATUS)
485 			return 0;
486 	}
487 
488 	return -EINVAL;
489 }
490 
491 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
492 {
493 	u32 reg;
494 
495 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
496 	reg &= ~SW_FUNC_EN_N;
497 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
498 }
499 
500 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
501 {
502 	int reg;
503 	int retval = 0;
504 	int timeout_loop = 0;
505 
506 	/* Enable AUX CH operation */
507 	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
508 	reg |= AUX_EN;
509 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
510 
511 	/* Is AUX CH command reply received? */
512 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
513 	while (!(reg & RPLY_RECEIV)) {
514 		timeout_loop++;
515 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
516 			dev_err(dp->dev, "AUX CH command reply failed!\n");
517 			return -ETIMEDOUT;
518 		}
519 		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
520 		usleep_range(10, 11);
521 	}
522 
523 	/* Clear interrupt source for AUX CH command reply */
524 	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
525 
526 	/* Clear interrupt source for AUX CH access error */
527 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
528 	if (reg & AUX_ERR) {
529 		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
530 		return -EREMOTEIO;
531 	}
532 
533 	/* Check AUX CH error access status */
534 	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
535 	if ((reg & AUX_STATUS_MASK) != 0) {
536 		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
537 			reg & AUX_STATUS_MASK);
538 		return -EREMOTEIO;
539 	}
540 
541 	return retval;
542 }
543 
544 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
545 				   unsigned int reg_addr,
546 				   unsigned char data)
547 {
548 	u32 reg;
549 	int i;
550 	int retval;
551 
552 	for (i = 0; i < 3; i++) {
553 		/* Clear AUX CH data buffer */
554 		reg = BUF_CLR;
555 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
556 
557 		/* Select DPCD device address */
558 		reg = AUX_ADDR_7_0(reg_addr);
559 		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
560 		reg = AUX_ADDR_15_8(reg_addr);
561 		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
562 		reg = AUX_ADDR_19_16(reg_addr);
563 		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
564 
565 		/* Write data buffer */
566 		reg = (unsigned int)data;
567 		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
568 
569 		/*
570 		 * Set DisplayPort transaction and write 1 byte
571 		 * If bit 3 is 1, DisplayPort transaction.
572 		 * If Bit 3 is 0, I2C transaction.
573 		 */
574 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
575 		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
576 
577 		/* Start AUX transaction */
578 		retval = analogix_dp_start_aux_transaction(dp);
579 		if (retval == 0)
580 			break;
581 
582 		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
583 	}
584 
585 	return retval;
586 }
587 
588 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
589 {
590 	u32 reg;
591 
592 	reg = bwtype;
593 	if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
594 		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
595 }
596 
597 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
598 {
599 	u32 reg;
600 
601 	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
602 	*bwtype = reg;
603 }
604 
605 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
606 {
607 	u32 reg;
608 
609 	reg = count;
610 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
611 }
612 
613 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
614 {
615 	u32 reg;
616 
617 	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
618 	*count = reg;
619 }
620 
621 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
622 				      bool enable)
623 {
624 	u32 reg;
625 
626 	if (enable) {
627 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
628 		reg |= ENHANCED;
629 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
630 	} else {
631 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
632 		reg &= ~ENHANCED;
633 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
634 	}
635 }
636 
637 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
638 				      enum pattern_set pattern)
639 {
640 	u32 reg;
641 
642 	switch (pattern) {
643 	case PRBS7:
644 		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
645 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
646 		break;
647 	case D10_2:
648 		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
649 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
650 		break;
651 	case TRAINING_PTN1:
652 		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
653 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
654 		break;
655 	case TRAINING_PTN2:
656 		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
657 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
658 		break;
659 	case DP_NONE:
660 		reg = SCRAMBLING_ENABLE |
661 			LINK_QUAL_PATTERN_SET_DISABLE |
662 			SW_TRAINING_PATTERN_SET_NORMAL;
663 		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
664 		break;
665 	default:
666 		break;
667 	}
668 }
669 
670 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
671 					u32 level)
672 {
673 	u32 reg;
674 
675 	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
676 	reg &= ~PRE_EMPHASIS_SET_MASK;
677 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
678 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
679 }
680 
681 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
682 					u32 level)
683 {
684 	u32 reg;
685 
686 	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
687 	reg &= ~PRE_EMPHASIS_SET_MASK;
688 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
689 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
690 }
691 
692 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
693 					u32 level)
694 {
695 	u32 reg;
696 
697 	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
698 	reg &= ~PRE_EMPHASIS_SET_MASK;
699 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
700 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
701 }
702 
703 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
704 					u32 level)
705 {
706 	u32 reg;
707 
708 	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
709 	reg &= ~PRE_EMPHASIS_SET_MASK;
710 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
711 	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
712 }
713 
714 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
715 					 u32 training_lane)
716 {
717 	u32 reg;
718 
719 	reg = training_lane;
720 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
721 }
722 
723 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
724 					 u32 training_lane)
725 {
726 	u32 reg;
727 
728 	reg = training_lane;
729 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
730 }
731 
732 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
733 					 u32 training_lane)
734 {
735 	u32 reg;
736 
737 	reg = training_lane;
738 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
739 }
740 
741 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
742 					 u32 training_lane)
743 {
744 	u32 reg;
745 
746 	reg = training_lane;
747 	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
748 }
749 
750 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
751 {
752 	return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
753 }
754 
755 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
756 {
757 	return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
758 }
759 
760 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
761 {
762 	return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
763 }
764 
765 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
766 {
767 	return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
768 }
769 
770 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
771 {
772 	u32 reg;
773 
774 	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
775 	reg |= MACRO_RST;
776 	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
777 
778 	/* 10 us is the minimum reset time. */
779 	usleep_range(10, 20);
780 
781 	reg &= ~MACRO_RST;
782 	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
783 }
784 
785 void analogix_dp_init_video(struct analogix_dp_device *dp)
786 {
787 	u32 reg;
788 
789 	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
790 	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
791 
792 	reg = 0x0;
793 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
794 
795 	reg = CHA_CRI(4) | CHA_CTRL;
796 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
797 
798 	reg = 0x0;
799 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
800 
801 	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
802 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
803 }
804 
805 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
806 {
807 	u32 reg;
808 
809 	/* Configure the input color depth, color space, dynamic range */
810 	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
811 		(dp->video_info.color_depth << IN_BPC_SHIFT) |
812 		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
813 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
814 
815 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
816 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
817 	reg &= ~IN_YC_COEFFI_MASK;
818 	if (dp->video_info.ycbcr_coeff)
819 		reg |= IN_YC_COEFFI_ITU709;
820 	else
821 		reg |= IN_YC_COEFFI_ITU601;
822 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
823 }
824 
825 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
826 {
827 	u32 reg;
828 
829 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
830 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
831 
832 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
833 
834 	if (!(reg & DET_STA)) {
835 		dev_dbg(dp->dev, "Input stream clock not detected.\n");
836 		return -EINVAL;
837 	}
838 
839 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
840 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
841 
842 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
843 	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
844 
845 	if (reg & CHA_STA) {
846 		dev_dbg(dp->dev, "Input stream clk is changing\n");
847 		return -EINVAL;
848 	}
849 
850 	return 0;
851 }
852 
853 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
854 				 enum clock_recovery_m_value_type type,
855 				 u32 m_value, u32 n_value)
856 {
857 	u32 reg;
858 
859 	if (type == REGISTER_M) {
860 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
861 		reg |= FIX_M_VID;
862 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
863 		reg = m_value & 0xff;
864 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
865 		reg = (m_value >> 8) & 0xff;
866 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
867 		reg = (m_value >> 16) & 0xff;
868 		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
869 
870 		reg = n_value & 0xff;
871 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
872 		reg = (n_value >> 8) & 0xff;
873 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
874 		reg = (n_value >> 16) & 0xff;
875 		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
876 	} else  {
877 		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
878 		reg &= ~FIX_M_VID;
879 		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
880 
881 		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
882 		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
883 		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
884 	}
885 }
886 
887 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
888 {
889 	u32 reg;
890 
891 	if (type == VIDEO_TIMING_FROM_CAPTURE) {
892 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
893 		reg &= ~FORMAT_SEL;
894 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
895 	} else {
896 		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
897 		reg |= FORMAT_SEL;
898 		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
899 	}
900 }
901 
902 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
903 {
904 	u32 reg;
905 
906 	if (enable) {
907 		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
908 		reg &= ~VIDEO_MODE_MASK;
909 		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
910 		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
911 	} else {
912 		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
913 		reg &= ~VIDEO_MODE_MASK;
914 		reg |= VIDEO_MODE_SLAVE_MODE;
915 		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
916 	}
917 }
918 
919 void analogix_dp_start_video(struct analogix_dp_device *dp)
920 {
921 	u32 reg;
922 
923 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
924 	reg |= VIDEO_EN;
925 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
926 }
927 
928 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
929 {
930 	u32 reg;
931 
932 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
933 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
934 
935 	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
936 	if (!(reg & STRM_VALID)) {
937 		dev_dbg(dp->dev, "Input video stream is not detected.\n");
938 		return -EINVAL;
939 	}
940 
941 	return 0;
942 }
943 
944 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
945 {
946 	u32 reg;
947 
948 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
949 	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
950 	reg |= MASTER_VID_FUNC_EN_N;
951 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
952 
953 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
954 	reg &= ~INTERACE_SCAN_CFG;
955 	reg |= (dp->video_info.interlaced << 2);
956 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
957 
958 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
959 	reg &= ~VSYNC_POLARITY_CFG;
960 	reg |= (dp->video_info.v_sync_polarity << 1);
961 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
962 
963 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
964 	reg &= ~HSYNC_POLARITY_CFG;
965 	reg |= (dp->video_info.h_sync_polarity << 0);
966 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
967 
968 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
969 	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
970 }
971 
972 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
973 {
974 	u32 reg;
975 
976 	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
977 	reg &= ~SCRAMBLING_DISABLE;
978 	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
979 }
980 
981 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
982 {
983 	u32 reg;
984 
985 	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
986 	reg |= SCRAMBLING_DISABLE;
987 	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
988 }
989 
990 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
991 {
992 	writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
993 }
994 
995 void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
996 			      struct edp_vsc_psr *vsc)
997 {
998 	unsigned int val;
999 
1000 	/* don't send info frame */
1001 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1002 	val &= ~IF_EN;
1003 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1004 
1005 	/* configure single frame update mode */
1006 	writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE,
1007 	       dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL);
1008 
1009 	/* configure VSC HB0~HB3 */
1010 	writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0);
1011 	writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1);
1012 	writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2);
1013 	writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3);
1014 
1015 	/* configure reused VSC PB0~PB3, magic number from vendor */
1016 	writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
1017 	writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
1018 	writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
1019 	writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
1020 
1021 	/* configure DB0 / DB1 values */
1022 	writel(vsc->DB0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
1023 	writel(vsc->DB1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
1024 
1025 	/* set reuse spd inforframe */
1026 	val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1027 	val |= REUSE_SPD_EN;
1028 	writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1029 
1030 	/* mark info frame update */
1031 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1032 	val = (val | IF_UP) & ~IF_EN;
1033 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1034 
1035 	/* send info frame */
1036 	val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1037 	val |= IF_EN;
1038 	writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1039 }
1040 
1041 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
1042 			     struct drm_dp_aux_msg *msg)
1043 {
1044 	u32 reg;
1045 	u8 *buffer = msg->buffer;
1046 	int timeout_loop = 0;
1047 	unsigned int i;
1048 	int num_transferred = 0;
1049 
1050 	/* Buffer size of AUX CH is 16 bytes */
1051 	if (WARN_ON(msg->size > 16))
1052 		return -E2BIG;
1053 
1054 	/* Clear AUX CH data buffer */
1055 	reg = BUF_CLR;
1056 	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
1057 
1058 	switch (msg->request & ~DP_AUX_I2C_MOT) {
1059 	case DP_AUX_I2C_WRITE:
1060 		reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION;
1061 		if (msg->request & DP_AUX_I2C_MOT)
1062 			reg |= AUX_TX_COMM_MOT;
1063 		break;
1064 
1065 	case DP_AUX_I2C_READ:
1066 		reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION;
1067 		if (msg->request & DP_AUX_I2C_MOT)
1068 			reg |= AUX_TX_COMM_MOT;
1069 		break;
1070 
1071 	case DP_AUX_NATIVE_WRITE:
1072 		reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION;
1073 		break;
1074 
1075 	case DP_AUX_NATIVE_READ:
1076 		reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION;
1077 		break;
1078 
1079 	default:
1080 		return -EINVAL;
1081 	}
1082 
1083 	reg |= AUX_LENGTH(msg->size);
1084 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
1085 
1086 	/* Select DPCD device address */
1087 	reg = AUX_ADDR_7_0(msg->address);
1088 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
1089 	reg = AUX_ADDR_15_8(msg->address);
1090 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
1091 	reg = AUX_ADDR_19_16(msg->address);
1092 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
1093 
1094 	if (!(msg->request & DP_AUX_I2C_READ)) {
1095 		for (i = 0; i < msg->size; i++) {
1096 			reg = buffer[i];
1097 			writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1098 			       4 * i);
1099 			num_transferred++;
1100 		}
1101 	}
1102 
1103 	/* Enable AUX CH operation */
1104 	reg = AUX_EN;
1105 
1106 	/* Zero-sized messages specify address-only transactions. */
1107 	if (msg->size < 1)
1108 		reg |= ADDR_ONLY;
1109 
1110 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
1111 
1112 	/* Is AUX CH command reply received? */
1113 	/* TODO: Wait for an interrupt instead of looping? */
1114 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1115 	while (!(reg & RPLY_RECEIV)) {
1116 		timeout_loop++;
1117 		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
1118 			dev_err(dp->dev, "AUX CH command reply failed!\n");
1119 			return -ETIMEDOUT;
1120 		}
1121 		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1122 		usleep_range(10, 11);
1123 	}
1124 
1125 	/* Clear interrupt source for AUX CH command reply */
1126 	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
1127 
1128 	/* Clear interrupt source for AUX CH access error */
1129 	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1130 	if (reg & AUX_ERR) {
1131 		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
1132 		return -EREMOTEIO;
1133 	}
1134 
1135 	/* Check AUX CH error access status */
1136 	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
1137 	if ((reg & AUX_STATUS_MASK)) {
1138 		dev_err(dp->dev, "AUX CH error happened: %d\n\n",
1139 			reg & AUX_STATUS_MASK);
1140 		return -EREMOTEIO;
1141 	}
1142 
1143 	if (msg->request & DP_AUX_I2C_READ) {
1144 		for (i = 0; i < msg->size; i++) {
1145 			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1146 				    4 * i);
1147 			buffer[i] = (unsigned char)reg;
1148 			num_transferred++;
1149 		}
1150 	}
1151 
1152 	/* Check if Rx sends defer */
1153 	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
1154 	if (reg == AUX_RX_COMM_AUX_DEFER)
1155 		msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1156 	else if (reg == AUX_RX_COMM_I2C_DEFER)
1157 		msg->reply = DP_AUX_I2C_REPLY_DEFER;
1158 	else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
1159 		 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
1160 		msg->reply = DP_AUX_I2C_REPLY_ACK;
1161 	else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
1162 		 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
1163 		msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1164 
1165 	return num_transferred > 0 ? num_transferred : -EBUSY;
1166 }
1167