1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2016, Analogix Semiconductor. 4 * 5 * Based on anx7808 driver obtained from chromeos with copyright: 6 * Copyright(c) 2013, Google Inc. 7 */ 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/types.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_bridge.h> 23 #include <drm/drm_crtc.h> 24 #include <drm/drm_dp_helper.h> 25 #include <drm/drm_edid.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 29 #include "analogix-anx78xx.h" 30 31 #define I2C_NUM_ADDRESSES 5 32 #define I2C_IDX_TX_P0 0 33 #define I2C_IDX_TX_P1 1 34 #define I2C_IDX_TX_P2 2 35 #define I2C_IDX_RX_P0 3 36 #define I2C_IDX_RX_P1 4 37 38 #define XTAL_CLK 270 /* 27M */ 39 #define AUX_CH_BUFFER_SIZE 16 40 #define AUX_WAIT_TIMEOUT_MS 15 41 42 static const u8 anx7808_i2c_addresses[] = { 43 [I2C_IDX_TX_P0] = 0x78, 44 [I2C_IDX_TX_P1] = 0x7a, 45 [I2C_IDX_TX_P2] = 0x72, 46 [I2C_IDX_RX_P0] = 0x7e, 47 [I2C_IDX_RX_P1] = 0x80, 48 }; 49 50 static const u8 anx781x_i2c_addresses[] = { 51 [I2C_IDX_TX_P0] = 0x70, 52 [I2C_IDX_TX_P1] = 0x7a, 53 [I2C_IDX_TX_P2] = 0x72, 54 [I2C_IDX_RX_P0] = 0x7e, 55 [I2C_IDX_RX_P1] = 0x80, 56 }; 57 58 struct anx78xx_platform_data { 59 struct regulator *dvdd10; 60 struct gpio_desc *gpiod_hpd; 61 struct gpio_desc *gpiod_pd; 62 struct gpio_desc *gpiod_reset; 63 64 int hpd_irq; 65 int intp_irq; 66 }; 67 68 struct anx78xx { 69 struct drm_dp_aux aux; 70 struct drm_bridge bridge; 71 struct i2c_client *client; 72 struct edid *edid; 73 struct drm_connector connector; 74 struct anx78xx_platform_data pdata; 75 struct mutex lock; 76 77 /* 78 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2, 79 * RX_P0 and RX_P1. 80 */ 81 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES]; 82 struct regmap *map[I2C_NUM_ADDRESSES]; 83 84 u16 chipid; 85 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 86 87 bool powered; 88 }; 89 90 static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c) 91 { 92 return container_of(c, struct anx78xx, connector); 93 } 94 95 static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge) 96 { 97 return container_of(bridge, struct anx78xx, bridge); 98 } 99 100 static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask) 101 { 102 return regmap_update_bits(map, reg, mask, mask); 103 } 104 105 static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask) 106 { 107 return regmap_update_bits(map, reg, mask, 0); 108 } 109 110 static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx) 111 { 112 unsigned int value; 113 int err; 114 115 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG, 116 &value); 117 if (err < 0) 118 return false; 119 120 return (value & SP_AUX_EN) == 0; 121 } 122 123 static int anx78xx_aux_wait(struct anx78xx *anx78xx) 124 { 125 unsigned long timeout; 126 unsigned int status; 127 int err; 128 129 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1; 130 131 while (!anx78xx_aux_op_finished(anx78xx)) { 132 if (time_after(jiffies, timeout)) { 133 if (!anx78xx_aux_op_finished(anx78xx)) { 134 DRM_ERROR("Timed out waiting AUX to finish\n"); 135 return -ETIMEDOUT; 136 } 137 138 break; 139 } 140 141 usleep_range(1000, 2000); 142 } 143 144 /* Read the AUX channel access status */ 145 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG, 146 &status); 147 if (err < 0) { 148 DRM_ERROR("Failed to read from AUX channel: %d\n", err); 149 return err; 150 } 151 152 if (status & SP_AUX_STATUS) { 153 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n", 154 status); 155 return -ETIMEDOUT; 156 } 157 158 return 0; 159 } 160 161 static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr) 162 { 163 int err; 164 165 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG, 166 addr & 0xff); 167 if (err) 168 return err; 169 170 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG, 171 (addr & 0xff00) >> 8); 172 if (err) 173 return err; 174 175 /* 176 * DP AUX CH Address Register #2, only update bits[3:0] 177 * [7:4] RESERVED 178 * [3:0] AUX_ADDR[19:16], Register control AUX CH address. 179 */ 180 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0], 181 SP_AUX_ADDR_19_16_REG, 182 SP_AUX_ADDR_19_16_MASK, 183 (addr & 0xf0000) >> 16); 184 185 if (err) 186 return err; 187 188 return 0; 189 } 190 191 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux, 192 struct drm_dp_aux_msg *msg) 193 { 194 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux); 195 u8 ctrl1 = msg->request; 196 u8 ctrl2 = SP_AUX_EN; 197 u8 *buffer = msg->buffer; 198 int err; 199 200 /* The DP AUX transmit and receive buffer has 16 bytes. */ 201 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE)) 202 return -E2BIG; 203 204 /* Zero-sized messages specify address-only transactions. */ 205 if (msg->size < 1) 206 ctrl2 |= SP_ADDR_ONLY; 207 else /* For non-zero-sized set the length field. */ 208 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT; 209 210 if ((msg->request & DP_AUX_I2C_READ) == 0) { 211 /* When WRITE | MOT write values to data buffer */ 212 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0], 213 SP_DP_BUF_DATA0_REG, buffer, 214 msg->size); 215 if (err) 216 return err; 217 } 218 219 /* Write address and request */ 220 err = anx78xx_aux_address(anx78xx, msg->address); 221 if (err) 222 return err; 223 224 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG, 225 ctrl1); 226 if (err) 227 return err; 228 229 /* Start transaction */ 230 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0], 231 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY | 232 SP_AUX_EN, ctrl2); 233 if (err) 234 return err; 235 236 err = anx78xx_aux_wait(anx78xx); 237 if (err) 238 return err; 239 240 msg->reply = DP_AUX_I2C_REPLY_ACK; 241 242 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) { 243 /* Read values from data buffer */ 244 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0], 245 SP_DP_BUF_DATA0_REG, buffer, 246 msg->size); 247 if (err) 248 return err; 249 } 250 251 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 252 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY); 253 if (err) 254 return err; 255 256 return msg->size; 257 } 258 259 static int anx78xx_set_hpd(struct anx78xx *anx78xx) 260 { 261 int err; 262 263 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 264 SP_TMDS_CTRL_BASE + 7, SP_PD_RT); 265 if (err) 266 return err; 267 268 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, 269 SP_HPD_OUT); 270 if (err) 271 return err; 272 273 return 0; 274 } 275 276 static int anx78xx_clear_hpd(struct anx78xx *anx78xx) 277 { 278 int err; 279 280 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG, 281 SP_HPD_OUT); 282 if (err) 283 return err; 284 285 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 286 SP_TMDS_CTRL_BASE + 7, SP_PD_RT); 287 if (err) 288 return err; 289 290 return 0; 291 } 292 293 static const struct reg_sequence tmds_phy_initialization[] = { 294 { SP_TMDS_CTRL_BASE + 1, 0x90 }, 295 { SP_TMDS_CTRL_BASE + 2, 0xa9 }, 296 { SP_TMDS_CTRL_BASE + 6, 0x92 }, 297 { SP_TMDS_CTRL_BASE + 7, 0x80 }, 298 { SP_TMDS_CTRL_BASE + 20, 0xf2 }, 299 { SP_TMDS_CTRL_BASE + 22, 0xc4 }, 300 { SP_TMDS_CTRL_BASE + 23, 0x18 }, 301 }; 302 303 static int anx78xx_rx_initialization(struct anx78xx *anx78xx) 304 { 305 int err; 306 307 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, 308 SP_AUD_MUTE | SP_VID_MUTE); 309 if (err) 310 return err; 311 312 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG, 313 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN | 314 SP_DIGITAL_CKDT_EN); 315 if (err) 316 return err; 317 318 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 319 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | 320 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); 321 if (err) 322 return err; 323 324 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 325 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST | 326 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST); 327 if (err) 328 return err; 329 330 /* Sync detect change, GP set mute */ 331 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 332 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) | 333 BIT(6)); 334 if (err) 335 return err; 336 337 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 338 SP_AUD_EXCEPTION_ENABLE_BASE + 3, 339 SP_AEC_EN21); 340 if (err) 341 return err; 342 343 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG, 344 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN); 345 if (err) 346 return err; 347 348 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0], 349 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL); 350 if (err) 351 return err; 352 353 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], 354 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT); 355 if (err) 356 return err; 357 358 /* Enable DDC stretch */ 359 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 360 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR); 361 if (err) 362 return err; 363 364 /* TMDS phy initialization */ 365 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0], 366 tmds_phy_initialization, 367 ARRAY_SIZE(tmds_phy_initialization)); 368 if (err) 369 return err; 370 371 err = anx78xx_clear_hpd(anx78xx); 372 if (err) 373 return err; 374 375 return 0; 376 } 377 378 static const u8 dp_tx_output_precise_tune_bits[20] = { 379 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f, 380 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 381 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e, 382 }; 383 384 static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx) 385 { 386 int err; 387 388 /* 389 * REVISIT : It is writing to a RESERVED bits in Analog Control 0 390 * register. 391 */ 392 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG, 393 0x02); 394 if (err) 395 return err; 396 397 /* 398 * Write DP TX output emphasis precise tune bits. 399 */ 400 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1], 401 SP_DP_TX_LT_CTRL0_REG, 402 dp_tx_output_precise_tune_bits, 403 ARRAY_SIZE(dp_tx_output_precise_tune_bits)); 404 405 if (err) 406 return err; 407 408 return 0; 409 } 410 411 static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx) 412 { 413 unsigned int value; 414 int err; 415 416 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2], 417 SP_ANALOG_DEBUG2_REG, 418 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS, 419 SP_XTAL_FRQ_27M); 420 if (err) 421 return err; 422 423 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG, 424 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK); 425 if (err) 426 return err; 427 428 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG, 429 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10)); 430 if (err) 431 return err; 432 433 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 434 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff); 435 if (err) 436 return err; 437 438 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 439 SP_I2C_GEN_10US_TIMER1_REG, 440 (XTAL_CLK & 0xff00) >> 8); 441 if (err) 442 return err; 443 444 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG, 445 XTAL_CLK / 10 - 1); 446 if (err) 447 return err; 448 449 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], 450 SP_HDMI_US_TIMER_CTRL_REG, 451 &value); 452 if (err) 453 return err; 454 455 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], 456 SP_HDMI_US_TIMER_CTRL_REG, 457 (value & SP_MS_TIMER_MARGIN_10_8_MASK) | 458 ((((XTAL_CLK / 10) >> 1) - 2) << 3)); 459 if (err) 460 return err; 461 462 return 0; 463 } 464 465 static const struct reg_sequence otp_key_protect[] = { 466 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 }, 467 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 }, 468 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 }, 469 }; 470 471 static int anx78xx_tx_initialization(struct anx78xx *anx78xx) 472 { 473 int err; 474 475 /* Set terminal resistor to 50 ohm */ 476 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG, 477 0x30); 478 if (err) 479 return err; 480 481 /* Enable aux double diff output */ 482 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 483 SP_DP_AUX_CH_CTRL2_REG, 0x08); 484 if (err) 485 return err; 486 487 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 488 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN | 489 SP_AUTO_START); 490 if (err) 491 return err; 492 493 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0], 494 otp_key_protect, 495 ARRAY_SIZE(otp_key_protect)); 496 if (err) 497 return err; 498 499 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 500 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP); 501 if (err) 502 return err; 503 504 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG, 505 SP_VID_VRES_TH); 506 if (err) 507 return err; 508 509 /* 510 * DP HDCP auto authentication wait timer (when downstream starts to 511 * auth, DP side will wait for this period then do auth automatically) 512 */ 513 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG, 514 0x00); 515 if (err) 516 return err; 517 518 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 519 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING); 520 if (err) 521 return err; 522 523 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 524 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG); 525 if (err) 526 return err; 527 528 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], 529 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS); 530 if (err) 531 return err; 532 533 err = anx78xx_xtal_clk_sel(anx78xx); 534 if (err) 535 return err; 536 537 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG, 538 SP_DEFER_CTRL_EN | 0x0c); 539 if (err) 540 return err; 541 542 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 543 SP_DP_POLLING_CTRL_REG, 544 SP_AUTO_POLLING_DISABLE); 545 if (err) 546 return err; 547 548 /* 549 * Short the link integrity check timer to speed up bstatus 550 * polling for HDCP CTS item 1A-07 551 */ 552 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 553 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d); 554 if (err) 555 return err; 556 557 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 558 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP); 559 if (err) 560 return err; 561 562 /* Power down the main link by default */ 563 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 564 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); 565 if (err) 566 return err; 567 568 err = anx78xx_link_phy_initialization(anx78xx); 569 if (err) 570 return err; 571 572 /* Gen m_clk with downspreading */ 573 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 574 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL); 575 if (err) 576 return err; 577 578 return 0; 579 } 580 581 static int anx78xx_enable_interrupts(struct anx78xx *anx78xx) 582 { 583 int err; 584 585 /* 586 * BIT0: INT pin assertion polarity: 1 = assert high 587 * BIT1: INT pin output type: 0 = push/pull 588 */ 589 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01); 590 if (err) 591 return err; 592 593 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], 594 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG); 595 if (err) 596 return err; 597 598 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG, 599 SP_TRAINING_FINISH); 600 if (err) 601 return err; 602 603 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG, 604 SP_CKDT_CHG | SP_SCDT_CHG); 605 if (err) 606 return err; 607 608 return 0; 609 } 610 611 static void anx78xx_poweron(struct anx78xx *anx78xx) 612 { 613 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 614 int err; 615 616 if (WARN_ON(anx78xx->powered)) 617 return; 618 619 if (pdata->dvdd10) { 620 err = regulator_enable(pdata->dvdd10); 621 if (err) { 622 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n", 623 err); 624 return; 625 } 626 627 usleep_range(1000, 2000); 628 } 629 630 gpiod_set_value_cansleep(pdata->gpiod_reset, 1); 631 usleep_range(1000, 2000); 632 633 gpiod_set_value_cansleep(pdata->gpiod_pd, 0); 634 usleep_range(1000, 2000); 635 636 gpiod_set_value_cansleep(pdata->gpiod_reset, 0); 637 638 /* Power on registers module */ 639 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 640 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 641 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 642 SP_REGISTER_PD | SP_TOTAL_PD); 643 644 anx78xx->powered = true; 645 } 646 647 static void anx78xx_poweroff(struct anx78xx *anx78xx) 648 { 649 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 650 int err; 651 652 if (WARN_ON(!anx78xx->powered)) 653 return; 654 655 gpiod_set_value_cansleep(pdata->gpiod_reset, 1); 656 usleep_range(1000, 2000); 657 658 gpiod_set_value_cansleep(pdata->gpiod_pd, 1); 659 usleep_range(1000, 2000); 660 661 if (pdata->dvdd10) { 662 err = regulator_disable(pdata->dvdd10); 663 if (err) { 664 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n", 665 err); 666 return; 667 } 668 669 usleep_range(1000, 2000); 670 } 671 672 anx78xx->powered = false; 673 } 674 675 static int anx78xx_start(struct anx78xx *anx78xx) 676 { 677 int err; 678 679 /* Power on all modules */ 680 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 681 SP_POWERDOWN_CTRL_REG, 682 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | 683 SP_LINK_PD); 684 685 err = anx78xx_enable_interrupts(anx78xx); 686 if (err) { 687 DRM_ERROR("Failed to enable interrupts: %d\n", err); 688 goto err_poweroff; 689 } 690 691 err = anx78xx_rx_initialization(anx78xx); 692 if (err) { 693 DRM_ERROR("Failed receiver initialization: %d\n", err); 694 goto err_poweroff; 695 } 696 697 err = anx78xx_tx_initialization(anx78xx); 698 if (err) { 699 DRM_ERROR("Failed transmitter initialization: %d\n", err); 700 goto err_poweroff; 701 } 702 703 /* 704 * This delay seems to help keep the hardware in a good state. Without 705 * it, there are times where it fails silently. 706 */ 707 usleep_range(10000, 15000); 708 709 return 0; 710 711 err_poweroff: 712 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err); 713 anx78xx_poweroff(anx78xx); 714 715 return err; 716 } 717 718 static int anx78xx_init_pdata(struct anx78xx *anx78xx) 719 { 720 struct anx78xx_platform_data *pdata = &anx78xx->pdata; 721 struct device *dev = &anx78xx->client->dev; 722 723 /* 1.0V digital core power regulator */ 724 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10"); 725 if (IS_ERR(pdata->dvdd10)) { 726 if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER) 727 DRM_ERROR("DVDD10 regulator not found\n"); 728 729 return PTR_ERR(pdata->dvdd10); 730 } 731 732 /* GPIO for HPD */ 733 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN); 734 if (IS_ERR(pdata->gpiod_hpd)) 735 return PTR_ERR(pdata->gpiod_hpd); 736 737 /* GPIO for chip power down */ 738 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH); 739 if (IS_ERR(pdata->gpiod_pd)) 740 return PTR_ERR(pdata->gpiod_pd); 741 742 /* GPIO for chip reset */ 743 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 744 745 return PTR_ERR_OR_ZERO(pdata->gpiod_reset); 746 } 747 748 static int anx78xx_dp_link_training(struct anx78xx *anx78xx) 749 { 750 u8 dp_bw, dpcd[2]; 751 int err; 752 753 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG, 754 0x0); 755 if (err) 756 return err; 757 758 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 759 SP_POWERDOWN_CTRL_REG, 760 SP_TOTAL_PD); 761 if (err) 762 return err; 763 764 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw); 765 if (err < 0) 766 return err; 767 768 switch (dp_bw) { 769 case DP_LINK_BW_1_62: 770 case DP_LINK_BW_2_7: 771 case DP_LINK_BW_5_4: 772 break; 773 774 default: 775 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw); 776 return -EINVAL; 777 } 778 779 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 780 SP_VIDEO_MUTE); 781 if (err) 782 return err; 783 784 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], 785 SP_VID_CTRL1_REG, SP_VIDEO_EN); 786 if (err) 787 return err; 788 789 /* Get DPCD info */ 790 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV, 791 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); 792 if (err < 0) { 793 DRM_ERROR("Failed to read DPCD: %d\n", err); 794 return err; 795 } 796 797 /* Clear channel x SERDES power down */ 798 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 799 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD); 800 if (err) 801 return err; 802 803 /* 804 * Power up the sink (DP_SET_POWER register is only available on DPCD 805 * v1.1 and later). 806 */ 807 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { 808 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); 809 if (err < 0) { 810 DRM_ERROR("Failed to read DP_SET_POWER register: %d\n", 811 err); 812 return err; 813 } 814 815 dpcd[0] &= ~DP_SET_POWER_MASK; 816 dpcd[0] |= DP_SET_POWER_D0; 817 818 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]); 819 if (err < 0) { 820 DRM_ERROR("Failed to power up DisplayPort link: %d\n", 821 err); 822 return err; 823 } 824 825 /* 826 * According to the DP 1.1 specification, a "Sink Device must 827 * exit the power saving state within 1 ms" (Section 2.5.3.1, 828 * Table 5-52, "Sink Control Field" (register 0x600). 829 */ 830 usleep_range(1000, 2000); 831 } 832 833 /* Possibly enable downspread on the sink */ 834 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 835 SP_DP_DOWNSPREAD_CTRL1_REG, 0); 836 if (err) 837 return err; 838 839 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { 840 DRM_DEBUG("Enable downspread on the sink\n"); 841 /* 4000PPM */ 842 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 843 SP_DP_DOWNSPREAD_CTRL1_REG, 8); 844 if (err) 845 return err; 846 847 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 848 DP_SPREAD_AMP_0_5); 849 if (err < 0) 850 return err; 851 } else { 852 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0); 853 if (err < 0) 854 return err; 855 } 856 857 /* Set the lane count and the link rate on the sink */ 858 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) 859 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 860 SP_DP_SYSTEM_CTRL_BASE + 4, 861 SP_ENHANCED_MODE); 862 else 863 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 864 SP_DP_SYSTEM_CTRL_BASE + 4, 865 SP_ENHANCED_MODE); 866 if (err) 867 return err; 868 869 dpcd[0] = drm_dp_max_link_rate(anx78xx->dpcd); 870 dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]); 871 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], 872 SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); 873 if (err) 874 return err; 875 876 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); 877 878 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) 879 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 880 881 err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd, 882 sizeof(dpcd)); 883 if (err < 0) { 884 DRM_ERROR("Failed to configure link: %d\n", err); 885 return err; 886 } 887 888 /* Start training on the source */ 889 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG, 890 SP_LT_EN); 891 if (err) 892 return err; 893 894 return 0; 895 } 896 897 static int anx78xx_config_dp_output(struct anx78xx *anx78xx) 898 { 899 int err; 900 901 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 902 SP_VIDEO_MUTE); 903 if (err) 904 return err; 905 906 /* Enable DP output */ 907 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG, 908 SP_VIDEO_EN); 909 if (err) 910 return err; 911 912 return 0; 913 } 914 915 static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx, 916 struct hdmi_avi_infoframe *frame) 917 { 918 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 919 int err; 920 921 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer)); 922 if (err < 0) { 923 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err); 924 return err; 925 } 926 927 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0], 928 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); 929 if (err) 930 return err; 931 932 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2], 933 SP_INFOFRAME_AVI_DB1_REG, buffer, 934 frame->length); 935 if (err) 936 return err; 937 938 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 939 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD); 940 if (err) 941 return err; 942 943 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0], 944 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN); 945 if (err) 946 return err; 947 948 return 0; 949 } 950 951 static int anx78xx_get_downstream_info(struct anx78xx *anx78xx) 952 { 953 u8 value; 954 int err; 955 956 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value); 957 if (err < 0) { 958 DRM_ERROR("Get sink count failed %d\n", err); 959 return err; 960 } 961 962 if (!DP_GET_SINK_COUNT(value)) { 963 DRM_ERROR("Downstream disconnected\n"); 964 return -EIO; 965 } 966 967 return 0; 968 } 969 970 static int anx78xx_get_modes(struct drm_connector *connector) 971 { 972 struct anx78xx *anx78xx = connector_to_anx78xx(connector); 973 int err, num_modes = 0; 974 975 if (WARN_ON(!anx78xx->powered)) 976 return 0; 977 978 if (anx78xx->edid) 979 return drm_add_edid_modes(connector, anx78xx->edid); 980 981 mutex_lock(&anx78xx->lock); 982 983 err = anx78xx_get_downstream_info(anx78xx); 984 if (err) { 985 DRM_ERROR("Failed to get downstream info: %d\n", err); 986 goto unlock; 987 } 988 989 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc); 990 if (!anx78xx->edid) { 991 DRM_ERROR("Failed to read EDID\n"); 992 goto unlock; 993 } 994 995 err = drm_connector_update_edid_property(connector, 996 anx78xx->edid); 997 if (err) { 998 DRM_ERROR("Failed to update EDID property: %d\n", err); 999 goto unlock; 1000 } 1001 1002 num_modes = drm_add_edid_modes(connector, anx78xx->edid); 1003 1004 unlock: 1005 mutex_unlock(&anx78xx->lock); 1006 1007 return num_modes; 1008 } 1009 1010 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = { 1011 .get_modes = anx78xx_get_modes, 1012 }; 1013 1014 static enum drm_connector_status anx78xx_detect(struct drm_connector *connector, 1015 bool force) 1016 { 1017 struct anx78xx *anx78xx = connector_to_anx78xx(connector); 1018 1019 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) 1020 return connector_status_disconnected; 1021 1022 return connector_status_connected; 1023 } 1024 1025 static const struct drm_connector_funcs anx78xx_connector_funcs = { 1026 .fill_modes = drm_helper_probe_single_connector_modes, 1027 .detect = anx78xx_detect, 1028 .destroy = drm_connector_cleanup, 1029 .reset = drm_atomic_helper_connector_reset, 1030 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1031 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1032 }; 1033 1034 static int anx78xx_bridge_attach(struct drm_bridge *bridge) 1035 { 1036 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 1037 int err; 1038 1039 if (!bridge->encoder) { 1040 DRM_ERROR("Parent encoder object not found"); 1041 return -ENODEV; 1042 } 1043 1044 /* Register aux channel */ 1045 anx78xx->aux.name = "DP-AUX"; 1046 anx78xx->aux.dev = &anx78xx->client->dev; 1047 anx78xx->aux.transfer = anx78xx_aux_transfer; 1048 1049 err = drm_dp_aux_register(&anx78xx->aux); 1050 if (err < 0) { 1051 DRM_ERROR("Failed to register aux channel: %d\n", err); 1052 return err; 1053 } 1054 1055 err = drm_connector_init(bridge->dev, &anx78xx->connector, 1056 &anx78xx_connector_funcs, 1057 DRM_MODE_CONNECTOR_DisplayPort); 1058 if (err) { 1059 DRM_ERROR("Failed to initialize connector: %d\n", err); 1060 return err; 1061 } 1062 1063 drm_connector_helper_add(&anx78xx->connector, 1064 &anx78xx_connector_helper_funcs); 1065 1066 err = drm_connector_register(&anx78xx->connector); 1067 if (err) { 1068 DRM_ERROR("Failed to register connector: %d\n", err); 1069 return err; 1070 } 1071 1072 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD; 1073 1074 err = drm_connector_attach_encoder(&anx78xx->connector, 1075 bridge->encoder); 1076 if (err) { 1077 DRM_ERROR("Failed to link up connector to encoder: %d\n", err); 1078 return err; 1079 } 1080 1081 return 0; 1082 } 1083 1084 static enum drm_mode_status 1085 anx78xx_bridge_mode_valid(struct drm_bridge *bridge, 1086 const struct drm_display_mode *mode) 1087 { 1088 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1089 return MODE_NO_INTERLACE; 1090 1091 /* Max 1200p at 5.4 Ghz, one lane */ 1092 if (mode->clock > 154000) 1093 return MODE_CLOCK_HIGH; 1094 1095 return MODE_OK; 1096 } 1097 1098 static void anx78xx_bridge_disable(struct drm_bridge *bridge) 1099 { 1100 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 1101 1102 /* Power off all modules except configuration registers access */ 1103 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG, 1104 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD); 1105 } 1106 1107 static void anx78xx_bridge_mode_set(struct drm_bridge *bridge, 1108 const struct drm_display_mode *mode, 1109 const struct drm_display_mode *adjusted_mode) 1110 { 1111 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 1112 struct hdmi_avi_infoframe frame; 1113 int err; 1114 1115 if (WARN_ON(!anx78xx->powered)) 1116 return; 1117 1118 mutex_lock(&anx78xx->lock); 1119 1120 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 1121 &anx78xx->connector, 1122 adjusted_mode); 1123 if (err) { 1124 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err); 1125 goto unlock; 1126 } 1127 1128 err = anx78xx_send_video_infoframe(anx78xx, &frame); 1129 if (err) 1130 DRM_ERROR("Failed to send AVI infoframe: %d\n", err); 1131 1132 unlock: 1133 mutex_unlock(&anx78xx->lock); 1134 } 1135 1136 static void anx78xx_bridge_enable(struct drm_bridge *bridge) 1137 { 1138 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge); 1139 int err; 1140 1141 err = anx78xx_start(anx78xx); 1142 if (err) { 1143 DRM_ERROR("Failed to initialize: %d\n", err); 1144 return; 1145 } 1146 1147 err = anx78xx_set_hpd(anx78xx); 1148 if (err) 1149 DRM_ERROR("Failed to set HPD: %d\n", err); 1150 } 1151 1152 static const struct drm_bridge_funcs anx78xx_bridge_funcs = { 1153 .attach = anx78xx_bridge_attach, 1154 .mode_valid = anx78xx_bridge_mode_valid, 1155 .disable = anx78xx_bridge_disable, 1156 .mode_set = anx78xx_bridge_mode_set, 1157 .enable = anx78xx_bridge_enable, 1158 }; 1159 1160 static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data) 1161 { 1162 struct anx78xx *anx78xx = data; 1163 int err; 1164 1165 if (anx78xx->powered) 1166 return IRQ_HANDLED; 1167 1168 mutex_lock(&anx78xx->lock); 1169 1170 /* Cable is pulled, power on the chip */ 1171 anx78xx_poweron(anx78xx); 1172 1173 err = anx78xx_enable_interrupts(anx78xx); 1174 if (err) 1175 DRM_ERROR("Failed to enable interrupts: %d\n", err); 1176 1177 mutex_unlock(&anx78xx->lock); 1178 1179 return IRQ_HANDLED; 1180 } 1181 1182 static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq) 1183 { 1184 int err; 1185 1186 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq); 1187 1188 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, 1189 irq); 1190 if (err) 1191 return err; 1192 1193 if (irq & SP_TRAINING_FINISH) { 1194 DRM_DEBUG_KMS("IRQ: hardware link training finished\n"); 1195 err = anx78xx_config_dp_output(anx78xx); 1196 } 1197 1198 return err; 1199 } 1200 1201 static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq) 1202 { 1203 bool event = false; 1204 int err; 1205 1206 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq); 1207 1208 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], 1209 SP_COMMON_INT_STATUS4_REG, irq); 1210 if (err) { 1211 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err); 1212 return event; 1213 } 1214 1215 if (irq & SP_HPD_LOST) { 1216 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n"); 1217 event = true; 1218 anx78xx_poweroff(anx78xx); 1219 /* Free cached EDID */ 1220 kfree(anx78xx->edid); 1221 anx78xx->edid = NULL; 1222 } else if (irq & SP_HPD_PLUG) { 1223 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n"); 1224 event = true; 1225 } 1226 1227 return event; 1228 } 1229 1230 static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq) 1231 { 1232 unsigned int value; 1233 int err; 1234 1235 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq); 1236 1237 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, 1238 irq); 1239 if (err) { 1240 DRM_ERROR("Write HDMI int 1 failed: %d\n", err); 1241 return; 1242 } 1243 1244 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) { 1245 DRM_DEBUG_KMS("IRQ: HDMI input detected\n"); 1246 1247 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], 1248 SP_SYSTEM_STATUS_REG, &value); 1249 if (err) { 1250 DRM_ERROR("Read system status reg failed: %d\n", err); 1251 return; 1252 } 1253 1254 if (!(value & SP_TMDS_CLOCK_DET)) { 1255 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n"); 1256 return; 1257 } 1258 1259 if (!(value & SP_TMDS_DE_DET)) { 1260 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n"); 1261 return; 1262 } 1263 1264 err = anx78xx_dp_link_training(anx78xx); 1265 if (err) 1266 DRM_ERROR("Failed to start link training: %d\n", err); 1267 } 1268 } 1269 1270 static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data) 1271 { 1272 struct anx78xx *anx78xx = data; 1273 bool event = false; 1274 unsigned int irq; 1275 int err; 1276 1277 mutex_lock(&anx78xx->lock); 1278 1279 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG, 1280 &irq); 1281 if (err) { 1282 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err); 1283 goto unlock; 1284 } 1285 1286 if (irq) 1287 anx78xx_handle_dp_int_1(anx78xx, irq); 1288 1289 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], 1290 SP_COMMON_INT_STATUS4_REG, &irq); 1291 if (err) { 1292 DRM_ERROR("Failed to read common interrupt 4 status: %d\n", 1293 err); 1294 goto unlock; 1295 } 1296 1297 if (irq) 1298 event = anx78xx_handle_common_int_4(anx78xx, irq); 1299 1300 /* Make sure we are still powered after handle HPD events */ 1301 if (!anx78xx->powered) 1302 goto unlock; 1303 1304 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG, 1305 &irq); 1306 if (err) { 1307 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err); 1308 goto unlock; 1309 } 1310 1311 if (irq) 1312 anx78xx_handle_hdmi_int_1(anx78xx, irq); 1313 1314 unlock: 1315 mutex_unlock(&anx78xx->lock); 1316 1317 if (event) 1318 drm_helper_hpd_irq_event(anx78xx->connector.dev); 1319 1320 return IRQ_HANDLED; 1321 } 1322 1323 static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx) 1324 { 1325 unsigned int i; 1326 1327 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++) 1328 i2c_unregister_device(anx78xx->i2c_dummy[i]); 1329 } 1330 1331 static const struct regmap_config anx78xx_regmap_config = { 1332 .reg_bits = 8, 1333 .val_bits = 8, 1334 }; 1335 1336 static const u16 anx78xx_chipid_list[] = { 1337 0x7808, 1338 0x7812, 1339 0x7814, 1340 0x7818, 1341 }; 1342 1343 static int anx78xx_i2c_probe(struct i2c_client *client, 1344 const struct i2c_device_id *id) 1345 { 1346 struct anx78xx *anx78xx; 1347 struct anx78xx_platform_data *pdata; 1348 unsigned int i, idl, idh, version; 1349 const u8 *i2c_addresses; 1350 bool found = false; 1351 int err; 1352 1353 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL); 1354 if (!anx78xx) 1355 return -ENOMEM; 1356 1357 pdata = &anx78xx->pdata; 1358 1359 mutex_init(&anx78xx->lock); 1360 1361 #if IS_ENABLED(CONFIG_OF) 1362 anx78xx->bridge.of_node = client->dev.of_node; 1363 #endif 1364 1365 anx78xx->client = client; 1366 i2c_set_clientdata(client, anx78xx); 1367 1368 err = anx78xx_init_pdata(anx78xx); 1369 if (err) { 1370 if (err != -EPROBE_DEFER) 1371 DRM_ERROR("Failed to initialize pdata: %d\n", err); 1372 1373 return err; 1374 } 1375 1376 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd); 1377 if (pdata->hpd_irq < 0) { 1378 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq); 1379 return -ENODEV; 1380 } 1381 1382 pdata->intp_irq = client->irq; 1383 if (!pdata->intp_irq) { 1384 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n"); 1385 return -ENODEV; 1386 } 1387 1388 /* Map slave addresses of ANX7814 */ 1389 i2c_addresses = device_get_match_data(&client->dev); 1390 for (i = 0; i < I2C_NUM_ADDRESSES; i++) { 1391 struct i2c_client *i2c_dummy; 1392 1393 i2c_dummy = i2c_new_dummy_device(client->adapter, 1394 i2c_addresses[i] >> 1); 1395 if (IS_ERR(i2c_dummy)) { 1396 err = PTR_ERR(i2c_dummy); 1397 DRM_ERROR("Failed to reserve I2C bus %02x: %d\n", 1398 i2c_addresses[i], err); 1399 goto err_unregister_i2c; 1400 } 1401 1402 anx78xx->i2c_dummy[i] = i2c_dummy; 1403 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i], 1404 &anx78xx_regmap_config); 1405 if (IS_ERR(anx78xx->map[i])) { 1406 err = PTR_ERR(anx78xx->map[i]); 1407 DRM_ERROR("Failed regmap initialization %02x\n", 1408 i2c_addresses[i]); 1409 goto err_unregister_i2c; 1410 } 1411 } 1412 1413 /* Look for supported chip ID */ 1414 anx78xx_poweron(anx78xx); 1415 1416 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG, 1417 &idl); 1418 if (err) 1419 goto err_poweroff; 1420 1421 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG, 1422 &idh); 1423 if (err) 1424 goto err_poweroff; 1425 1426 anx78xx->chipid = (u8)idl | ((u8)idh << 8); 1427 1428 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG, 1429 &version); 1430 if (err) 1431 goto err_poweroff; 1432 1433 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) { 1434 if (anx78xx->chipid == anx78xx_chipid_list[i]) { 1435 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n", 1436 anx78xx->chipid, version); 1437 found = true; 1438 break; 1439 } 1440 } 1441 1442 if (!found) { 1443 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n", 1444 anx78xx->chipid, version); 1445 err = -ENODEV; 1446 goto err_poweroff; 1447 } 1448 1449 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL, 1450 anx78xx_hpd_threaded_handler, 1451 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1452 "anx78xx-hpd", anx78xx); 1453 if (err) { 1454 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n", 1455 err); 1456 goto err_poweroff; 1457 } 1458 1459 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL, 1460 anx78xx_intp_threaded_handler, 1461 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 1462 "anx78xx-intp", anx78xx); 1463 if (err) { 1464 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err); 1465 goto err_poweroff; 1466 } 1467 1468 anx78xx->bridge.funcs = &anx78xx_bridge_funcs; 1469 1470 drm_bridge_add(&anx78xx->bridge); 1471 1472 /* If cable is pulled out, just poweroff and wait for HPD event */ 1473 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd)) 1474 anx78xx_poweroff(anx78xx); 1475 1476 return 0; 1477 1478 err_poweroff: 1479 anx78xx_poweroff(anx78xx); 1480 1481 err_unregister_i2c: 1482 unregister_i2c_dummy_clients(anx78xx); 1483 return err; 1484 } 1485 1486 static int anx78xx_i2c_remove(struct i2c_client *client) 1487 { 1488 struct anx78xx *anx78xx = i2c_get_clientdata(client); 1489 1490 drm_bridge_remove(&anx78xx->bridge); 1491 1492 unregister_i2c_dummy_clients(anx78xx); 1493 1494 kfree(anx78xx->edid); 1495 1496 return 0; 1497 } 1498 1499 static const struct i2c_device_id anx78xx_id[] = { 1500 { "anx7814", 0 }, 1501 { /* sentinel */ } 1502 }; 1503 MODULE_DEVICE_TABLE(i2c, anx78xx_id); 1504 1505 #if IS_ENABLED(CONFIG_OF) 1506 static const struct of_device_id anx78xx_match_table[] = { 1507 { .compatible = "analogix,anx7808", .data = anx7808_i2c_addresses }, 1508 { .compatible = "analogix,anx7812", .data = anx781x_i2c_addresses }, 1509 { .compatible = "analogix,anx7814", .data = anx781x_i2c_addresses }, 1510 { .compatible = "analogix,anx7818", .data = anx781x_i2c_addresses }, 1511 { /* sentinel */ }, 1512 }; 1513 MODULE_DEVICE_TABLE(of, anx78xx_match_table); 1514 #endif 1515 1516 static struct i2c_driver anx78xx_driver = { 1517 .driver = { 1518 .name = "anx7814", 1519 .of_match_table = of_match_ptr(anx78xx_match_table), 1520 }, 1521 .probe = anx78xx_i2c_probe, 1522 .remove = anx78xx_i2c_remove, 1523 .id_table = anx78xx_id, 1524 }; 1525 module_i2c_driver(anx78xx_driver); 1526 1527 MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver"); 1528 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>"); 1529 MODULE_LICENSE("GPL v2"); 1530