1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v11_0.h" 33 #include "smu11_driver_if_arcturus.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "arcturus_ppt.h" 38 #include "smu_v11_0_pptable.h" 39 #include "arcturus_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/i2c.h> 46 #include <linux/pci.h> 47 #include "amdgpu_ras.h" 48 #include "smu_cmn.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \ 63 [smu_feature] = {1, (arcturus_feature)} 64 65 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 66 #define SMU_FEATURES_LOW_SHIFT 0 67 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 68 #define SMU_FEATURES_HIGH_SHIFT 32 69 70 #define SMC_DPM_FEATURE ( \ 71 FEATURE_DPM_PREFETCHER_MASK | \ 72 FEATURE_DPM_GFXCLK_MASK | \ 73 FEATURE_DPM_UCLK_MASK | \ 74 FEATURE_DPM_SOCCLK_MASK | \ 75 FEATURE_DPM_MP0CLK_MASK | \ 76 FEATURE_DPM_FCLK_MASK | \ 77 FEATURE_DPM_XGMI_MASK) 78 79 /* possible frequency drift (1Mhz) */ 80 #define EPSILON 1 81 82 #define smnPCIE_ESM_CTRL 0x111003D0 83 84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = { 85 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 86 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 87 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 88 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 89 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 90 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 91 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 92 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 93 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 94 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 95 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 96 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), 97 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), 98 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 99 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 100 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 101 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 102 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 103 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 104 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 105 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 108 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 109 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 110 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 111 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 112 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 113 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 114 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 115 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 116 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 117 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 119 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0), 120 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 121 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 122 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 123 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 124 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0), 125 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0), 126 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0), 127 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0), 128 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 129 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 130 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 131 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0), 132 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0), 133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 139 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0), 140 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 142 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 143 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1), 144 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1), 145 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0), 146 }; 147 148 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = { 149 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 150 CLK_MAP(SCLK, PPCLK_GFXCLK), 151 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 152 CLK_MAP(FCLK, PPCLK_FCLK), 153 CLK_MAP(UCLK, PPCLK_UCLK), 154 CLK_MAP(MCLK, PPCLK_UCLK), 155 CLK_MAP(DCLK, PPCLK_DCLK), 156 CLK_MAP(VCLK, PPCLK_VCLK), 157 }; 158 159 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = { 160 FEA_MAP(DPM_PREFETCHER), 161 FEA_MAP(DPM_GFXCLK), 162 FEA_MAP(DPM_UCLK), 163 FEA_MAP(DPM_SOCCLK), 164 FEA_MAP(DPM_FCLK), 165 FEA_MAP(DPM_MP0CLK), 166 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT), 167 FEA_MAP(DS_GFXCLK), 168 FEA_MAP(DS_SOCCLK), 169 FEA_MAP(DS_LCLK), 170 FEA_MAP(DS_FCLK), 171 FEA_MAP(DS_UCLK), 172 FEA_MAP(GFX_ULV), 173 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT), 174 FEA_MAP(RSMU_SMN_CG), 175 FEA_MAP(WAFL_CG), 176 FEA_MAP(PPT), 177 FEA_MAP(TDC), 178 FEA_MAP(APCC_PLUS), 179 FEA_MAP(VR0HOT), 180 FEA_MAP(VR1HOT), 181 FEA_MAP(FW_CTF), 182 FEA_MAP(FAN_CONTROL), 183 FEA_MAP(THERMAL), 184 FEA_MAP(OUT_OF_BAND_MONITOR), 185 FEA_MAP(TEMP_DEPENDENT_VMIN), 186 }; 187 188 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = { 189 TAB_MAP(PPTABLE), 190 TAB_MAP(AVFS), 191 TAB_MAP(AVFS_PSM_DEBUG), 192 TAB_MAP(AVFS_FUSE_OVERRIDE), 193 TAB_MAP(PMSTATUSLOG), 194 TAB_MAP(SMU_METRICS), 195 TAB_MAP(DRIVER_SMU_CONFIG), 196 TAB_MAP(OVERDRIVE), 197 TAB_MAP(I2C_COMMANDS), 198 TAB_MAP(ACTIVITY_MONITOR_COEFF), 199 }; 200 201 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 202 PWR_MAP(AC), 203 PWR_MAP(DC), 204 }; 205 206 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 212 }; 213 214 static int arcturus_tables_init(struct smu_context *smu) 215 { 216 struct smu_table_context *smu_table = &smu->smu_table; 217 struct smu_table *tables = smu_table->tables; 218 219 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 220 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 221 222 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 223 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 224 225 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 226 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 227 228 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 229 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 230 231 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 232 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 233 AMDGPU_GEM_DOMAIN_VRAM); 234 235 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 236 if (!smu_table->metrics_table) 237 return -ENOMEM; 238 smu_table->metrics_time = 0; 239 240 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1); 241 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 242 if (!smu_table->gpu_metrics_table) { 243 kfree(smu_table->metrics_table); 244 return -ENOMEM; 245 } 246 247 return 0; 248 } 249 250 static int arcturus_allocate_dpm_context(struct smu_context *smu) 251 { 252 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 253 254 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 255 GFP_KERNEL); 256 if (!smu_dpm->dpm_context) 257 return -ENOMEM; 258 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 259 260 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state), 261 GFP_KERNEL); 262 if (!smu_dpm->dpm_current_power_state) 263 return -ENOMEM; 264 265 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state), 266 GFP_KERNEL); 267 if (!smu_dpm->dpm_request_power_state) 268 return -ENOMEM; 269 270 return 0; 271 } 272 273 static int arcturus_init_smc_tables(struct smu_context *smu) 274 { 275 int ret = 0; 276 277 ret = arcturus_tables_init(smu); 278 if (ret) 279 return ret; 280 281 ret = arcturus_allocate_dpm_context(smu); 282 if (ret) 283 return ret; 284 285 return smu_v11_0_init_smc_tables(smu); 286 } 287 288 static int 289 arcturus_get_allowed_feature_mask(struct smu_context *smu, 290 uint32_t *feature_mask, uint32_t num) 291 { 292 if (num > 2) 293 return -EINVAL; 294 295 /* pptable will handle the features to enable */ 296 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 297 298 return 0; 299 } 300 301 static int arcturus_set_default_dpm_table(struct smu_context *smu) 302 { 303 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 304 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 305 struct smu_11_0_dpm_table *dpm_table = NULL; 306 int ret = 0; 307 308 /* socclk dpm table setup */ 309 dpm_table = &dpm_context->dpm_tables.soc_table; 310 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 311 ret = smu_v11_0_set_single_dpm_table(smu, 312 SMU_SOCCLK, 313 dpm_table); 314 if (ret) 315 return ret; 316 dpm_table->is_fine_grained = 317 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 318 } else { 319 dpm_table->count = 1; 320 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 321 dpm_table->dpm_levels[0].enabled = true; 322 dpm_table->min = dpm_table->dpm_levels[0].value; 323 dpm_table->max = dpm_table->dpm_levels[0].value; 324 } 325 326 /* gfxclk dpm table setup */ 327 dpm_table = &dpm_context->dpm_tables.gfx_table; 328 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 329 ret = smu_v11_0_set_single_dpm_table(smu, 330 SMU_GFXCLK, 331 dpm_table); 332 if (ret) 333 return ret; 334 dpm_table->is_fine_grained = 335 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 336 } else { 337 dpm_table->count = 1; 338 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 339 dpm_table->dpm_levels[0].enabled = true; 340 dpm_table->min = dpm_table->dpm_levels[0].value; 341 dpm_table->max = dpm_table->dpm_levels[0].value; 342 } 343 344 /* memclk dpm table setup */ 345 dpm_table = &dpm_context->dpm_tables.uclk_table; 346 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 347 ret = smu_v11_0_set_single_dpm_table(smu, 348 SMU_UCLK, 349 dpm_table); 350 if (ret) 351 return ret; 352 dpm_table->is_fine_grained = 353 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 354 } else { 355 dpm_table->count = 1; 356 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 357 dpm_table->dpm_levels[0].enabled = true; 358 dpm_table->min = dpm_table->dpm_levels[0].value; 359 dpm_table->max = dpm_table->dpm_levels[0].value; 360 } 361 362 /* fclk dpm table setup */ 363 dpm_table = &dpm_context->dpm_tables.fclk_table; 364 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 365 ret = smu_v11_0_set_single_dpm_table(smu, 366 SMU_FCLK, 367 dpm_table); 368 if (ret) 369 return ret; 370 dpm_table->is_fine_grained = 371 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; 372 } else { 373 dpm_table->count = 1; 374 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 375 dpm_table->dpm_levels[0].enabled = true; 376 dpm_table->min = dpm_table->dpm_levels[0].value; 377 dpm_table->max = dpm_table->dpm_levels[0].value; 378 } 379 380 return 0; 381 } 382 383 static void arcturus_check_bxco_support(struct smu_context *smu) 384 { 385 struct smu_table_context *table_context = &smu->smu_table; 386 struct smu_11_0_powerplay_table *powerplay_table = 387 table_context->power_play_table; 388 struct smu_baco_context *smu_baco = &smu->smu_baco; 389 struct amdgpu_device *adev = smu->adev; 390 uint32_t val; 391 392 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 393 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 394 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 395 smu_baco->platform_support = 396 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 397 false; 398 } 399 } 400 401 static int arcturus_check_powerplay_table(struct smu_context *smu) 402 { 403 struct smu_table_context *table_context = &smu->smu_table; 404 struct smu_11_0_powerplay_table *powerplay_table = 405 table_context->power_play_table; 406 407 arcturus_check_bxco_support(smu); 408 409 table_context->thermal_controller_type = 410 powerplay_table->thermal_controller_type; 411 412 return 0; 413 } 414 415 static int arcturus_store_powerplay_table(struct smu_context *smu) 416 { 417 struct smu_table_context *table_context = &smu->smu_table; 418 struct smu_11_0_powerplay_table *powerplay_table = 419 table_context->power_play_table; 420 421 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 422 sizeof(PPTable_t)); 423 424 return 0; 425 } 426 427 static int arcturus_append_powerplay_table(struct smu_context *smu) 428 { 429 struct smu_table_context *table_context = &smu->smu_table; 430 PPTable_t *smc_pptable = table_context->driver_pptable; 431 struct atom_smc_dpm_info_v4_6 *smc_dpm_table; 432 int index, ret; 433 434 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 435 smc_dpm_info); 436 437 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 438 (uint8_t **)&smc_dpm_table); 439 if (ret) 440 return ret; 441 442 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 443 smc_dpm_table->table_header.format_revision, 444 smc_dpm_table->table_header.content_revision); 445 446 if ((smc_dpm_table->table_header.format_revision == 4) && 447 (smc_dpm_table->table_header.content_revision == 6)) 448 memcpy(&smc_pptable->MaxVoltageStepGfx, 449 &smc_dpm_table->maxvoltagestepgfx, 450 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx)); 451 452 return 0; 453 } 454 455 static int arcturus_setup_pptable(struct smu_context *smu) 456 { 457 int ret = 0; 458 459 ret = smu_v11_0_setup_pptable(smu); 460 if (ret) 461 return ret; 462 463 ret = arcturus_store_powerplay_table(smu); 464 if (ret) 465 return ret; 466 467 ret = arcturus_append_powerplay_table(smu); 468 if (ret) 469 return ret; 470 471 ret = arcturus_check_powerplay_table(smu); 472 if (ret) 473 return ret; 474 475 return ret; 476 } 477 478 static int arcturus_run_btc(struct smu_context *smu) 479 { 480 int ret = 0; 481 482 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL); 483 if (ret) { 484 dev_err(smu->adev->dev, "RunAfllBtc failed!\n"); 485 return ret; 486 } 487 488 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 489 } 490 491 static int arcturus_populate_umd_state_clk(struct smu_context *smu) 492 { 493 struct smu_11_0_dpm_context *dpm_context = 494 smu->smu_dpm.dpm_context; 495 struct smu_11_0_dpm_table *gfx_table = 496 &dpm_context->dpm_tables.gfx_table; 497 struct smu_11_0_dpm_table *mem_table = 498 &dpm_context->dpm_tables.uclk_table; 499 struct smu_11_0_dpm_table *soc_table = 500 &dpm_context->dpm_tables.soc_table; 501 struct smu_umd_pstate_table *pstate_table = 502 &smu->pstate_table; 503 504 pstate_table->gfxclk_pstate.min = gfx_table->min; 505 pstate_table->gfxclk_pstate.peak = gfx_table->max; 506 507 pstate_table->uclk_pstate.min = mem_table->min; 508 pstate_table->uclk_pstate.peak = mem_table->max; 509 510 pstate_table->socclk_pstate.min = soc_table->min; 511 pstate_table->socclk_pstate.peak = soc_table->max; 512 513 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL && 514 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && 515 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) { 516 pstate_table->gfxclk_pstate.standard = 517 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value; 518 pstate_table->uclk_pstate.standard = 519 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value; 520 pstate_table->socclk_pstate.standard = 521 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value; 522 } else { 523 pstate_table->gfxclk_pstate.standard = 524 pstate_table->gfxclk_pstate.min; 525 pstate_table->uclk_pstate.standard = 526 pstate_table->uclk_pstate.min; 527 pstate_table->socclk_pstate.standard = 528 pstate_table->socclk_pstate.min; 529 } 530 531 return 0; 532 } 533 534 static int arcturus_get_clk_table(struct smu_context *smu, 535 struct pp_clock_levels_with_latency *clocks, 536 struct smu_11_0_dpm_table *dpm_table) 537 { 538 int i, count; 539 540 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 541 clocks->num_levels = count; 542 543 for (i = 0; i < count; i++) { 544 clocks->data[i].clocks_in_khz = 545 dpm_table->dpm_levels[i].value * 1000; 546 clocks->data[i].latency_in_us = 0; 547 } 548 549 return 0; 550 } 551 552 static int arcturus_freqs_in_same_level(int32_t frequency1, 553 int32_t frequency2) 554 { 555 return (abs(frequency1 - frequency2) <= EPSILON); 556 } 557 558 static int arcturus_get_smu_metrics_data(struct smu_context *smu, 559 MetricsMember_t member, 560 uint32_t *value) 561 { 562 struct smu_table_context *smu_table= &smu->smu_table; 563 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 564 int ret = 0; 565 566 mutex_lock(&smu->metrics_lock); 567 568 ret = smu_cmn_get_metrics_table_locked(smu, 569 NULL, 570 false); 571 if (ret) { 572 mutex_unlock(&smu->metrics_lock); 573 return ret; 574 } 575 576 switch (member) { 577 case METRICS_CURR_GFXCLK: 578 *value = metrics->CurrClock[PPCLK_GFXCLK]; 579 break; 580 case METRICS_CURR_SOCCLK: 581 *value = metrics->CurrClock[PPCLK_SOCCLK]; 582 break; 583 case METRICS_CURR_UCLK: 584 *value = metrics->CurrClock[PPCLK_UCLK]; 585 break; 586 case METRICS_CURR_VCLK: 587 *value = metrics->CurrClock[PPCLK_VCLK]; 588 break; 589 case METRICS_CURR_DCLK: 590 *value = metrics->CurrClock[PPCLK_DCLK]; 591 break; 592 case METRICS_CURR_FCLK: 593 *value = metrics->CurrClock[PPCLK_FCLK]; 594 break; 595 case METRICS_AVERAGE_GFXCLK: 596 *value = metrics->AverageGfxclkFrequency; 597 break; 598 case METRICS_AVERAGE_SOCCLK: 599 *value = metrics->AverageSocclkFrequency; 600 break; 601 case METRICS_AVERAGE_UCLK: 602 *value = metrics->AverageUclkFrequency; 603 break; 604 case METRICS_AVERAGE_VCLK: 605 *value = metrics->AverageVclkFrequency; 606 break; 607 case METRICS_AVERAGE_DCLK: 608 *value = metrics->AverageDclkFrequency; 609 break; 610 case METRICS_AVERAGE_GFXACTIVITY: 611 *value = metrics->AverageGfxActivity; 612 break; 613 case METRICS_AVERAGE_MEMACTIVITY: 614 *value = metrics->AverageUclkActivity; 615 break; 616 case METRICS_AVERAGE_VCNACTIVITY: 617 *value = metrics->VcnActivityPercentage; 618 break; 619 case METRICS_AVERAGE_SOCKETPOWER: 620 *value = metrics->AverageSocketPower << 8; 621 break; 622 case METRICS_TEMPERATURE_EDGE: 623 *value = metrics->TemperatureEdge * 624 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 625 break; 626 case METRICS_TEMPERATURE_HOTSPOT: 627 *value = metrics->TemperatureHotspot * 628 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 629 break; 630 case METRICS_TEMPERATURE_MEM: 631 *value = metrics->TemperatureHBM * 632 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 633 break; 634 case METRICS_TEMPERATURE_VRGFX: 635 *value = metrics->TemperatureVrGfx * 636 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 637 break; 638 case METRICS_TEMPERATURE_VRSOC: 639 *value = metrics->TemperatureVrSoc * 640 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 641 break; 642 case METRICS_TEMPERATURE_VRMEM: 643 *value = metrics->TemperatureVrMem * 644 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 645 break; 646 case METRICS_THROTTLER_STATUS: 647 *value = metrics->ThrottlerStatus; 648 break; 649 case METRICS_CURR_FANSPEED: 650 *value = metrics->CurrFanSpeed; 651 break; 652 default: 653 *value = UINT_MAX; 654 break; 655 } 656 657 mutex_unlock(&smu->metrics_lock); 658 659 return ret; 660 } 661 662 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu, 663 enum smu_clk_type clk_type, 664 uint32_t *value) 665 { 666 MetricsMember_t member_type; 667 int clk_id = 0; 668 669 if (!value) 670 return -EINVAL; 671 672 clk_id = smu_cmn_to_asic_specific_index(smu, 673 CMN2ASIC_MAPPING_CLK, 674 clk_type); 675 if (clk_id < 0) 676 return -EINVAL; 677 678 switch (clk_id) { 679 case PPCLK_GFXCLK: 680 /* 681 * CurrClock[clk_id] can provide accurate 682 * output only when the dpm feature is enabled. 683 * We can use Average_* for dpm disabled case. 684 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 685 */ 686 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 687 member_type = METRICS_CURR_GFXCLK; 688 else 689 member_type = METRICS_AVERAGE_GFXCLK; 690 break; 691 case PPCLK_UCLK: 692 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 693 member_type = METRICS_CURR_UCLK; 694 else 695 member_type = METRICS_AVERAGE_UCLK; 696 break; 697 case PPCLK_SOCCLK: 698 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 699 member_type = METRICS_CURR_SOCCLK; 700 else 701 member_type = METRICS_AVERAGE_SOCCLK; 702 break; 703 case PPCLK_VCLK: 704 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 705 member_type = METRICS_CURR_VCLK; 706 else 707 member_type = METRICS_AVERAGE_VCLK; 708 break; 709 case PPCLK_DCLK: 710 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) 711 member_type = METRICS_CURR_DCLK; 712 else 713 member_type = METRICS_AVERAGE_DCLK; 714 break; 715 case PPCLK_FCLK: 716 member_type = METRICS_CURR_FCLK; 717 break; 718 default: 719 return -EINVAL; 720 } 721 722 return arcturus_get_smu_metrics_data(smu, 723 member_type, 724 value); 725 } 726 727 static int arcturus_print_clk_levels(struct smu_context *smu, 728 enum smu_clk_type type, char *buf) 729 { 730 int i, now, size = 0; 731 int ret = 0; 732 struct pp_clock_levels_with_latency clocks; 733 struct smu_11_0_dpm_table *single_dpm_table; 734 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 735 struct smu_11_0_dpm_context *dpm_context = NULL; 736 uint32_t gen_speed, lane_width; 737 738 if (amdgpu_ras_intr_triggered()) 739 return snprintf(buf, PAGE_SIZE, "unavailable\n"); 740 741 dpm_context = smu_dpm->dpm_context; 742 743 switch (type) { 744 case SMU_SCLK: 745 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 746 if (ret) { 747 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 748 return ret; 749 } 750 751 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 752 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 753 if (ret) { 754 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 755 return ret; 756 } 757 758 /* 759 * For DPM disabled case, there will be only one clock level. 760 * And it's safe to assume that is always the current clock. 761 */ 762 for (i = 0; i < clocks.num_levels; i++) 763 size += sprintf(buf + size, "%d: %uMhz %s\n", i, 764 clocks.data[i].clocks_in_khz / 1000, 765 (clocks.num_levels == 1) ? "*" : 766 (arcturus_freqs_in_same_level( 767 clocks.data[i].clocks_in_khz / 1000, 768 now) ? "*" : "")); 769 break; 770 771 case SMU_MCLK: 772 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 773 if (ret) { 774 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 775 return ret; 776 } 777 778 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 779 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 780 if (ret) { 781 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 782 return ret; 783 } 784 785 for (i = 0; i < clocks.num_levels; i++) 786 size += sprintf(buf + size, "%d: %uMhz %s\n", 787 i, clocks.data[i].clocks_in_khz / 1000, 788 (clocks.num_levels == 1) ? "*" : 789 (arcturus_freqs_in_same_level( 790 clocks.data[i].clocks_in_khz / 1000, 791 now) ? "*" : "")); 792 break; 793 794 case SMU_SOCCLK: 795 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 796 if (ret) { 797 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 798 return ret; 799 } 800 801 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 802 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 803 if (ret) { 804 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 805 return ret; 806 } 807 808 for (i = 0; i < clocks.num_levels; i++) 809 size += sprintf(buf + size, "%d: %uMhz %s\n", 810 i, clocks.data[i].clocks_in_khz / 1000, 811 (clocks.num_levels == 1) ? "*" : 812 (arcturus_freqs_in_same_level( 813 clocks.data[i].clocks_in_khz / 1000, 814 now) ? "*" : "")); 815 break; 816 817 case SMU_FCLK: 818 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 819 if (ret) { 820 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 821 return ret; 822 } 823 824 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 825 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 826 if (ret) { 827 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 828 return ret; 829 } 830 831 for (i = 0; i < single_dpm_table->count; i++) 832 size += sprintf(buf + size, "%d: %uMhz %s\n", 833 i, single_dpm_table->dpm_levels[i].value, 834 (clocks.num_levels == 1) ? "*" : 835 (arcturus_freqs_in_same_level( 836 clocks.data[i].clocks_in_khz / 1000, 837 now) ? "*" : "")); 838 break; 839 840 case SMU_VCLK: 841 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 842 if (ret) { 843 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 844 return ret; 845 } 846 847 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 848 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 849 if (ret) { 850 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 851 return ret; 852 } 853 854 for (i = 0; i < single_dpm_table->count; i++) 855 size += sprintf(buf + size, "%d: %uMhz %s\n", 856 i, single_dpm_table->dpm_levels[i].value, 857 (clocks.num_levels == 1) ? "*" : 858 (arcturus_freqs_in_same_level( 859 clocks.data[i].clocks_in_khz / 1000, 860 now) ? "*" : "")); 861 break; 862 863 case SMU_DCLK: 864 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 865 if (ret) { 866 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 867 return ret; 868 } 869 870 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 871 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 872 if (ret) { 873 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 874 return ret; 875 } 876 877 for (i = 0; i < single_dpm_table->count; i++) 878 size += sprintf(buf + size, "%d: %uMhz %s\n", 879 i, single_dpm_table->dpm_levels[i].value, 880 (clocks.num_levels == 1) ? "*" : 881 (arcturus_freqs_in_same_level( 882 clocks.data[i].clocks_in_khz / 1000, 883 now) ? "*" : "")); 884 break; 885 886 case SMU_PCIE: 887 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 888 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 889 size += sprintf(buf + size, "0: %s %s %dMhz *\n", 890 (gen_speed == 0) ? "2.5GT/s," : 891 (gen_speed == 1) ? "5.0GT/s," : 892 (gen_speed == 2) ? "8.0GT/s," : 893 (gen_speed == 3) ? "16.0GT/s," : "", 894 (lane_width == 1) ? "x1" : 895 (lane_width == 2) ? "x2" : 896 (lane_width == 3) ? "x4" : 897 (lane_width == 4) ? "x8" : 898 (lane_width == 5) ? "x12" : 899 (lane_width == 6) ? "x16" : "", 900 smu->smu_table.boot_values.lclk / 100); 901 break; 902 903 default: 904 break; 905 } 906 907 return size; 908 } 909 910 static int arcturus_upload_dpm_level(struct smu_context *smu, 911 bool max, 912 uint32_t feature_mask, 913 uint32_t level) 914 { 915 struct smu_11_0_dpm_context *dpm_context = 916 smu->smu_dpm.dpm_context; 917 uint32_t freq; 918 int ret = 0; 919 920 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 921 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 922 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 923 ret = smu_cmn_send_smc_msg_with_param(smu, 924 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 925 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 926 NULL); 927 if (ret) { 928 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 929 max ? "max" : "min"); 930 return ret; 931 } 932 } 933 934 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 935 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 936 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 937 ret = smu_cmn_send_smc_msg_with_param(smu, 938 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 939 (PPCLK_UCLK << 16) | (freq & 0xffff), 940 NULL); 941 if (ret) { 942 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 943 max ? "max" : "min"); 944 return ret; 945 } 946 } 947 948 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 949 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 950 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 951 ret = smu_cmn_send_smc_msg_with_param(smu, 952 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 953 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 954 NULL); 955 if (ret) { 956 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 957 max ? "max" : "min"); 958 return ret; 959 } 960 } 961 962 return ret; 963 } 964 965 static int arcturus_force_clk_levels(struct smu_context *smu, 966 enum smu_clk_type type, uint32_t mask) 967 { 968 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 969 struct smu_11_0_dpm_table *single_dpm_table = NULL; 970 uint32_t soft_min_level, soft_max_level; 971 uint32_t smu_version; 972 int ret = 0; 973 974 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 975 if (ret) { 976 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 977 return ret; 978 } 979 980 if ((smu_version >= 0x361200) && 981 (smu_version <= 0x361a00)) { 982 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 983 "54.18 - 54.26(included) SMU firmwares\n"); 984 return -EOPNOTSUPP; 985 } 986 987 soft_min_level = mask ? (ffs(mask) - 1) : 0; 988 soft_max_level = mask ? (fls(mask) - 1) : 0; 989 990 switch (type) { 991 case SMU_SCLK: 992 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 993 if (soft_max_level >= single_dpm_table->count) { 994 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 995 soft_max_level, single_dpm_table->count - 1); 996 ret = -EINVAL; 997 break; 998 } 999 1000 ret = arcturus_upload_dpm_level(smu, 1001 false, 1002 FEATURE_DPM_GFXCLK_MASK, 1003 soft_min_level); 1004 if (ret) { 1005 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1006 break; 1007 } 1008 1009 ret = arcturus_upload_dpm_level(smu, 1010 true, 1011 FEATURE_DPM_GFXCLK_MASK, 1012 soft_max_level); 1013 if (ret) 1014 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1015 1016 break; 1017 1018 case SMU_MCLK: 1019 case SMU_SOCCLK: 1020 case SMU_FCLK: 1021 /* 1022 * Should not arrive here since Arcturus does not 1023 * support mclk/socclk/fclk softmin/softmax settings 1024 */ 1025 ret = -EINVAL; 1026 break; 1027 1028 default: 1029 break; 1030 } 1031 1032 return ret; 1033 } 1034 1035 static int arcturus_get_thermal_temperature_range(struct smu_context *smu, 1036 struct smu_temperature_range *range) 1037 { 1038 struct smu_table_context *table_context = &smu->smu_table; 1039 struct smu_11_0_powerplay_table *powerplay_table = 1040 table_context->power_play_table; 1041 PPTable_t *pptable = smu->smu_table.driver_pptable; 1042 1043 if (!range) 1044 return -EINVAL; 1045 1046 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1047 1048 range->max = pptable->TedgeLimit * 1049 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1050 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 1051 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1052 range->hotspot_crit_max = pptable->ThotspotLimit * 1053 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1054 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1055 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1056 range->mem_crit_max = pptable->TmemLimit * 1057 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1058 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1059 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1060 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1061 1062 return 0; 1063 } 1064 1065 static int arcturus_read_sensor(struct smu_context *smu, 1066 enum amd_pp_sensors sensor, 1067 void *data, uint32_t *size) 1068 { 1069 struct smu_table_context *table_context = &smu->smu_table; 1070 PPTable_t *pptable = table_context->driver_pptable; 1071 int ret = 0; 1072 1073 if (amdgpu_ras_intr_triggered()) 1074 return 0; 1075 1076 if (!data || !size) 1077 return -EINVAL; 1078 1079 mutex_lock(&smu->sensor_lock); 1080 switch (sensor) { 1081 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1082 *(uint32_t *)data = pptable->FanMaximumRpm; 1083 *size = 4; 1084 break; 1085 case AMDGPU_PP_SENSOR_MEM_LOAD: 1086 ret = arcturus_get_smu_metrics_data(smu, 1087 METRICS_AVERAGE_MEMACTIVITY, 1088 (uint32_t *)data); 1089 *size = 4; 1090 break; 1091 case AMDGPU_PP_SENSOR_GPU_LOAD: 1092 ret = arcturus_get_smu_metrics_data(smu, 1093 METRICS_AVERAGE_GFXACTIVITY, 1094 (uint32_t *)data); 1095 *size = 4; 1096 break; 1097 case AMDGPU_PP_SENSOR_GPU_POWER: 1098 ret = arcturus_get_smu_metrics_data(smu, 1099 METRICS_AVERAGE_SOCKETPOWER, 1100 (uint32_t *)data); 1101 *size = 4; 1102 break; 1103 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1104 ret = arcturus_get_smu_metrics_data(smu, 1105 METRICS_TEMPERATURE_HOTSPOT, 1106 (uint32_t *)data); 1107 *size = 4; 1108 break; 1109 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1110 ret = arcturus_get_smu_metrics_data(smu, 1111 METRICS_TEMPERATURE_EDGE, 1112 (uint32_t *)data); 1113 *size = 4; 1114 break; 1115 case AMDGPU_PP_SENSOR_MEM_TEMP: 1116 ret = arcturus_get_smu_metrics_data(smu, 1117 METRICS_TEMPERATURE_MEM, 1118 (uint32_t *)data); 1119 *size = 4; 1120 break; 1121 case AMDGPU_PP_SENSOR_GFX_MCLK: 1122 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1123 /* the output clock frequency in 10K unit */ 1124 *(uint32_t *)data *= 100; 1125 *size = 4; 1126 break; 1127 case AMDGPU_PP_SENSOR_GFX_SCLK: 1128 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1129 *(uint32_t *)data *= 100; 1130 *size = 4; 1131 break; 1132 case AMDGPU_PP_SENSOR_VDDGFX: 1133 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1134 *size = 4; 1135 break; 1136 default: 1137 ret = -EOPNOTSUPP; 1138 break; 1139 } 1140 mutex_unlock(&smu->sensor_lock); 1141 1142 return ret; 1143 } 1144 1145 static int arcturus_get_fan_speed_percent(struct smu_context *smu, 1146 uint32_t *speed) 1147 { 1148 int ret; 1149 u32 rpm; 1150 1151 if (!speed) 1152 return -EINVAL; 1153 1154 switch (smu_v11_0_get_fan_control_mode(smu)) { 1155 case AMD_FAN_CTRL_AUTO: 1156 ret = arcturus_get_smu_metrics_data(smu, 1157 METRICS_CURR_FANSPEED, 1158 &rpm); 1159 if (!ret && smu->fan_max_rpm) 1160 *speed = rpm * 100 / smu->fan_max_rpm; 1161 return ret; 1162 default: 1163 *speed = smu->user_dpm_profile.fan_speed_percent; 1164 return 0; 1165 } 1166 } 1167 1168 static int arcturus_get_fan_parameters(struct smu_context *smu) 1169 { 1170 PPTable_t *pptable = smu->smu_table.driver_pptable; 1171 1172 smu->fan_max_rpm = pptable->FanMaximumRpm; 1173 1174 return 0; 1175 } 1176 1177 static int arcturus_get_power_limit(struct smu_context *smu) 1178 { 1179 struct smu_11_0_powerplay_table *powerplay_table = 1180 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 1181 PPTable_t *pptable = smu->smu_table.driver_pptable; 1182 uint32_t power_limit, od_percent; 1183 1184 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1185 /* the last hope to figure out the ppt limit */ 1186 if (!pptable) { 1187 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1188 return -EINVAL; 1189 } 1190 power_limit = 1191 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1192 } 1193 smu->current_power_limit = smu->default_power_limit = power_limit; 1194 1195 if (smu->od_enabled) { 1196 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 1197 1198 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1199 1200 power_limit *= (100 + od_percent); 1201 power_limit /= 100; 1202 } 1203 smu->max_power_limit = power_limit; 1204 1205 return 0; 1206 } 1207 1208 static int arcturus_get_power_profile_mode(struct smu_context *smu, 1209 char *buf) 1210 { 1211 DpmActivityMonitorCoeffInt_t activity_monitor; 1212 static const char *profile_name[] = { 1213 "BOOTUP_DEFAULT", 1214 "3D_FULL_SCREEN", 1215 "POWER_SAVING", 1216 "VIDEO", 1217 "VR", 1218 "COMPUTE", 1219 "CUSTOM"}; 1220 static const char *title[] = { 1221 "PROFILE_INDEX(NAME)", 1222 "CLOCK_TYPE(NAME)", 1223 "FPS", 1224 "UseRlcBusy", 1225 "MinActiveFreqType", 1226 "MinActiveFreq", 1227 "BoosterFreqType", 1228 "BoosterFreq", 1229 "PD_Data_limit_c", 1230 "PD_Data_error_coeff", 1231 "PD_Data_error_rate_coeff"}; 1232 uint32_t i, size = 0; 1233 int16_t workload_type = 0; 1234 int result = 0; 1235 uint32_t smu_version; 1236 1237 if (!buf) 1238 return -EINVAL; 1239 1240 result = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1241 if (result) 1242 return result; 1243 1244 if (smu_version >= 0x360d00) 1245 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1246 title[0], title[1], title[2], title[3], title[4], title[5], 1247 title[6], title[7], title[8], title[9], title[10]); 1248 else 1249 size += sprintf(buf + size, "%16s\n", 1250 title[0]); 1251 1252 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1253 /* 1254 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1255 * Not all profile modes are supported on arcturus. 1256 */ 1257 workload_type = smu_cmn_to_asic_specific_index(smu, 1258 CMN2ASIC_MAPPING_WORKLOAD, 1259 i); 1260 if (workload_type < 0) 1261 continue; 1262 1263 if (smu_version >= 0x360d00) { 1264 result = smu_cmn_update_table(smu, 1265 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1266 workload_type, 1267 (void *)(&activity_monitor), 1268 false); 1269 if (result) { 1270 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1271 return result; 1272 } 1273 } 1274 1275 size += sprintf(buf + size, "%2d %14s%s\n", 1276 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1277 1278 if (smu_version >= 0x360d00) { 1279 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1280 " ", 1281 0, 1282 "GFXCLK", 1283 activity_monitor.Gfx_FPS, 1284 activity_monitor.Gfx_UseRlcBusy, 1285 activity_monitor.Gfx_MinActiveFreqType, 1286 activity_monitor.Gfx_MinActiveFreq, 1287 activity_monitor.Gfx_BoosterFreqType, 1288 activity_monitor.Gfx_BoosterFreq, 1289 activity_monitor.Gfx_PD_Data_limit_c, 1290 activity_monitor.Gfx_PD_Data_error_coeff, 1291 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1292 1293 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1294 " ", 1295 1, 1296 "UCLK", 1297 activity_monitor.Mem_FPS, 1298 activity_monitor.Mem_UseRlcBusy, 1299 activity_monitor.Mem_MinActiveFreqType, 1300 activity_monitor.Mem_MinActiveFreq, 1301 activity_monitor.Mem_BoosterFreqType, 1302 activity_monitor.Mem_BoosterFreq, 1303 activity_monitor.Mem_PD_Data_limit_c, 1304 activity_monitor.Mem_PD_Data_error_coeff, 1305 activity_monitor.Mem_PD_Data_error_rate_coeff); 1306 } 1307 } 1308 1309 return size; 1310 } 1311 1312 static int arcturus_set_power_profile_mode(struct smu_context *smu, 1313 long *input, 1314 uint32_t size) 1315 { 1316 DpmActivityMonitorCoeffInt_t activity_monitor; 1317 int workload_type = 0; 1318 uint32_t profile_mode = input[size]; 1319 int ret = 0; 1320 uint32_t smu_version; 1321 1322 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1323 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1324 return -EINVAL; 1325 } 1326 1327 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1328 if (ret) 1329 return ret; 1330 1331 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && 1332 (smu_version >=0x360d00)) { 1333 ret = smu_cmn_update_table(smu, 1334 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1335 WORKLOAD_PPLIB_CUSTOM_BIT, 1336 (void *)(&activity_monitor), 1337 false); 1338 if (ret) { 1339 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1340 return ret; 1341 } 1342 1343 switch (input[0]) { 1344 case 0: /* Gfxclk */ 1345 activity_monitor.Gfx_FPS = input[1]; 1346 activity_monitor.Gfx_UseRlcBusy = input[2]; 1347 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1348 activity_monitor.Gfx_MinActiveFreq = input[4]; 1349 activity_monitor.Gfx_BoosterFreqType = input[5]; 1350 activity_monitor.Gfx_BoosterFreq = input[6]; 1351 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1352 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1353 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1354 break; 1355 case 1: /* Uclk */ 1356 activity_monitor.Mem_FPS = input[1]; 1357 activity_monitor.Mem_UseRlcBusy = input[2]; 1358 activity_monitor.Mem_MinActiveFreqType = input[3]; 1359 activity_monitor.Mem_MinActiveFreq = input[4]; 1360 activity_monitor.Mem_BoosterFreqType = input[5]; 1361 activity_monitor.Mem_BoosterFreq = input[6]; 1362 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1363 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1364 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1365 break; 1366 } 1367 1368 ret = smu_cmn_update_table(smu, 1369 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1370 WORKLOAD_PPLIB_CUSTOM_BIT, 1371 (void *)(&activity_monitor), 1372 true); 1373 if (ret) { 1374 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1375 return ret; 1376 } 1377 } 1378 1379 /* 1380 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1381 * Not all profile modes are supported on arcturus. 1382 */ 1383 workload_type = smu_cmn_to_asic_specific_index(smu, 1384 CMN2ASIC_MAPPING_WORKLOAD, 1385 profile_mode); 1386 if (workload_type < 0) { 1387 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode); 1388 return -EINVAL; 1389 } 1390 1391 ret = smu_cmn_send_smc_msg_with_param(smu, 1392 SMU_MSG_SetWorkloadMask, 1393 1 << workload_type, 1394 NULL); 1395 if (ret) { 1396 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 1397 return ret; 1398 } 1399 1400 smu->power_profile_mode = profile_mode; 1401 1402 return 0; 1403 } 1404 1405 static int arcturus_set_performance_level(struct smu_context *smu, 1406 enum amd_dpm_forced_level level) 1407 { 1408 uint32_t smu_version; 1409 int ret; 1410 1411 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1412 if (ret) { 1413 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 1414 return ret; 1415 } 1416 1417 switch (level) { 1418 case AMD_DPM_FORCED_LEVEL_HIGH: 1419 case AMD_DPM_FORCED_LEVEL_LOW: 1420 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1421 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1422 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1423 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1424 if ((smu_version >= 0x361200) && 1425 (smu_version <= 0x361a00)) { 1426 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 1427 "54.18 - 54.26(included) SMU firmwares\n"); 1428 return -EOPNOTSUPP; 1429 } 1430 break; 1431 default: 1432 break; 1433 } 1434 1435 return smu_v11_0_set_performance_level(smu, level); 1436 } 1437 1438 static void arcturus_dump_pptable(struct smu_context *smu) 1439 { 1440 struct smu_table_context *table_context = &smu->smu_table; 1441 PPTable_t *pptable = table_context->driver_pptable; 1442 int i; 1443 1444 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 1445 1446 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 1447 1448 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 1449 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 1450 1451 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 1452 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]); 1453 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]); 1454 } 1455 1456 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc); 1457 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau); 1458 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx); 1459 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau); 1460 1461 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit); 1462 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit); 1463 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit); 1464 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit); 1465 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit); 1466 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit); 1467 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit); 1468 1469 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit); 1470 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); 1471 1472 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask); 1473 1474 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); 1475 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding); 1476 1477 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass); 1478 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]); 1479 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]); 1480 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]); 1481 1482 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx); 1483 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc); 1484 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx); 1485 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc); 1486 1487 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx); 1488 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc); 1489 1490 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 1491 " .VoltageMode = 0x%02x\n" 1492 " .SnapToDiscrete = 0x%02x\n" 1493 " .NumDiscreteLevels = 0x%02x\n" 1494 " .padding = 0x%02x\n" 1495 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1496 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1497 " .SsFmin = 0x%04x\n" 1498 " .Padding_16 = 0x%04x\n", 1499 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 1500 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 1501 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 1502 pptable->DpmDescriptor[PPCLK_GFXCLK].padding, 1503 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 1504 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 1505 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 1506 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 1507 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 1508 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 1509 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 1510 1511 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n" 1512 " .VoltageMode = 0x%02x\n" 1513 " .SnapToDiscrete = 0x%02x\n" 1514 " .NumDiscreteLevels = 0x%02x\n" 1515 " .padding = 0x%02x\n" 1516 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1517 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1518 " .SsFmin = 0x%04x\n" 1519 " .Padding_16 = 0x%04x\n", 1520 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode, 1521 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete, 1522 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels, 1523 pptable->DpmDescriptor[PPCLK_VCLK].padding, 1524 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m, 1525 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b, 1526 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a, 1527 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b, 1528 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c, 1529 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin, 1530 pptable->DpmDescriptor[PPCLK_VCLK].Padding16); 1531 1532 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n" 1533 " .VoltageMode = 0x%02x\n" 1534 " .SnapToDiscrete = 0x%02x\n" 1535 " .NumDiscreteLevels = 0x%02x\n" 1536 " .padding = 0x%02x\n" 1537 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1538 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1539 " .SsFmin = 0x%04x\n" 1540 " .Padding_16 = 0x%04x\n", 1541 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode, 1542 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete, 1543 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels, 1544 pptable->DpmDescriptor[PPCLK_DCLK].padding, 1545 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m, 1546 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b, 1547 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a, 1548 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b, 1549 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c, 1550 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin, 1551 pptable->DpmDescriptor[PPCLK_DCLK].Padding16); 1552 1553 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 1554 " .VoltageMode = 0x%02x\n" 1555 " .SnapToDiscrete = 0x%02x\n" 1556 " .NumDiscreteLevels = 0x%02x\n" 1557 " .padding = 0x%02x\n" 1558 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1559 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1560 " .SsFmin = 0x%04x\n" 1561 " .Padding_16 = 0x%04x\n", 1562 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 1563 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 1564 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 1565 pptable->DpmDescriptor[PPCLK_SOCCLK].padding, 1566 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 1567 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 1568 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 1569 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 1570 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 1571 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 1572 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 1573 1574 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 1575 " .VoltageMode = 0x%02x\n" 1576 " .SnapToDiscrete = 0x%02x\n" 1577 " .NumDiscreteLevels = 0x%02x\n" 1578 " .padding = 0x%02x\n" 1579 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1580 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1581 " .SsFmin = 0x%04x\n" 1582 " .Padding_16 = 0x%04x\n", 1583 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 1584 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 1585 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 1586 pptable->DpmDescriptor[PPCLK_UCLK].padding, 1587 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 1588 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 1589 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 1590 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 1591 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 1592 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 1593 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 1594 1595 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 1596 " .VoltageMode = 0x%02x\n" 1597 " .SnapToDiscrete = 0x%02x\n" 1598 " .NumDiscreteLevels = 0x%02x\n" 1599 " .padding = 0x%02x\n" 1600 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1601 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1602 " .SsFmin = 0x%04x\n" 1603 " .Padding_16 = 0x%04x\n", 1604 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 1605 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 1606 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 1607 pptable->DpmDescriptor[PPCLK_FCLK].padding, 1608 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 1609 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 1610 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 1611 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 1612 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 1613 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 1614 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 1615 1616 1617 dev_info(smu->adev->dev, "FreqTableGfx\n"); 1618 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 1619 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]); 1620 1621 dev_info(smu->adev->dev, "FreqTableVclk\n"); 1622 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 1623 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]); 1624 1625 dev_info(smu->adev->dev, "FreqTableDclk\n"); 1626 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 1627 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]); 1628 1629 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 1630 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 1631 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]); 1632 1633 dev_info(smu->adev->dev, "FreqTableUclk\n"); 1634 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 1635 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]); 1636 1637 dev_info(smu->adev->dev, "FreqTableFclk\n"); 1638 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 1639 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]); 1640 1641 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 1642 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1643 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]); 1644 1645 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 1646 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1647 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]); 1648 1649 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 1650 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate); 1651 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]); 1652 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]); 1653 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]); 1654 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]); 1655 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq); 1656 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 1657 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456); 1658 1659 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm); 1660 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature); 1661 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature); 1662 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit); 1663 1664 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp); 1665 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp); 1666 1667 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge); 1668 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot); 1669 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx); 1670 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc); 1671 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem); 1672 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm); 1673 1674 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin); 1675 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm); 1676 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm); 1677 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm); 1678 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature); 1679 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk); 1680 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable); 1681 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev); 1682 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect); 1683 1684 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta); 1685 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta); 1686 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta); 1687 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved); 1688 1689 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 1690 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 1691 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]); 1692 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]); 1693 1694 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 1695 pptable->dBtcGbGfxPll.a, 1696 pptable->dBtcGbGfxPll.b, 1697 pptable->dBtcGbGfxPll.c); 1698 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 1699 pptable->dBtcGbGfxAfll.a, 1700 pptable->dBtcGbGfxAfll.b, 1701 pptable->dBtcGbGfxAfll.c); 1702 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 1703 pptable->dBtcGbSoc.a, 1704 pptable->dBtcGbSoc.b, 1705 pptable->dBtcGbSoc.c); 1706 1707 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 1708 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 1709 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 1710 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 1711 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 1712 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 1713 1714 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 1715 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 1716 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 1717 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 1718 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 1719 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 1720 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 1721 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 1722 1723 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 1724 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 1725 1726 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 1727 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 1728 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 1729 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 1730 1731 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 1732 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 1733 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 1734 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 1735 1736 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 1737 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 1738 1739 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 1740 for (i = 0; i < NUM_XGMI_LEVELS; i++) 1741 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]); 1742 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 1743 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 1744 1745 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin); 1746 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin); 1747 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp); 1748 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp); 1749 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp); 1750 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp); 1751 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis); 1752 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis); 1753 1754 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 1755 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 1756 pptable->ReservedEquation0.a, 1757 pptable->ReservedEquation0.b, 1758 pptable->ReservedEquation0.c); 1759 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 1760 pptable->ReservedEquation1.a, 1761 pptable->ReservedEquation1.b, 1762 pptable->ReservedEquation1.c); 1763 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 1764 pptable->ReservedEquation2.a, 1765 pptable->ReservedEquation2.b, 1766 pptable->ReservedEquation2.c); 1767 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 1768 pptable->ReservedEquation3.a, 1769 pptable->ReservedEquation3.b, 1770 pptable->ReservedEquation3.c); 1771 1772 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); 1773 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv); 1774 1775 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig); 1776 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1); 1777 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2); 1778 1779 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow); 1780 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh); 1781 1782 dev_info(smu->adev->dev, "Board Parameters:\n"); 1783 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); 1784 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); 1785 1786 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 1787 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 1788 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping); 1789 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping); 1790 1791 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 1792 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent); 1793 1794 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 1795 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 1796 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 1797 1798 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 1799 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 1800 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 1801 1802 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent); 1803 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset); 1804 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem); 1805 1806 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent); 1807 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset); 1808 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput); 1809 1810 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio); 1811 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity); 1812 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio); 1813 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity); 1814 1815 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled); 1816 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent); 1817 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq); 1818 1819 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled); 1820 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent); 1821 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq); 1822 1823 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled); 1824 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent); 1825 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq); 1826 1827 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled); 1828 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); 1829 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); 1830 1831 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 1832 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 1833 dev_info(smu->adev->dev, " .Enabled = %d\n", 1834 pptable->I2cControllers[i].Enabled); 1835 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 1836 pptable->I2cControllers[i].SlaveAddress); 1837 dev_info(smu->adev->dev, " .ControllerPort = %d\n", 1838 pptable->I2cControllers[i].ControllerPort); 1839 dev_info(smu->adev->dev, " .ControllerName = %d\n", 1840 pptable->I2cControllers[i].ControllerName); 1841 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n", 1842 pptable->I2cControllers[i].ThermalThrotter); 1843 dev_info(smu->adev->dev, " .I2cProtocol = %d\n", 1844 pptable->I2cControllers[i].I2cProtocol); 1845 dev_info(smu->adev->dev, " .Speed = %d\n", 1846 pptable->I2cControllers[i].Speed); 1847 } 1848 1849 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled); 1850 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth); 1851 1852 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower); 1853 1854 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 1855 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 1856 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]); 1857 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 1858 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 1859 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]); 1860 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 1861 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 1862 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]); 1863 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 1864 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 1865 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]); 1866 1867 } 1868 1869 static bool arcturus_is_dpm_running(struct smu_context *smu) 1870 { 1871 int ret = 0; 1872 uint32_t feature_mask[2]; 1873 uint64_t feature_enabled; 1874 1875 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 1876 if (ret) 1877 return false; 1878 1879 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 1880 1881 return !!(feature_enabled & SMC_DPM_FEATURE); 1882 } 1883 1884 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 1885 { 1886 int ret = 0; 1887 1888 if (enable) { 1889 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1890 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1); 1891 if (ret) { 1892 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n"); 1893 return ret; 1894 } 1895 } 1896 } else { 1897 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { 1898 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0); 1899 if (ret) { 1900 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n"); 1901 return ret; 1902 } 1903 } 1904 } 1905 1906 return ret; 1907 } 1908 1909 static void arcturus_fill_i2c_req(SwI2cRequest_t *req, bool write, 1910 uint8_t address, uint32_t numbytes, 1911 uint8_t *data) 1912 { 1913 int i; 1914 1915 req->I2CcontrollerPort = 0; 1916 req->I2CSpeed = 2; 1917 req->SlaveAddress = address; 1918 req->NumCmds = numbytes; 1919 1920 for (i = 0; i < numbytes; i++) { 1921 SwI2cCmd_t *cmd = &req->SwI2cCmds[i]; 1922 1923 /* First 2 bytes are always write for lower 2b EEPROM address */ 1924 if (i < 2) 1925 cmd->Cmd = 1; 1926 else 1927 cmd->Cmd = write; 1928 1929 1930 /* Add RESTART for read after address filled */ 1931 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0; 1932 1933 /* Add STOP in the end */ 1934 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0; 1935 1936 /* Fill with data regardless if read or write to simplify code */ 1937 cmd->RegisterAddr = data[i]; 1938 } 1939 } 1940 1941 static int arcturus_i2c_read_data(struct i2c_adapter *control, 1942 uint8_t address, 1943 uint8_t *data, 1944 uint32_t numbytes) 1945 { 1946 uint32_t i, ret = 0; 1947 SwI2cRequest_t req; 1948 struct amdgpu_device *adev = to_amdgpu_device(control); 1949 struct smu_table_context *smu_table = &adev->smu.smu_table; 1950 struct smu_table *table = &smu_table->driver_table; 1951 1952 if (numbytes > MAX_SW_I2C_COMMANDS) { 1953 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 1954 numbytes, MAX_SW_I2C_COMMANDS); 1955 return -EINVAL; 1956 } 1957 1958 memset(&req, 0, sizeof(req)); 1959 arcturus_fill_i2c_req(&req, false, address, numbytes, data); 1960 1961 mutex_lock(&adev->smu.mutex); 1962 /* Now read data starting with that address */ 1963 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, 1964 true); 1965 mutex_unlock(&adev->smu.mutex); 1966 1967 if (!ret) { 1968 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr; 1969 1970 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */ 1971 for (i = 0; i < numbytes; i++) 1972 data[i] = res->SwI2cCmds[i].Data; 1973 1974 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :", 1975 (uint16_t)address, numbytes); 1976 1977 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 1978 8, 1, data, numbytes, false); 1979 } else 1980 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret); 1981 1982 return ret; 1983 } 1984 1985 static int arcturus_i2c_write_data(struct i2c_adapter *control, 1986 uint8_t address, 1987 uint8_t *data, 1988 uint32_t numbytes) 1989 { 1990 uint32_t ret; 1991 SwI2cRequest_t req; 1992 struct amdgpu_device *adev = to_amdgpu_device(control); 1993 1994 if (numbytes > MAX_SW_I2C_COMMANDS) { 1995 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n", 1996 numbytes, MAX_SW_I2C_COMMANDS); 1997 return -EINVAL; 1998 } 1999 2000 memset(&req, 0, sizeof(req)); 2001 arcturus_fill_i2c_req(&req, true, address, numbytes, data); 2002 2003 mutex_lock(&adev->smu.mutex); 2004 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true); 2005 mutex_unlock(&adev->smu.mutex); 2006 2007 if (!ret) { 2008 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ", 2009 (uint16_t)address, numbytes); 2010 2011 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE, 2012 8, 1, data, numbytes, false); 2013 /* 2014 * According to EEPROM spec there is a MAX of 10 ms required for 2015 * EEPROM to flush internal RX buffer after STOP was issued at the 2016 * end of write transaction. During this time the EEPROM will not be 2017 * responsive to any more commands - so wait a bit more. 2018 */ 2019 msleep(10); 2020 2021 } else 2022 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret); 2023 2024 return ret; 2025 } 2026 2027 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap, 2028 struct i2c_msg *msgs, int num) 2029 { 2030 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0; 2031 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 }; 2032 2033 for (i = 0; i < num; i++) { 2034 /* 2035 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at 2036 * once and hence the data needs to be spliced into chunks and sent each 2037 * chunk separately 2038 */ 2039 data_size = msgs[i].len - 2; 2040 data_chunk_size = MAX_SW_I2C_COMMANDS - 2; 2041 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff); 2042 data_ptr = msgs[i].buf + 2; 2043 2044 for (j = 0; j < data_size / data_chunk_size; j++) { 2045 /* Insert the EEPROM dest addess, bits 0-15 */ 2046 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 2047 data_chunk[1] = (next_eeprom_addr & 0xff); 2048 2049 if (msgs[i].flags & I2C_M_RD) { 2050 ret = arcturus_i2c_read_data(i2c_adap, 2051 (uint8_t)msgs[i].addr, 2052 data_chunk, MAX_SW_I2C_COMMANDS); 2053 2054 memcpy(data_ptr, data_chunk + 2, data_chunk_size); 2055 } else { 2056 2057 memcpy(data_chunk + 2, data_ptr, data_chunk_size); 2058 2059 ret = arcturus_i2c_write_data(i2c_adap, 2060 (uint8_t)msgs[i].addr, 2061 data_chunk, MAX_SW_I2C_COMMANDS); 2062 } 2063 2064 if (ret) { 2065 num = -EIO; 2066 goto fail; 2067 } 2068 2069 next_eeprom_addr += data_chunk_size; 2070 data_ptr += data_chunk_size; 2071 } 2072 2073 if (data_size % data_chunk_size) { 2074 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff); 2075 data_chunk[1] = (next_eeprom_addr & 0xff); 2076 2077 if (msgs[i].flags & I2C_M_RD) { 2078 ret = arcturus_i2c_read_data(i2c_adap, 2079 (uint8_t)msgs[i].addr, 2080 data_chunk, (data_size % data_chunk_size) + 2); 2081 2082 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size); 2083 } else { 2084 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size); 2085 2086 ret = arcturus_i2c_write_data(i2c_adap, 2087 (uint8_t)msgs[i].addr, 2088 data_chunk, (data_size % data_chunk_size) + 2); 2089 } 2090 2091 if (ret) { 2092 num = -EIO; 2093 goto fail; 2094 } 2095 } 2096 } 2097 2098 fail: 2099 return num; 2100 } 2101 2102 static u32 arcturus_i2c_func(struct i2c_adapter *adap) 2103 { 2104 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2105 } 2106 2107 2108 static const struct i2c_algorithm arcturus_i2c_algo = { 2109 .master_xfer = arcturus_i2c_xfer, 2110 .functionality = arcturus_i2c_func, 2111 }; 2112 2113 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 2114 { 2115 struct amdgpu_device *adev = to_amdgpu_device(control); 2116 int res; 2117 2118 control->owner = THIS_MODULE; 2119 control->class = I2C_CLASS_SPD; 2120 control->dev.parent = &adev->pdev->dev; 2121 control->algo = &arcturus_i2c_algo; 2122 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 2123 2124 res = i2c_add_adapter(control); 2125 if (res) 2126 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2127 2128 return res; 2129 } 2130 2131 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 2132 { 2133 i2c_del_adapter(control); 2134 } 2135 2136 static void arcturus_get_unique_id(struct smu_context *smu) 2137 { 2138 struct amdgpu_device *adev = smu->adev; 2139 uint32_t top32 = 0, bottom32 = 0, smu_version; 2140 uint64_t id; 2141 2142 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) { 2143 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n"); 2144 return; 2145 } 2146 2147 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */ 2148 if (smu_version < 0x361700) { 2149 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n"); 2150 return; 2151 } 2152 2153 /* Get the SN to turn into a Unique ID */ 2154 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32); 2155 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32); 2156 2157 id = ((uint64_t)bottom32 << 32) | top32; 2158 adev->unique_id = id; 2159 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a 2160 * 16-digit HEX string for convenience and backwards-compatibility 2161 */ 2162 sprintf(adev->serial, "%llx", id); 2163 } 2164 2165 static int arcturus_set_df_cstate(struct smu_context *smu, 2166 enum pp_df_cstate state) 2167 { 2168 uint32_t smu_version; 2169 int ret; 2170 2171 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2172 if (ret) { 2173 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2174 return ret; 2175 } 2176 2177 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */ 2178 if (smu_version < 0x360F00) { 2179 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n"); 2180 return -EINVAL; 2181 } 2182 2183 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 2184 } 2185 2186 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en) 2187 { 2188 uint32_t smu_version; 2189 int ret; 2190 2191 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2192 if (ret) { 2193 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2194 return ret; 2195 } 2196 2197 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */ 2198 if (smu_version < 0x00361700) { 2199 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n"); 2200 return -EINVAL; 2201 } 2202 2203 if (en) 2204 return smu_cmn_send_smc_msg_with_param(smu, 2205 SMU_MSG_GmiPwrDnControl, 2206 1, 2207 NULL); 2208 2209 return smu_cmn_send_smc_msg_with_param(smu, 2210 SMU_MSG_GmiPwrDnControl, 2211 0, 2212 NULL); 2213 } 2214 2215 static const struct throttling_logging_label { 2216 uint32_t feature_mask; 2217 const char *label; 2218 } logging_label[] = { 2219 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"}, 2220 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 2221 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 2222 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 2223 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 2224 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"}, 2225 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"}, 2226 }; 2227 static void arcturus_log_thermal_throttling_event(struct smu_context *smu) 2228 { 2229 int ret; 2230 int throttler_idx, throtting_events = 0, buf_idx = 0; 2231 struct amdgpu_device *adev = smu->adev; 2232 uint32_t throttler_status; 2233 char log_buf[256]; 2234 2235 ret = arcturus_get_smu_metrics_data(smu, 2236 METRICS_THROTTLER_STATUS, 2237 &throttler_status); 2238 if (ret) 2239 return; 2240 2241 memset(log_buf, 0, sizeof(log_buf)); 2242 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 2243 throttler_idx++) { 2244 if (throttler_status & logging_label[throttler_idx].feature_mask) { 2245 throtting_events++; 2246 buf_idx += snprintf(log_buf + buf_idx, 2247 sizeof(log_buf) - buf_idx, 2248 "%s%s", 2249 throtting_events > 1 ? " and " : "", 2250 logging_label[throttler_idx].label); 2251 if (buf_idx >= sizeof(log_buf)) { 2252 dev_err(adev->dev, "buffer overflow!\n"); 2253 log_buf[sizeof(log_buf) - 1] = '\0'; 2254 break; 2255 } 2256 } 2257 } 2258 2259 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 2260 log_buf); 2261 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status); 2262 } 2263 2264 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu) 2265 { 2266 struct amdgpu_device *adev = smu->adev; 2267 uint32_t esm_ctrl; 2268 2269 /* TODO: confirm this on real target */ 2270 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 2271 if ((esm_ctrl >> 15) & 0x1FFFF) 2272 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128); 2273 2274 return smu_v11_0_get_current_pcie_link_speed(smu); 2275 } 2276 2277 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, 2278 void **table) 2279 { 2280 struct smu_table_context *smu_table = &smu->smu_table; 2281 struct gpu_metrics_v1_1 *gpu_metrics = 2282 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table; 2283 SmuMetrics_t metrics; 2284 int ret = 0; 2285 2286 ret = smu_cmn_get_metrics_table(smu, 2287 &metrics, 2288 true); 2289 if (ret) 2290 return ret; 2291 2292 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1); 2293 2294 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2295 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2296 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2297 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2298 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2299 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2300 2301 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2302 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2303 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 2304 2305 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2306 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 2307 2308 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2309 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2310 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2311 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 2312 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 2313 2314 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2315 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2316 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2317 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2318 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2319 2320 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2321 2322 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2323 2324 gpu_metrics->pcie_link_width = 2325 smu_v11_0_get_current_pcie_link_width(smu); 2326 gpu_metrics->pcie_link_speed = 2327 arcturus_get_current_pcie_link_speed(smu); 2328 2329 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2330 2331 *table = (void *)gpu_metrics; 2332 2333 return sizeof(struct gpu_metrics_v1_1); 2334 } 2335 2336 static const struct pptable_funcs arcturus_ppt_funcs = { 2337 /* init dpm */ 2338 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, 2339 /* btc */ 2340 .run_btc = arcturus_run_btc, 2341 /* dpm/clk tables */ 2342 .set_default_dpm_table = arcturus_set_default_dpm_table, 2343 .populate_umd_state_clk = arcturus_populate_umd_state_clk, 2344 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range, 2345 .print_clk_levels = arcturus_print_clk_levels, 2346 .force_clk_levels = arcturus_force_clk_levels, 2347 .read_sensor = arcturus_read_sensor, 2348 .get_fan_speed_percent = arcturus_get_fan_speed_percent, 2349 .get_power_profile_mode = arcturus_get_power_profile_mode, 2350 .set_power_profile_mode = arcturus_set_power_profile_mode, 2351 .set_performance_level = arcturus_set_performance_level, 2352 /* debug (internal used) */ 2353 .dump_pptable = arcturus_dump_pptable, 2354 .get_power_limit = arcturus_get_power_limit, 2355 .is_dpm_running = arcturus_is_dpm_running, 2356 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable, 2357 .i2c_init = arcturus_i2c_control_init, 2358 .i2c_fini = arcturus_i2c_control_fini, 2359 .get_unique_id = arcturus_get_unique_id, 2360 .init_microcode = smu_v11_0_init_microcode, 2361 .load_microcode = smu_v11_0_load_microcode, 2362 .fini_microcode = smu_v11_0_fini_microcode, 2363 .init_smc_tables = arcturus_init_smc_tables, 2364 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2365 .init_power = smu_v11_0_init_power, 2366 .fini_power = smu_v11_0_fini_power, 2367 .check_fw_status = smu_v11_0_check_fw_status, 2368 /* pptable related */ 2369 .setup_pptable = arcturus_setup_pptable, 2370 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2371 .check_fw_version = smu_v11_0_check_fw_version, 2372 .write_pptable = smu_cmn_write_pptable, 2373 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2374 .set_tool_table_location = smu_v11_0_set_tool_table_location, 2375 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2376 .system_features_control = smu_v11_0_system_features_control, 2377 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2378 .send_smc_msg = smu_cmn_send_smc_msg, 2379 .init_display_count = NULL, 2380 .set_allowed_mask = smu_v11_0_set_allowed_mask, 2381 .get_enabled_mask = smu_cmn_get_enabled_mask, 2382 .feature_is_enabled = smu_cmn_feature_is_enabled, 2383 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2384 .notify_display_change = NULL, 2385 .set_power_limit = smu_v11_0_set_power_limit, 2386 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 2387 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 2388 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 2389 .set_min_dcef_deep_sleep = NULL, 2390 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 2391 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 2392 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 2393 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, 2394 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 2395 .gfx_off_control = smu_v11_0_gfx_off_control, 2396 .register_irq_handler = smu_v11_0_register_irq_handler, 2397 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 2398 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 2399 .baco_is_support = smu_v11_0_baco_is_support, 2400 .baco_get_state = smu_v11_0_baco_get_state, 2401 .baco_set_state = smu_v11_0_baco_set_state, 2402 .baco_enter = smu_v11_0_baco_enter, 2403 .baco_exit = smu_v11_0_baco_exit, 2404 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 2405 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 2406 .set_df_cstate = arcturus_set_df_cstate, 2407 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, 2408 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, 2409 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2410 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2411 .get_gpu_metrics = arcturus_get_gpu_metrics, 2412 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 2413 .deep_sleep_control = smu_v11_0_deep_sleep_control, 2414 .get_fan_parameters = arcturus_get_fan_parameters, 2415 .interrupt_work = smu_v11_0_interrupt_work, 2416 .set_light_sbr = smu_v11_0_set_light_sbr, 2417 .set_mp1_state = smu_cmn_set_mp1_state, 2418 }; 2419 2420 void arcturus_set_ppt_funcs(struct smu_context *smu) 2421 { 2422 smu->ppt_funcs = &arcturus_ppt_funcs; 2423 smu->message_map = arcturus_message_map; 2424 smu->clock_map = arcturus_clk_map; 2425 smu->feature_map = arcturus_feature_mask_map; 2426 smu->table_map = arcturus_table_map; 2427 smu->pwr_src_map = arcturus_pwr_src_map; 2428 smu->workload_map = arcturus_workload_map; 2429 } 2430