1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v11_0.h"
33 #include "smu11_driver_if_arcturus.h"
34 #include "soc15_common.h"
35 #include "atom.h"
36 #include "power_state.h"
37 #include "arcturus_ppt.h"
38 #include "smu_v11_0_pptable.h"
39 #include "arcturus_ppsmc.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/i2c.h>
46 #include <linux/pci.h>
47 #include "amdgpu_ras.h"
48 #include "smu_cmn.h"
49 
50 /*
51  * DO NOT use these for err/warn/info/debug messages.
52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53  * They are more MGPU friendly.
54  */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59 
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61 
62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
63 	[smu_feature] = {1, (arcturus_feature)}
64 
65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
66 #define SMU_FEATURES_LOW_SHIFT       0
67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
68 #define SMU_FEATURES_HIGH_SHIFT      32
69 
70 #define SMC_DPM_FEATURE ( \
71 	FEATURE_DPM_PREFETCHER_MASK | \
72 	FEATURE_DPM_GFXCLK_MASK | \
73 	FEATURE_DPM_UCLK_MASK | \
74 	FEATURE_DPM_SOCCLK_MASK | \
75 	FEATURE_DPM_MP0CLK_MASK | \
76 	FEATURE_DPM_FCLK_MASK | \
77 	FEATURE_DPM_XGMI_MASK)
78 
79 /* possible frequency drift (1Mhz) */
80 #define EPSILON				1
81 
82 #define smnPCIE_ESM_CTRL			0x111003D0
83 
84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
85 	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage,			0),
86 	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion,			1),
87 	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion,		1),
88 	MSG_MAP(SetAllowedFeaturesMaskLow,	     PPSMC_MSG_SetAllowedFeaturesMaskLow,	0),
89 	MSG_MAP(SetAllowedFeaturesMaskHigh,	     PPSMC_MSG_SetAllowedFeaturesMaskHigh,	0),
90 	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures,		0),
91 	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures,		0),
92 	MSG_MAP(EnableSmuFeaturesLow,		     PPSMC_MSG_EnableSmuFeaturesLow,		1),
93 	MSG_MAP(EnableSmuFeaturesHigh,		     PPSMC_MSG_EnableSmuFeaturesHigh,		1),
94 	MSG_MAP(DisableSmuFeaturesLow,		     PPSMC_MSG_DisableSmuFeaturesLow,		0),
95 	MSG_MAP(DisableSmuFeaturesHigh,		     PPSMC_MSG_DisableSmuFeaturesHigh,		0),
96 	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow,	0),
97 	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh,	0),
98 	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh,		1),
99 	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow,		1),
100 	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh,		0),
101 	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow,		0),
102 	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram,		1),
103 	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu,		0),
104 	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable,		0),
105 	MSG_MAP(UseBackupPPTable,		     PPSMC_MSG_UseBackupPPTable,		0),
106 	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh,	0),
107 	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow,	0),
108 	MSG_MAP(EnterBaco,			     PPSMC_MSG_EnterBaco,			0),
109 	MSG_MAP(ExitBaco,			     PPSMC_MSG_ExitBaco,			0),
110 	MSG_MAP(ArmD3,				     PPSMC_MSG_ArmD3,				0),
111 	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq,		0),
112 	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq,		0),
113 	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq,		0),
114 	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq,		0),
115 	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq,			0),
116 	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq,			0),
117 	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex,		1),
118 	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask,			1),
119 	MSG_MAP(SetDfSwitchType,		     PPSMC_MSG_SetDfSwitchType,			0),
120 	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm,			0),
121 	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive,	0),
122 	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit,			0),
123 	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit,			1),
124 	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0,			0),
125 	MSG_MAP(PowerDownVcn0,			     PPSMC_MSG_PowerDownVcn0,			0),
126 	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1,			0),
127 	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1,			0),
128 	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload,		0),
129 	MSG_MAP(PrepareMp1ForReset,		     PPSMC_MSG_PrepareMp1ForReset,		0),
130 	MSG_MAP(PrepareMp1ForShutdown,		     PPSMC_MSG_PrepareMp1ForShutdown,		0),
131 	MSG_MAP(SoftReset,			     PPSMC_MSG_SoftReset,			0),
132 	MSG_MAP(RunAfllBtc,			     PPSMC_MSG_RunAfllBtc,			0),
133 	MSG_MAP(RunDcBtc,			     PPSMC_MSG_RunDcBtc,			0),
134 	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh,		0),
135 	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow,		0),
136 	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize,		0),
137 	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData,			0),
138 	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest,			0),
139 	MSG_MAP(SetXgmiMode,			     PPSMC_MSG_SetXgmiMode,			0),
140 	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable,		0),
141 	MSG_MAP(DFCstateControl,		     PPSMC_MSG_DFCstateControl,			0),
142 	MSG_MAP(GmiPwrDnControl,		     PPSMC_MSG_GmiPwrDnControl,			0),
143 	MSG_MAP(ReadSerialNumTop32,		     PPSMC_MSG_ReadSerialNumTop32,		1),
144 	MSG_MAP(ReadSerialNumBottom32,		     PPSMC_MSG_ReadSerialNumBottom32,		1),
145 };
146 
147 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
148 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
149 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
150 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
151 	CLK_MAP(FCLK, PPCLK_FCLK),
152 	CLK_MAP(UCLK, PPCLK_UCLK),
153 	CLK_MAP(MCLK, PPCLK_UCLK),
154 	CLK_MAP(DCLK, PPCLK_DCLK),
155 	CLK_MAP(VCLK, PPCLK_VCLK),
156 };
157 
158 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
159 	FEA_MAP(DPM_PREFETCHER),
160 	FEA_MAP(DPM_GFXCLK),
161 	FEA_MAP(DPM_UCLK),
162 	FEA_MAP(DPM_SOCCLK),
163 	FEA_MAP(DPM_FCLK),
164 	FEA_MAP(DPM_MP0CLK),
165 	ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
166 	FEA_MAP(DS_GFXCLK),
167 	FEA_MAP(DS_SOCCLK),
168 	FEA_MAP(DS_LCLK),
169 	FEA_MAP(DS_FCLK),
170 	FEA_MAP(DS_UCLK),
171 	FEA_MAP(GFX_ULV),
172 	ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
173 	FEA_MAP(RSMU_SMN_CG),
174 	FEA_MAP(WAFL_CG),
175 	FEA_MAP(PPT),
176 	FEA_MAP(TDC),
177 	FEA_MAP(APCC_PLUS),
178 	FEA_MAP(VR0HOT),
179 	FEA_MAP(VR1HOT),
180 	FEA_MAP(FW_CTF),
181 	FEA_MAP(FAN_CONTROL),
182 	FEA_MAP(THERMAL),
183 	FEA_MAP(OUT_OF_BAND_MONITOR),
184 	FEA_MAP(TEMP_DEPENDENT_VMIN),
185 };
186 
187 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
188 	TAB_MAP(PPTABLE),
189 	TAB_MAP(AVFS),
190 	TAB_MAP(AVFS_PSM_DEBUG),
191 	TAB_MAP(AVFS_FUSE_OVERRIDE),
192 	TAB_MAP(PMSTATUSLOG),
193 	TAB_MAP(SMU_METRICS),
194 	TAB_MAP(DRIVER_SMU_CONFIG),
195 	TAB_MAP(OVERDRIVE),
196 	TAB_MAP(I2C_COMMANDS),
197 	TAB_MAP(ACTIVITY_MONITOR_COEFF),
198 };
199 
200 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
201 	PWR_MAP(AC),
202 	PWR_MAP(DC),
203 };
204 
205 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
206 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
207 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
208 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
209 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
210 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
211 };
212 
213 static int arcturus_tables_init(struct smu_context *smu)
214 {
215 	struct smu_table_context *smu_table = &smu->smu_table;
216 	struct smu_table *tables = smu_table->tables;
217 
218 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
219 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
220 
221 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
222 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223 
224 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
225 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
226 
227 	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
228 			       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
229 
230 	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
231 		       sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
232 		       AMDGPU_GEM_DOMAIN_VRAM);
233 
234 	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
235 	if (!smu_table->metrics_table)
236 		return -ENOMEM;
237 	smu_table->metrics_time = 0;
238 
239 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
240 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
241 	if (!smu_table->gpu_metrics_table) {
242 		kfree(smu_table->metrics_table);
243 		return -ENOMEM;
244 	}
245 
246 	return 0;
247 }
248 
249 static int arcturus_allocate_dpm_context(struct smu_context *smu)
250 {
251 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
252 
253 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
254 				       GFP_KERNEL);
255 	if (!smu_dpm->dpm_context)
256 		return -ENOMEM;
257 	smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
258 
259 	smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
260 				       GFP_KERNEL);
261 	if (!smu_dpm->dpm_current_power_state)
262 		return -ENOMEM;
263 
264 	smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
265 				       GFP_KERNEL);
266 	if (!smu_dpm->dpm_request_power_state)
267 		return -ENOMEM;
268 
269 	return 0;
270 }
271 
272 static int arcturus_init_smc_tables(struct smu_context *smu)
273 {
274 	int ret = 0;
275 
276 	ret = arcturus_tables_init(smu);
277 	if (ret)
278 		return ret;
279 
280 	ret = arcturus_allocate_dpm_context(smu);
281 	if (ret)
282 		return ret;
283 
284 	return smu_v11_0_init_smc_tables(smu);
285 }
286 
287 static int
288 arcturus_get_allowed_feature_mask(struct smu_context *smu,
289 				  uint32_t *feature_mask, uint32_t num)
290 {
291 	if (num > 2)
292 		return -EINVAL;
293 
294 	/* pptable will handle the features to enable */
295 	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
296 
297 	return 0;
298 }
299 
300 static int arcturus_set_default_dpm_table(struct smu_context *smu)
301 {
302 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
303 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
304 	struct smu_11_0_dpm_table *dpm_table = NULL;
305 	int ret = 0;
306 
307 	/* socclk dpm table setup */
308 	dpm_table = &dpm_context->dpm_tables.soc_table;
309 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
310 		ret = smu_v11_0_set_single_dpm_table(smu,
311 						     SMU_SOCCLK,
312 						     dpm_table);
313 		if (ret)
314 			return ret;
315 		dpm_table->is_fine_grained =
316 			!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
317 	} else {
318 		dpm_table->count = 1;
319 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
320 		dpm_table->dpm_levels[0].enabled = true;
321 		dpm_table->min = dpm_table->dpm_levels[0].value;
322 		dpm_table->max = dpm_table->dpm_levels[0].value;
323 	}
324 
325 	/* gfxclk dpm table setup */
326 	dpm_table = &dpm_context->dpm_tables.gfx_table;
327 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
328 		ret = smu_v11_0_set_single_dpm_table(smu,
329 						     SMU_GFXCLK,
330 						     dpm_table);
331 		if (ret)
332 			return ret;
333 		dpm_table->is_fine_grained =
334 			!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
335 	} else {
336 		dpm_table->count = 1;
337 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
338 		dpm_table->dpm_levels[0].enabled = true;
339 		dpm_table->min = dpm_table->dpm_levels[0].value;
340 		dpm_table->max = dpm_table->dpm_levels[0].value;
341 	}
342 
343 	/* memclk dpm table setup */
344 	dpm_table = &dpm_context->dpm_tables.uclk_table;
345 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
346 		ret = smu_v11_0_set_single_dpm_table(smu,
347 						     SMU_UCLK,
348 						     dpm_table);
349 		if (ret)
350 			return ret;
351 		dpm_table->is_fine_grained =
352 			!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
353 	} else {
354 		dpm_table->count = 1;
355 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
356 		dpm_table->dpm_levels[0].enabled = true;
357 		dpm_table->min = dpm_table->dpm_levels[0].value;
358 		dpm_table->max = dpm_table->dpm_levels[0].value;
359 	}
360 
361 	/* fclk dpm table setup */
362 	dpm_table = &dpm_context->dpm_tables.fclk_table;
363 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
364 		ret = smu_v11_0_set_single_dpm_table(smu,
365 						     SMU_FCLK,
366 						     dpm_table);
367 		if (ret)
368 			return ret;
369 		dpm_table->is_fine_grained =
370 			!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
371 	} else {
372 		dpm_table->count = 1;
373 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
374 		dpm_table->dpm_levels[0].enabled = true;
375 		dpm_table->min = dpm_table->dpm_levels[0].value;
376 		dpm_table->max = dpm_table->dpm_levels[0].value;
377 	}
378 
379 	return 0;
380 }
381 
382 static int arcturus_check_powerplay_table(struct smu_context *smu)
383 {
384 	struct smu_table_context *table_context = &smu->smu_table;
385 	struct smu_11_0_powerplay_table *powerplay_table =
386 		table_context->power_play_table;
387 	struct smu_baco_context *smu_baco = &smu->smu_baco;
388 
389 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
390 	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
391 		smu_baco->platform_support = true;
392 
393 	table_context->thermal_controller_type =
394 		powerplay_table->thermal_controller_type;
395 
396 	return 0;
397 }
398 
399 static int arcturus_store_powerplay_table(struct smu_context *smu)
400 {
401 	struct smu_table_context *table_context = &smu->smu_table;
402 	struct smu_11_0_powerplay_table *powerplay_table =
403 		table_context->power_play_table;
404 
405 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
406 	       sizeof(PPTable_t));
407 
408 	return 0;
409 }
410 
411 static int arcturus_append_powerplay_table(struct smu_context *smu)
412 {
413 	struct smu_table_context *table_context = &smu->smu_table;
414 	PPTable_t *smc_pptable = table_context->driver_pptable;
415 	struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
416 	int index, ret;
417 
418 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
419 					   smc_dpm_info);
420 
421 	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
422 				      (uint8_t **)&smc_dpm_table);
423 	if (ret)
424 		return ret;
425 
426 	dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
427 			smc_dpm_table->table_header.format_revision,
428 			smc_dpm_table->table_header.content_revision);
429 
430 	if ((smc_dpm_table->table_header.format_revision == 4) &&
431 	    (smc_dpm_table->table_header.content_revision == 6))
432 		memcpy(&smc_pptable->MaxVoltageStepGfx,
433 		       &smc_dpm_table->maxvoltagestepgfx,
434 		       sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
435 
436 	return 0;
437 }
438 
439 static int arcturus_setup_pptable(struct smu_context *smu)
440 {
441 	int ret = 0;
442 
443 	ret = smu_v11_0_setup_pptable(smu);
444 	if (ret)
445 		return ret;
446 
447 	ret = arcturus_store_powerplay_table(smu);
448 	if (ret)
449 		return ret;
450 
451 	ret = arcturus_append_powerplay_table(smu);
452 	if (ret)
453 		return ret;
454 
455 	ret = arcturus_check_powerplay_table(smu);
456 	if (ret)
457 		return ret;
458 
459 	return ret;
460 }
461 
462 static int arcturus_run_btc(struct smu_context *smu)
463 {
464 	int ret = 0;
465 
466 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
467 	if (ret) {
468 		dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
469 		return ret;
470 	}
471 
472 	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
473 }
474 
475 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
476 {
477 	struct smu_11_0_dpm_context *dpm_context =
478 				smu->smu_dpm.dpm_context;
479 	struct smu_11_0_dpm_table *gfx_table =
480 				&dpm_context->dpm_tables.gfx_table;
481 	struct smu_11_0_dpm_table *mem_table =
482 				&dpm_context->dpm_tables.uclk_table;
483 	struct smu_11_0_dpm_table *soc_table =
484 				&dpm_context->dpm_tables.soc_table;
485 	struct smu_umd_pstate_table *pstate_table =
486 				&smu->pstate_table;
487 
488 	pstate_table->gfxclk_pstate.min = gfx_table->min;
489 	pstate_table->gfxclk_pstate.peak = gfx_table->max;
490 
491 	pstate_table->uclk_pstate.min = mem_table->min;
492 	pstate_table->uclk_pstate.peak = mem_table->max;
493 
494 	pstate_table->socclk_pstate.min = soc_table->min;
495 	pstate_table->socclk_pstate.peak = soc_table->max;
496 
497 	if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
498 	    mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
499 	    soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
500 		pstate_table->gfxclk_pstate.standard =
501 			gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
502 		pstate_table->uclk_pstate.standard =
503 			mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
504 		pstate_table->socclk_pstate.standard =
505 			soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
506 	} else {
507 		pstate_table->gfxclk_pstate.standard =
508 			pstate_table->gfxclk_pstate.min;
509 		pstate_table->uclk_pstate.standard =
510 			pstate_table->uclk_pstate.min;
511 		pstate_table->socclk_pstate.standard =
512 			pstate_table->socclk_pstate.min;
513 	}
514 
515 	return 0;
516 }
517 
518 static int arcturus_get_clk_table(struct smu_context *smu,
519 			struct pp_clock_levels_with_latency *clocks,
520 			struct smu_11_0_dpm_table *dpm_table)
521 {
522 	int i, count;
523 
524 	count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
525 	clocks->num_levels = count;
526 
527 	for (i = 0; i < count; i++) {
528 		clocks->data[i].clocks_in_khz =
529 			dpm_table->dpm_levels[i].value * 1000;
530 		clocks->data[i].latency_in_us = 0;
531 	}
532 
533 	return 0;
534 }
535 
536 static int arcturus_freqs_in_same_level(int32_t frequency1,
537 					int32_t frequency2)
538 {
539 	return (abs(frequency1 - frequency2) <= EPSILON);
540 }
541 
542 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
543 					 MetricsMember_t member,
544 					 uint32_t *value)
545 {
546 	struct smu_table_context *smu_table= &smu->smu_table;
547 	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
548 	int ret = 0;
549 
550 	mutex_lock(&smu->metrics_lock);
551 
552 	ret = smu_cmn_get_metrics_table_locked(smu,
553 					       NULL,
554 					       false);
555 	if (ret) {
556 		mutex_unlock(&smu->metrics_lock);
557 		return ret;
558 	}
559 
560 	switch (member) {
561 	case METRICS_CURR_GFXCLK:
562 		*value = metrics->CurrClock[PPCLK_GFXCLK];
563 		break;
564 	case METRICS_CURR_SOCCLK:
565 		*value = metrics->CurrClock[PPCLK_SOCCLK];
566 		break;
567 	case METRICS_CURR_UCLK:
568 		*value = metrics->CurrClock[PPCLK_UCLK];
569 		break;
570 	case METRICS_CURR_VCLK:
571 		*value = metrics->CurrClock[PPCLK_VCLK];
572 		break;
573 	case METRICS_CURR_DCLK:
574 		*value = metrics->CurrClock[PPCLK_DCLK];
575 		break;
576 	case METRICS_CURR_FCLK:
577 		*value = metrics->CurrClock[PPCLK_FCLK];
578 		break;
579 	case METRICS_AVERAGE_GFXCLK:
580 		*value = metrics->AverageGfxclkFrequency;
581 		break;
582 	case METRICS_AVERAGE_SOCCLK:
583 		*value = metrics->AverageSocclkFrequency;
584 		break;
585 	case METRICS_AVERAGE_UCLK:
586 		*value = metrics->AverageUclkFrequency;
587 		break;
588 	case METRICS_AVERAGE_VCLK:
589 		*value = metrics->AverageVclkFrequency;
590 		break;
591 	case METRICS_AVERAGE_DCLK:
592 		*value = metrics->AverageDclkFrequency;
593 		break;
594 	case METRICS_AVERAGE_GFXACTIVITY:
595 		*value = metrics->AverageGfxActivity;
596 		break;
597 	case METRICS_AVERAGE_MEMACTIVITY:
598 		*value = metrics->AverageUclkActivity;
599 		break;
600 	case METRICS_AVERAGE_VCNACTIVITY:
601 		*value = metrics->VcnActivityPercentage;
602 		break;
603 	case METRICS_AVERAGE_SOCKETPOWER:
604 		*value = metrics->AverageSocketPower << 8;
605 		break;
606 	case METRICS_TEMPERATURE_EDGE:
607 		*value = metrics->TemperatureEdge *
608 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
609 		break;
610 	case METRICS_TEMPERATURE_HOTSPOT:
611 		*value = metrics->TemperatureHotspot *
612 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
613 		break;
614 	case METRICS_TEMPERATURE_MEM:
615 		*value = metrics->TemperatureHBM *
616 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
617 		break;
618 	case METRICS_TEMPERATURE_VRGFX:
619 		*value = metrics->TemperatureVrGfx *
620 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
621 		break;
622 	case METRICS_TEMPERATURE_VRSOC:
623 		*value = metrics->TemperatureVrSoc *
624 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
625 		break;
626 	case METRICS_TEMPERATURE_VRMEM:
627 		*value = metrics->TemperatureVrMem *
628 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
629 		break;
630 	case METRICS_THROTTLER_STATUS:
631 		*value = metrics->ThrottlerStatus;
632 		break;
633 	case METRICS_CURR_FANSPEED:
634 		*value = metrics->CurrFanSpeed;
635 		break;
636 	default:
637 		*value = UINT_MAX;
638 		break;
639 	}
640 
641 	mutex_unlock(&smu->metrics_lock);
642 
643 	return ret;
644 }
645 
646 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
647 				       enum smu_clk_type clk_type,
648 				       uint32_t *value)
649 {
650 	MetricsMember_t member_type;
651 	int clk_id = 0;
652 
653 	if (!value)
654 		return -EINVAL;
655 
656 	clk_id = smu_cmn_to_asic_specific_index(smu,
657 						CMN2ASIC_MAPPING_CLK,
658 						clk_type);
659 	if (clk_id < 0)
660 		return -EINVAL;
661 
662 	switch (clk_id) {
663 	case PPCLK_GFXCLK:
664 		/*
665 		 * CurrClock[clk_id] can provide accurate
666 		 *   output only when the dpm feature is enabled.
667 		 * We can use Average_* for dpm disabled case.
668 		 *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
669 		 */
670 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
671 			member_type = METRICS_CURR_GFXCLK;
672 		else
673 			member_type = METRICS_AVERAGE_GFXCLK;
674 		break;
675 	case PPCLK_UCLK:
676 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
677 			member_type = METRICS_CURR_UCLK;
678 		else
679 			member_type = METRICS_AVERAGE_UCLK;
680 		break;
681 	case PPCLK_SOCCLK:
682 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
683 			member_type = METRICS_CURR_SOCCLK;
684 		else
685 			member_type = METRICS_AVERAGE_SOCCLK;
686 		break;
687 	case PPCLK_VCLK:
688 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
689 			member_type = METRICS_CURR_VCLK;
690 		else
691 			member_type = METRICS_AVERAGE_VCLK;
692 		break;
693 	case PPCLK_DCLK:
694 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
695 			member_type = METRICS_CURR_DCLK;
696 		else
697 			member_type = METRICS_AVERAGE_DCLK;
698 		break;
699 	case PPCLK_FCLK:
700 		member_type = METRICS_CURR_FCLK;
701 		break;
702 	default:
703 		return -EINVAL;
704 	}
705 
706 	return arcturus_get_smu_metrics_data(smu,
707 					     member_type,
708 					     value);
709 }
710 
711 static int arcturus_print_clk_levels(struct smu_context *smu,
712 			enum smu_clk_type type, char *buf)
713 {
714 	int i, now, size = 0;
715 	int ret = 0;
716 	struct pp_clock_levels_with_latency clocks;
717 	struct smu_11_0_dpm_table *single_dpm_table;
718 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
719 	struct smu_11_0_dpm_context *dpm_context = NULL;
720 	uint32_t gen_speed, lane_width;
721 
722 	if (amdgpu_ras_intr_triggered())
723 		return snprintf(buf, PAGE_SIZE, "unavailable\n");
724 
725 	dpm_context = smu_dpm->dpm_context;
726 
727 	switch (type) {
728 	case SMU_SCLK:
729 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
730 		if (ret) {
731 			dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
732 			return ret;
733 		}
734 
735 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
736 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
737 		if (ret) {
738 			dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
739 			return ret;
740 		}
741 
742 		/*
743 		 * For DPM disabled case, there will be only one clock level.
744 		 * And it's safe to assume that is always the current clock.
745 		 */
746 		for (i = 0; i < clocks.num_levels; i++)
747 			size += sprintf(buf + size, "%d: %uMhz %s\n", i,
748 					clocks.data[i].clocks_in_khz / 1000,
749 					(clocks.num_levels == 1) ? "*" :
750 					(arcturus_freqs_in_same_level(
751 					clocks.data[i].clocks_in_khz / 1000,
752 					now) ? "*" : ""));
753 		break;
754 
755 	case SMU_MCLK:
756 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
757 		if (ret) {
758 			dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
759 			return ret;
760 		}
761 
762 		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
763 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
764 		if (ret) {
765 			dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
766 			return ret;
767 		}
768 
769 		for (i = 0; i < clocks.num_levels; i++)
770 			size += sprintf(buf + size, "%d: %uMhz %s\n",
771 				i, clocks.data[i].clocks_in_khz / 1000,
772 				(clocks.num_levels == 1) ? "*" :
773 				(arcturus_freqs_in_same_level(
774 				clocks.data[i].clocks_in_khz / 1000,
775 				now) ? "*" : ""));
776 		break;
777 
778 	case SMU_SOCCLK:
779 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
780 		if (ret) {
781 			dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
782 			return ret;
783 		}
784 
785 		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
786 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
787 		if (ret) {
788 			dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
789 			return ret;
790 		}
791 
792 		for (i = 0; i < clocks.num_levels; i++)
793 			size += sprintf(buf + size, "%d: %uMhz %s\n",
794 				i, clocks.data[i].clocks_in_khz / 1000,
795 				(clocks.num_levels == 1) ? "*" :
796 				(arcturus_freqs_in_same_level(
797 				clocks.data[i].clocks_in_khz / 1000,
798 				now) ? "*" : ""));
799 		break;
800 
801 	case SMU_FCLK:
802 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
803 		if (ret) {
804 			dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
805 			return ret;
806 		}
807 
808 		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
809 		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
810 		if (ret) {
811 			dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
812 			return ret;
813 		}
814 
815 		for (i = 0; i < single_dpm_table->count; i++)
816 			size += sprintf(buf + size, "%d: %uMhz %s\n",
817 				i, single_dpm_table->dpm_levels[i].value,
818 				(clocks.num_levels == 1) ? "*" :
819 				(arcturus_freqs_in_same_level(
820 				clocks.data[i].clocks_in_khz / 1000,
821 				now) ? "*" : ""));
822 		break;
823 
824 	case SMU_PCIE:
825 		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
826 		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
827 		size += sprintf(buf + size, "0: %s %s %dMhz *\n",
828 				(gen_speed == 0) ? "2.5GT/s," :
829 				(gen_speed == 1) ? "5.0GT/s," :
830 				(gen_speed == 2) ? "8.0GT/s," :
831 				(gen_speed == 3) ? "16.0GT/s," : "",
832 				(lane_width == 1) ? "x1" :
833 				(lane_width == 2) ? "x2" :
834 				(lane_width == 3) ? "x4" :
835 				(lane_width == 4) ? "x8" :
836 				(lane_width == 5) ? "x12" :
837 				(lane_width == 6) ? "x16" : "",
838 				smu->smu_table.boot_values.lclk / 100);
839 		break;
840 
841 	default:
842 		break;
843 	}
844 
845 	return size;
846 }
847 
848 static int arcturus_upload_dpm_level(struct smu_context *smu,
849 				     bool max,
850 				     uint32_t feature_mask,
851 				     uint32_t level)
852 {
853 	struct smu_11_0_dpm_context *dpm_context =
854 			smu->smu_dpm.dpm_context;
855 	uint32_t freq;
856 	int ret = 0;
857 
858 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
859 	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
860 		freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
861 		ret = smu_cmn_send_smc_msg_with_param(smu,
862 			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
863 			(PPCLK_GFXCLK << 16) | (freq & 0xffff),
864 			NULL);
865 		if (ret) {
866 			dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
867 						max ? "max" : "min");
868 			return ret;
869 		}
870 	}
871 
872 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
873 	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
874 		freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
875 		ret = smu_cmn_send_smc_msg_with_param(smu,
876 			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
877 			(PPCLK_UCLK << 16) | (freq & 0xffff),
878 			NULL);
879 		if (ret) {
880 			dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
881 						max ? "max" : "min");
882 			return ret;
883 		}
884 	}
885 
886 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
887 	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
888 		freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
889 		ret = smu_cmn_send_smc_msg_with_param(smu,
890 			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
891 			(PPCLK_SOCCLK << 16) | (freq & 0xffff),
892 			NULL);
893 		if (ret) {
894 			dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
895 						max ? "max" : "min");
896 			return ret;
897 		}
898 	}
899 
900 	return ret;
901 }
902 
903 static int arcturus_force_clk_levels(struct smu_context *smu,
904 			enum smu_clk_type type, uint32_t mask)
905 {
906 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
907 	struct smu_11_0_dpm_table *single_dpm_table = NULL;
908 	uint32_t soft_min_level, soft_max_level;
909 	uint32_t smu_version;
910 	int ret = 0;
911 
912 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
913 	if (ret) {
914 		dev_err(smu->adev->dev, "Failed to get smu version!\n");
915 		return ret;
916 	}
917 
918 	if ((smu_version >= 0x361200) &&
919 	    (smu_version <= 0x361a00)) {
920 		dev_err(smu->adev->dev, "Forcing clock level is not supported with "
921 		       "54.18 - 54.26(included) SMU firmwares\n");
922 		return -EOPNOTSUPP;
923 	}
924 
925 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
926 	soft_max_level = mask ? (fls(mask) - 1) : 0;
927 
928 	switch (type) {
929 	case SMU_SCLK:
930 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
931 		if (soft_max_level >= single_dpm_table->count) {
932 			dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
933 					soft_max_level, single_dpm_table->count - 1);
934 			ret = -EINVAL;
935 			break;
936 		}
937 
938 		ret = arcturus_upload_dpm_level(smu,
939 						false,
940 						FEATURE_DPM_GFXCLK_MASK,
941 						soft_min_level);
942 		if (ret) {
943 			dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
944 			break;
945 		}
946 
947 		ret = arcturus_upload_dpm_level(smu,
948 						true,
949 						FEATURE_DPM_GFXCLK_MASK,
950 						soft_max_level);
951 		if (ret)
952 			dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
953 
954 		break;
955 
956 	case SMU_MCLK:
957 	case SMU_SOCCLK:
958 	case SMU_FCLK:
959 		/*
960 		 * Should not arrive here since Arcturus does not
961 		 * support mclk/socclk/fclk softmin/softmax settings
962 		 */
963 		ret = -EINVAL;
964 		break;
965 
966 	default:
967 		break;
968 	}
969 
970 	return ret;
971 }
972 
973 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
974 						struct smu_temperature_range *range)
975 {
976 	struct smu_table_context *table_context = &smu->smu_table;
977 	struct smu_11_0_powerplay_table *powerplay_table =
978 				table_context->power_play_table;
979 	PPTable_t *pptable = smu->smu_table.driver_pptable;
980 
981 	if (!range)
982 		return -EINVAL;
983 
984 	memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
985 
986 	range->max = pptable->TedgeLimit *
987 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
988 	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
989 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
990 	range->hotspot_crit_max = pptable->ThotspotLimit *
991 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
992 	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
993 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
994 	range->mem_crit_max = pptable->TmemLimit *
995 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
996 	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
997 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
998 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
999 
1000 	return 0;
1001 }
1002 
1003 static int arcturus_read_sensor(struct smu_context *smu,
1004 				enum amd_pp_sensors sensor,
1005 				void *data, uint32_t *size)
1006 {
1007 	struct smu_table_context *table_context = &smu->smu_table;
1008 	PPTable_t *pptable = table_context->driver_pptable;
1009 	int ret = 0;
1010 
1011 	if (amdgpu_ras_intr_triggered())
1012 		return 0;
1013 
1014 	if (!data || !size)
1015 		return -EINVAL;
1016 
1017 	mutex_lock(&smu->sensor_lock);
1018 	switch (sensor) {
1019 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1020 		*(uint32_t *)data = pptable->FanMaximumRpm;
1021 		*size = 4;
1022 		break;
1023 	case AMDGPU_PP_SENSOR_MEM_LOAD:
1024 		ret = arcturus_get_smu_metrics_data(smu,
1025 						    METRICS_AVERAGE_MEMACTIVITY,
1026 						    (uint32_t *)data);
1027 		*size = 4;
1028 		break;
1029 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1030 		ret = arcturus_get_smu_metrics_data(smu,
1031 						    METRICS_AVERAGE_GFXACTIVITY,
1032 						    (uint32_t *)data);
1033 		*size = 4;
1034 		break;
1035 	case AMDGPU_PP_SENSOR_GPU_POWER:
1036 		ret = arcturus_get_smu_metrics_data(smu,
1037 						    METRICS_AVERAGE_SOCKETPOWER,
1038 						    (uint32_t *)data);
1039 		*size = 4;
1040 		break;
1041 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1042 		ret = arcturus_get_smu_metrics_data(smu,
1043 						    METRICS_TEMPERATURE_HOTSPOT,
1044 						    (uint32_t *)data);
1045 		*size = 4;
1046 		break;
1047 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
1048 		ret = arcturus_get_smu_metrics_data(smu,
1049 						    METRICS_TEMPERATURE_EDGE,
1050 						    (uint32_t *)data);
1051 		*size = 4;
1052 		break;
1053 	case AMDGPU_PP_SENSOR_MEM_TEMP:
1054 		ret = arcturus_get_smu_metrics_data(smu,
1055 						    METRICS_TEMPERATURE_MEM,
1056 						    (uint32_t *)data);
1057 		*size = 4;
1058 		break;
1059 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1060 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1061 		/* the output clock frequency in 10K unit */
1062 		*(uint32_t *)data *= 100;
1063 		*size = 4;
1064 		break;
1065 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1066 		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1067 		*(uint32_t *)data *= 100;
1068 		*size = 4;
1069 		break;
1070 	case AMDGPU_PP_SENSOR_VDDGFX:
1071 		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1072 		*size = 4;
1073 		break;
1074 	default:
1075 		ret = -EOPNOTSUPP;
1076 		break;
1077 	}
1078 	mutex_unlock(&smu->sensor_lock);
1079 
1080 	return ret;
1081 }
1082 
1083 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1084 					  uint32_t *speed)
1085 {
1086 	int ret;
1087 	u32 rpm;
1088 
1089 	if (!speed)
1090 		return -EINVAL;
1091 
1092 	switch (smu_v11_0_get_fan_control_mode(smu)) {
1093 	case AMD_FAN_CTRL_AUTO:
1094 		ret = arcturus_get_smu_metrics_data(smu,
1095 						    METRICS_CURR_FANSPEED,
1096 						    &rpm);
1097 		if (!ret && smu->fan_max_rpm)
1098 			*speed = rpm * 100 / smu->fan_max_rpm;
1099 		return ret;
1100 	default:
1101 		*speed = smu->user_dpm_profile.fan_speed_percent;
1102 		return 0;
1103 	}
1104 }
1105 
1106 static int arcturus_get_fan_parameters(struct smu_context *smu)
1107 {
1108 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1109 
1110 	smu->fan_max_rpm = pptable->FanMaximumRpm;
1111 
1112 	return 0;
1113 }
1114 
1115 static int arcturus_get_power_limit(struct smu_context *smu)
1116 {
1117 	struct smu_11_0_powerplay_table *powerplay_table =
1118 		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1119 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1120 	uint32_t power_limit, od_percent;
1121 
1122 	if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1123 		/* the last hope to figure out the ppt limit */
1124 		if (!pptable) {
1125 			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1126 			return -EINVAL;
1127 		}
1128 		power_limit =
1129 			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1130 	}
1131 	smu->current_power_limit = power_limit;
1132 
1133 	if (smu->od_enabled) {
1134 		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1135 
1136 		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1137 
1138 		power_limit *= (100 + od_percent);
1139 		power_limit /= 100;
1140 	}
1141 	smu->max_power_limit = power_limit;
1142 
1143 	return 0;
1144 }
1145 
1146 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1147 					   char *buf)
1148 {
1149 	DpmActivityMonitorCoeffInt_t activity_monitor;
1150 	static const char *profile_name[] = {
1151 					"BOOTUP_DEFAULT",
1152 					"3D_FULL_SCREEN",
1153 					"POWER_SAVING",
1154 					"VIDEO",
1155 					"VR",
1156 					"COMPUTE",
1157 					"CUSTOM"};
1158 	static const char *title[] = {
1159 			"PROFILE_INDEX(NAME)",
1160 			"CLOCK_TYPE(NAME)",
1161 			"FPS",
1162 			"UseRlcBusy",
1163 			"MinActiveFreqType",
1164 			"MinActiveFreq",
1165 			"BoosterFreqType",
1166 			"BoosterFreq",
1167 			"PD_Data_limit_c",
1168 			"PD_Data_error_coeff",
1169 			"PD_Data_error_rate_coeff"};
1170 	uint32_t i, size = 0;
1171 	int16_t workload_type = 0;
1172 	int result = 0;
1173 	uint32_t smu_version;
1174 
1175 	if (!buf)
1176 		return -EINVAL;
1177 
1178 	result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1179 	if (result)
1180 		return result;
1181 
1182 	if (smu_version >= 0x360d00)
1183 		size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1184 			title[0], title[1], title[2], title[3], title[4], title[5],
1185 			title[6], title[7], title[8], title[9], title[10]);
1186 	else
1187 		size += sprintf(buf + size, "%16s\n",
1188 			title[0]);
1189 
1190 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1191 		/*
1192 		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1193 		 * Not all profile modes are supported on arcturus.
1194 		 */
1195 		workload_type = smu_cmn_to_asic_specific_index(smu,
1196 							       CMN2ASIC_MAPPING_WORKLOAD,
1197 							       i);
1198 		if (workload_type < 0)
1199 			continue;
1200 
1201 		if (smu_version >= 0x360d00) {
1202 			result = smu_cmn_update_table(smu,
1203 						  SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1204 						  workload_type,
1205 						  (void *)(&activity_monitor),
1206 						  false);
1207 			if (result) {
1208 				dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1209 				return result;
1210 			}
1211 		}
1212 
1213 		size += sprintf(buf + size, "%2d %14s%s\n",
1214 			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1215 
1216 		if (smu_version >= 0x360d00) {
1217 			size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1218 				" ",
1219 				0,
1220 				"GFXCLK",
1221 				activity_monitor.Gfx_FPS,
1222 				activity_monitor.Gfx_UseRlcBusy,
1223 				activity_monitor.Gfx_MinActiveFreqType,
1224 				activity_monitor.Gfx_MinActiveFreq,
1225 				activity_monitor.Gfx_BoosterFreqType,
1226 				activity_monitor.Gfx_BoosterFreq,
1227 				activity_monitor.Gfx_PD_Data_limit_c,
1228 				activity_monitor.Gfx_PD_Data_error_coeff,
1229 				activity_monitor.Gfx_PD_Data_error_rate_coeff);
1230 
1231 			size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1232 				" ",
1233 				1,
1234 				"UCLK",
1235 				activity_monitor.Mem_FPS,
1236 				activity_monitor.Mem_UseRlcBusy,
1237 				activity_monitor.Mem_MinActiveFreqType,
1238 				activity_monitor.Mem_MinActiveFreq,
1239 				activity_monitor.Mem_BoosterFreqType,
1240 				activity_monitor.Mem_BoosterFreq,
1241 				activity_monitor.Mem_PD_Data_limit_c,
1242 				activity_monitor.Mem_PD_Data_error_coeff,
1243 				activity_monitor.Mem_PD_Data_error_rate_coeff);
1244 		}
1245 	}
1246 
1247 	return size;
1248 }
1249 
1250 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1251 					   long *input,
1252 					   uint32_t size)
1253 {
1254 	DpmActivityMonitorCoeffInt_t activity_monitor;
1255 	int workload_type = 0;
1256 	uint32_t profile_mode = input[size];
1257 	int ret = 0;
1258 	uint32_t smu_version;
1259 
1260 	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1261 		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1262 		return -EINVAL;
1263 	}
1264 
1265 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1266 	if (ret)
1267 		return ret;
1268 
1269 	if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1270 	     (smu_version >=0x360d00)) {
1271 		ret = smu_cmn_update_table(smu,
1272 				       SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1273 				       WORKLOAD_PPLIB_CUSTOM_BIT,
1274 				       (void *)(&activity_monitor),
1275 				       false);
1276 		if (ret) {
1277 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1278 			return ret;
1279 		}
1280 
1281 		switch (input[0]) {
1282 		case 0: /* Gfxclk */
1283 			activity_monitor.Gfx_FPS = input[1];
1284 			activity_monitor.Gfx_UseRlcBusy = input[2];
1285 			activity_monitor.Gfx_MinActiveFreqType = input[3];
1286 			activity_monitor.Gfx_MinActiveFreq = input[4];
1287 			activity_monitor.Gfx_BoosterFreqType = input[5];
1288 			activity_monitor.Gfx_BoosterFreq = input[6];
1289 			activity_monitor.Gfx_PD_Data_limit_c = input[7];
1290 			activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1291 			activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1292 			break;
1293 		case 1: /* Uclk */
1294 			activity_monitor.Mem_FPS = input[1];
1295 			activity_monitor.Mem_UseRlcBusy = input[2];
1296 			activity_monitor.Mem_MinActiveFreqType = input[3];
1297 			activity_monitor.Mem_MinActiveFreq = input[4];
1298 			activity_monitor.Mem_BoosterFreqType = input[5];
1299 			activity_monitor.Mem_BoosterFreq = input[6];
1300 			activity_monitor.Mem_PD_Data_limit_c = input[7];
1301 			activity_monitor.Mem_PD_Data_error_coeff = input[8];
1302 			activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1303 			break;
1304 		}
1305 
1306 		ret = smu_cmn_update_table(smu,
1307 				       SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1308 				       WORKLOAD_PPLIB_CUSTOM_BIT,
1309 				       (void *)(&activity_monitor),
1310 				       true);
1311 		if (ret) {
1312 			dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1313 			return ret;
1314 		}
1315 	}
1316 
1317 	/*
1318 	 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1319 	 * Not all profile modes are supported on arcturus.
1320 	 */
1321 	workload_type = smu_cmn_to_asic_specific_index(smu,
1322 						       CMN2ASIC_MAPPING_WORKLOAD,
1323 						       profile_mode);
1324 	if (workload_type < 0) {
1325 		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1326 		return -EINVAL;
1327 	}
1328 
1329 	ret = smu_cmn_send_smc_msg_with_param(smu,
1330 					  SMU_MSG_SetWorkloadMask,
1331 					  1 << workload_type,
1332 					  NULL);
1333 	if (ret) {
1334 		dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1335 		return ret;
1336 	}
1337 
1338 	smu->power_profile_mode = profile_mode;
1339 
1340 	return 0;
1341 }
1342 
1343 static int arcturus_set_performance_level(struct smu_context *smu,
1344 					  enum amd_dpm_forced_level level)
1345 {
1346 	uint32_t smu_version;
1347 	int ret;
1348 
1349 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1350 	if (ret) {
1351 		dev_err(smu->adev->dev, "Failed to get smu version!\n");
1352 		return ret;
1353 	}
1354 
1355 	switch (level) {
1356 	case AMD_DPM_FORCED_LEVEL_HIGH:
1357 	case AMD_DPM_FORCED_LEVEL_LOW:
1358 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1359 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1360 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1361 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1362 		if ((smu_version >= 0x361200) &&
1363 		    (smu_version <= 0x361a00)) {
1364 			dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1365 			       "54.18 - 54.26(included) SMU firmwares\n");
1366 			return -EOPNOTSUPP;
1367 		}
1368 		break;
1369 	default:
1370 		break;
1371 	}
1372 
1373 	return smu_v11_0_set_performance_level(smu, level);
1374 }
1375 
1376 static void arcturus_dump_pptable(struct smu_context *smu)
1377 {
1378 	struct smu_table_context *table_context = &smu->smu_table;
1379 	PPTable_t *pptable = table_context->driver_pptable;
1380 	int i;
1381 
1382 	dev_info(smu->adev->dev, "Dumped PPTable:\n");
1383 
1384 	dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1385 
1386 	dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1387 	dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1388 
1389 	for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1390 		dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1391 		dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1392 	}
1393 
1394 	dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1395 	dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1396 	dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1397 	dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1398 
1399 	dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1400 	dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1401 	dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1402 	dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1403 	dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1404 	dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1405 	dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1406 
1407 	dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1408 	dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1409 
1410 	dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1411 
1412 	dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1413 	dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1414 
1415 	dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1416 	dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1417 	dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1418 	dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1419 
1420 	dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1421 	dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1422 	dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1423 	dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1424 
1425 	dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1426 	dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1427 
1428 	dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1429 			"  .VoltageMode          = 0x%02x\n"
1430 			"  .SnapToDiscrete       = 0x%02x\n"
1431 			"  .NumDiscreteLevels    = 0x%02x\n"
1432 			"  .padding              = 0x%02x\n"
1433 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1434 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1435 			"  .SsFmin               = 0x%04x\n"
1436 			"  .Padding_16           = 0x%04x\n",
1437 			pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1438 			pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1439 			pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1440 			pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1441 			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1442 			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1443 			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1444 			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1445 			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1446 			pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1447 			pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1448 
1449 	dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1450 			"  .VoltageMode          = 0x%02x\n"
1451 			"  .SnapToDiscrete       = 0x%02x\n"
1452 			"  .NumDiscreteLevels    = 0x%02x\n"
1453 			"  .padding              = 0x%02x\n"
1454 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1455 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1456 			"  .SsFmin               = 0x%04x\n"
1457 			"  .Padding_16           = 0x%04x\n",
1458 			pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1459 			pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1460 			pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1461 			pptable->DpmDescriptor[PPCLK_VCLK].padding,
1462 			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1463 			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1464 			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1465 			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1466 			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1467 			pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1468 			pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1469 
1470 	dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1471 			"  .VoltageMode          = 0x%02x\n"
1472 			"  .SnapToDiscrete       = 0x%02x\n"
1473 			"  .NumDiscreteLevels    = 0x%02x\n"
1474 			"  .padding              = 0x%02x\n"
1475 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1476 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1477 			"  .SsFmin               = 0x%04x\n"
1478 			"  .Padding_16           = 0x%04x\n",
1479 			pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1480 			pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1481 			pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1482 			pptable->DpmDescriptor[PPCLK_DCLK].padding,
1483 			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1484 			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1485 			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1486 			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1487 			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1488 			pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1489 			pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1490 
1491 	dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1492 			"  .VoltageMode          = 0x%02x\n"
1493 			"  .SnapToDiscrete       = 0x%02x\n"
1494 			"  .NumDiscreteLevels    = 0x%02x\n"
1495 			"  .padding              = 0x%02x\n"
1496 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1497 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1498 			"  .SsFmin               = 0x%04x\n"
1499 			"  .Padding_16           = 0x%04x\n",
1500 			pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1501 			pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1502 			pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1503 			pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1504 			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1505 			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1506 			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1507 			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1508 			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1509 			pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1510 			pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1511 
1512 	dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1513 			"  .VoltageMode          = 0x%02x\n"
1514 			"  .SnapToDiscrete       = 0x%02x\n"
1515 			"  .NumDiscreteLevels    = 0x%02x\n"
1516 			"  .padding              = 0x%02x\n"
1517 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1518 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1519 			"  .SsFmin               = 0x%04x\n"
1520 			"  .Padding_16           = 0x%04x\n",
1521 			pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1522 			pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1523 			pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1524 			pptable->DpmDescriptor[PPCLK_UCLK].padding,
1525 			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1526 			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1527 			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1528 			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1529 			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1530 			pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1531 			pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1532 
1533 	dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1534 			"  .VoltageMode          = 0x%02x\n"
1535 			"  .SnapToDiscrete       = 0x%02x\n"
1536 			"  .NumDiscreteLevels    = 0x%02x\n"
1537 			"  .padding              = 0x%02x\n"
1538 			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1539 			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1540 			"  .SsFmin               = 0x%04x\n"
1541 			"  .Padding_16           = 0x%04x\n",
1542 			pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1543 			pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1544 			pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1545 			pptable->DpmDescriptor[PPCLK_FCLK].padding,
1546 			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1547 			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1548 			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1549 			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1550 			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1551 			pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1552 			pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1553 
1554 
1555 	dev_info(smu->adev->dev, "FreqTableGfx\n");
1556 	for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1557 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1558 
1559 	dev_info(smu->adev->dev, "FreqTableVclk\n");
1560 	for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1561 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1562 
1563 	dev_info(smu->adev->dev, "FreqTableDclk\n");
1564 	for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1565 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1566 
1567 	dev_info(smu->adev->dev, "FreqTableSocclk\n");
1568 	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1569 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1570 
1571 	dev_info(smu->adev->dev, "FreqTableUclk\n");
1572 	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1573 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1574 
1575 	dev_info(smu->adev->dev, "FreqTableFclk\n");
1576 	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1577 		dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1578 
1579 	dev_info(smu->adev->dev, "Mp0clkFreq\n");
1580 	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1581 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1582 
1583 	dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1584 	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1585 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1586 
1587 	dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1588 	dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1589 	dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1590 	dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1591 	dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1592 	dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1593 	dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1594 	dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1595 	dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1596 
1597 	dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1598 	dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1599 	dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1600 	dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1601 
1602 	dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1603 	dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1604 
1605 	dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1606 	dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1607 	dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1608 	dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1609 	dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1610 	dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1611 
1612 	dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1613 	dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1614 	dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1615 	dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1616 	dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1617 	dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1618 	dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1619 	dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1620 	dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1621 
1622 	dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1623 	dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1624 	dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1625 	dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1626 
1627 	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1628 	dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1629 	dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1630 	dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1631 
1632 	dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1633 			pptable->dBtcGbGfxPll.a,
1634 			pptable->dBtcGbGfxPll.b,
1635 			pptable->dBtcGbGfxPll.c);
1636 	dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1637 			pptable->dBtcGbGfxAfll.a,
1638 			pptable->dBtcGbGfxAfll.b,
1639 			pptable->dBtcGbGfxAfll.c);
1640 	dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1641 			pptable->dBtcGbSoc.a,
1642 			pptable->dBtcGbSoc.b,
1643 			pptable->dBtcGbSoc.c);
1644 
1645 	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1646 			pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1647 			pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1648 	dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1649 			pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1650 			pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1651 
1652 	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1653 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1654 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1655 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1656 	dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1657 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1658 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1659 			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1660 
1661 	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1662 	dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1663 
1664 	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1665 	dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1666 	dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1667 	dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1668 
1669 	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1670 	dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1671 	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1672 	dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1673 
1674 	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1675 	dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1676 
1677 	dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1678 	for (i = 0; i < NUM_XGMI_LEVELS; i++)
1679 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1680 	dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1681 	dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1682 
1683 	dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1684 	dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1685 	dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1686 	dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1687 	dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1688 	dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1689 	dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1690 	dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1691 
1692 	dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1693 	dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1694 			pptable->ReservedEquation0.a,
1695 			pptable->ReservedEquation0.b,
1696 			pptable->ReservedEquation0.c);
1697 	dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1698 			pptable->ReservedEquation1.a,
1699 			pptable->ReservedEquation1.b,
1700 			pptable->ReservedEquation1.c);
1701 	dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1702 			pptable->ReservedEquation2.a,
1703 			pptable->ReservedEquation2.b,
1704 			pptable->ReservedEquation2.c);
1705 	dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1706 			pptable->ReservedEquation3.a,
1707 			pptable->ReservedEquation3.b,
1708 			pptable->ReservedEquation3.c);
1709 
1710 	dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1711 	dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1712 
1713 	dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1714 	dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1715 	dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1716 
1717 	dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1718 	dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1719 
1720 	dev_info(smu->adev->dev, "Board Parameters:\n");
1721 	dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1722 	dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1723 
1724 	dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1725 	dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1726 	dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1727 	dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1728 
1729 	dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1730 	dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1731 
1732 	dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1733 	dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1734 	dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1735 
1736 	dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1737 	dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1738 	dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1739 
1740 	dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1741 	dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1742 	dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1743 
1744 	dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1745 	dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1746 	dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1747 
1748 	dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1749 	dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1750 	dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1751 	dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1752 
1753 	dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1754 	dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1755 	dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1756 
1757 	dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1758 	dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1759 	dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1760 
1761 	dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1762 	dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1763 	dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1764 
1765 	dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1766 	dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1767 	dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1768 
1769 	for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1770 		dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1771 		dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1772 				pptable->I2cControllers[i].Enabled);
1773 		dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1774 				pptable->I2cControllers[i].SlaveAddress);
1775 		dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1776 				pptable->I2cControllers[i].ControllerPort);
1777 		dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1778 				pptable->I2cControllers[i].ControllerName);
1779 		dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1780 				pptable->I2cControllers[i].ThermalThrotter);
1781 		dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1782 				pptable->I2cControllers[i].I2cProtocol);
1783 		dev_info(smu->adev->dev, "                   .Speed = %d\n",
1784 				pptable->I2cControllers[i].Speed);
1785 	}
1786 
1787 	dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1788 	dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1789 
1790 	dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1791 
1792 	dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1793 	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1794 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1795 	dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1796 	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1797 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1798 	dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1799 	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1800 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1801 	dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1802 	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1803 		dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1804 
1805 }
1806 
1807 static bool arcturus_is_dpm_running(struct smu_context *smu)
1808 {
1809 	int ret = 0;
1810 	uint32_t feature_mask[2];
1811 	uint64_t feature_enabled;
1812 
1813 	ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1814 	if (ret)
1815 		return false;
1816 
1817 	feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1818 
1819 	return !!(feature_enabled & SMC_DPM_FEATURE);
1820 }
1821 
1822 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1823 {
1824 	int ret = 0;
1825 
1826 	if (enable) {
1827 		if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1828 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1829 			if (ret) {
1830 				dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1831 				return ret;
1832 			}
1833 		}
1834 	} else {
1835 		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1836 			ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1837 			if (ret) {
1838 				dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1839 				return ret;
1840 			}
1841 		}
1842 	}
1843 
1844 	return ret;
1845 }
1846 
1847 static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1848 				  uint8_t address, uint32_t numbytes,
1849 				  uint8_t *data)
1850 {
1851 	int i;
1852 
1853 	req->I2CcontrollerPort = 0;
1854 	req->I2CSpeed = 2;
1855 	req->SlaveAddress = address;
1856 	req->NumCmds = numbytes;
1857 
1858 	for (i = 0; i < numbytes; i++) {
1859 		SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1860 
1861 		/* First 2 bytes are always write for lower 2b EEPROM address */
1862 		if (i < 2)
1863 			cmd->Cmd = 1;
1864 		else
1865 			cmd->Cmd = write;
1866 
1867 
1868 		/* Add RESTART for read  after address filled */
1869 		cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1870 
1871 		/* Add STOP in the end */
1872 		cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1873 
1874 		/* Fill with data regardless if read or write to simplify code */
1875 		cmd->RegisterAddr = data[i];
1876 	}
1877 }
1878 
1879 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1880 					       uint8_t address,
1881 					       uint8_t *data,
1882 					       uint32_t numbytes)
1883 {
1884 	uint32_t  i, ret = 0;
1885 	SwI2cRequest_t req;
1886 	struct amdgpu_device *adev = to_amdgpu_device(control);
1887 	struct smu_table_context *smu_table = &adev->smu.smu_table;
1888 	struct smu_table *table = &smu_table->driver_table;
1889 
1890 	if (numbytes > MAX_SW_I2C_COMMANDS) {
1891 		dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1892 			numbytes, MAX_SW_I2C_COMMANDS);
1893 		return -EINVAL;
1894 	}
1895 
1896 	memset(&req, 0, sizeof(req));
1897 	arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1898 
1899 	mutex_lock(&adev->smu.mutex);
1900 	/* Now read data starting with that address */
1901 	ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1902 					true);
1903 	mutex_unlock(&adev->smu.mutex);
1904 
1905 	if (!ret) {
1906 		SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1907 
1908 		/* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1909 		for (i = 0; i < numbytes; i++)
1910 			data[i] = res->SwI2cCmds[i].Data;
1911 
1912 		dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
1913 				  (uint16_t)address, numbytes);
1914 
1915 		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1916 			       8, 1, data, numbytes, false);
1917 	} else
1918 		dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
1919 
1920 	return ret;
1921 }
1922 
1923 static int arcturus_i2c_write_data(struct i2c_adapter *control,
1924 						uint8_t address,
1925 						uint8_t *data,
1926 						uint32_t numbytes)
1927 {
1928 	uint32_t ret;
1929 	SwI2cRequest_t req;
1930 	struct amdgpu_device *adev = to_amdgpu_device(control);
1931 
1932 	if (numbytes > MAX_SW_I2C_COMMANDS) {
1933 		dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1934 			numbytes, MAX_SW_I2C_COMMANDS);
1935 		return -EINVAL;
1936 	}
1937 
1938 	memset(&req, 0, sizeof(req));
1939 	arcturus_fill_i2c_req(&req, true, address, numbytes, data);
1940 
1941 	mutex_lock(&adev->smu.mutex);
1942 	ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1943 	mutex_unlock(&adev->smu.mutex);
1944 
1945 	if (!ret) {
1946 		dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
1947 					 (uint16_t)address, numbytes);
1948 
1949 		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1950 			       8, 1, data, numbytes, false);
1951 		/*
1952 		 * According to EEPROM spec there is a MAX of 10 ms required for
1953 		 * EEPROM to flush internal RX buffer after STOP was issued at the
1954 		 * end of write transaction. During this time the EEPROM will not be
1955 		 * responsive to any more commands - so wait a bit more.
1956 		 */
1957 		msleep(10);
1958 
1959 	} else
1960 		dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
1961 
1962 	return ret;
1963 }
1964 
1965 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1966 			      struct i2c_msg *msgs, int num)
1967 {
1968 	uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1969 	uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1970 
1971 	for (i = 0; i < num; i++) {
1972 		/*
1973 		 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1974 		 * once and hence the data needs to be spliced into chunks and sent each
1975 		 * chunk separately
1976 		 */
1977 		data_size = msgs[i].len - 2;
1978 		data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1979 		next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1980 		data_ptr = msgs[i].buf + 2;
1981 
1982 		for (j = 0; j < data_size / data_chunk_size; j++) {
1983 			/* Insert the EEPROM dest addess, bits 0-15 */
1984 			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1985 			data_chunk[1] = (next_eeprom_addr & 0xff);
1986 
1987 			if (msgs[i].flags & I2C_M_RD) {
1988 				ret = arcturus_i2c_read_data(i2c_adap,
1989 							     (uint8_t)msgs[i].addr,
1990 							     data_chunk, MAX_SW_I2C_COMMANDS);
1991 
1992 				memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1993 			} else {
1994 
1995 				memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1996 
1997 				ret = arcturus_i2c_write_data(i2c_adap,
1998 							      (uint8_t)msgs[i].addr,
1999 							      data_chunk, MAX_SW_I2C_COMMANDS);
2000 			}
2001 
2002 			if (ret) {
2003 				num = -EIO;
2004 				goto fail;
2005 			}
2006 
2007 			next_eeprom_addr += data_chunk_size;
2008 			data_ptr += data_chunk_size;
2009 		}
2010 
2011 		if (data_size % data_chunk_size) {
2012 			data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2013 			data_chunk[1] = (next_eeprom_addr & 0xff);
2014 
2015 			if (msgs[i].flags & I2C_M_RD) {
2016 				ret = arcturus_i2c_read_data(i2c_adap,
2017 							     (uint8_t)msgs[i].addr,
2018 							     data_chunk, (data_size % data_chunk_size) + 2);
2019 
2020 				memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2021 			} else {
2022 				memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2023 
2024 				ret = arcturus_i2c_write_data(i2c_adap,
2025 							      (uint8_t)msgs[i].addr,
2026 							      data_chunk, (data_size % data_chunk_size) + 2);
2027 			}
2028 
2029 			if (ret) {
2030 				num = -EIO;
2031 				goto fail;
2032 			}
2033 		}
2034 	}
2035 
2036 fail:
2037 	return num;
2038 }
2039 
2040 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2041 {
2042 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2043 }
2044 
2045 
2046 static const struct i2c_algorithm arcturus_i2c_algo = {
2047 	.master_xfer = arcturus_i2c_xfer,
2048 	.functionality = arcturus_i2c_func,
2049 };
2050 
2051 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2052 {
2053 	struct amdgpu_device *adev = to_amdgpu_device(control);
2054 	int res;
2055 
2056 	control->owner = THIS_MODULE;
2057 	control->class = I2C_CLASS_SPD;
2058 	control->dev.parent = &adev->pdev->dev;
2059 	control->algo = &arcturus_i2c_algo;
2060 	snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2061 
2062 	res = i2c_add_adapter(control);
2063 	if (res)
2064 		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2065 
2066 	return res;
2067 }
2068 
2069 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2070 {
2071 	i2c_del_adapter(control);
2072 }
2073 
2074 static void arcturus_get_unique_id(struct smu_context *smu)
2075 {
2076 	struct amdgpu_device *adev = smu->adev;
2077 	uint32_t top32 = 0, bottom32 = 0, smu_version;
2078 	uint64_t id;
2079 
2080 	if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2081 		dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2082 		return;
2083 	}
2084 
2085 	/* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2086 	if (smu_version < 0x361700) {
2087 		dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2088 		return;
2089 	}
2090 
2091 	/* Get the SN to turn into a Unique ID */
2092 	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2093 	smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2094 
2095 	id = ((uint64_t)bottom32 << 32) | top32;
2096 	adev->unique_id = id;
2097 	/* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2098 	 * 16-digit HEX string for convenience and backwards-compatibility
2099 	 */
2100 	sprintf(adev->serial, "%llx", id);
2101 }
2102 
2103 static bool arcturus_is_baco_supported(struct smu_context *smu)
2104 {
2105 	struct amdgpu_device *adev = smu->adev;
2106 	uint32_t val;
2107 
2108 	if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
2109 		return false;
2110 
2111 	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2112 	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2113 }
2114 
2115 static int arcturus_set_df_cstate(struct smu_context *smu,
2116 				  enum pp_df_cstate state)
2117 {
2118 	uint32_t smu_version;
2119 	int ret;
2120 
2121 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2122 	if (ret) {
2123 		dev_err(smu->adev->dev, "Failed to get smu version!\n");
2124 		return ret;
2125 	}
2126 
2127 	/* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2128 	if (smu_version < 0x360F00) {
2129 		dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2130 		return -EINVAL;
2131 	}
2132 
2133 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2134 }
2135 
2136 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2137 {
2138 	uint32_t smu_version;
2139 	int ret;
2140 
2141 	ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2142 	if (ret) {
2143 		dev_err(smu->adev->dev, "Failed to get smu version!\n");
2144 		return ret;
2145 	}
2146 
2147 	/* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2148 	if (smu_version < 0x00361700) {
2149 		dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2150 		return -EINVAL;
2151 	}
2152 
2153 	if (en)
2154 		return smu_cmn_send_smc_msg_with_param(smu,
2155 						   SMU_MSG_GmiPwrDnControl,
2156 						   1,
2157 						   NULL);
2158 
2159 	return smu_cmn_send_smc_msg_with_param(smu,
2160 					   SMU_MSG_GmiPwrDnControl,
2161 					   0,
2162 					   NULL);
2163 }
2164 
2165 static const struct throttling_logging_label {
2166 	uint32_t feature_mask;
2167 	const char *label;
2168 } logging_label[] = {
2169 	{(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2170 	{(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2171 	{(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2172 	{(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2173 	{(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2174 	{(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2175 	{(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2176 };
2177 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2178 {
2179 	int ret;
2180 	int throttler_idx, throtting_events = 0, buf_idx = 0;
2181 	struct amdgpu_device *adev = smu->adev;
2182 	uint32_t throttler_status;
2183 	char log_buf[256];
2184 
2185 	ret = arcturus_get_smu_metrics_data(smu,
2186 					    METRICS_THROTTLER_STATUS,
2187 					    &throttler_status);
2188 	if (ret)
2189 		return;
2190 
2191 	memset(log_buf, 0, sizeof(log_buf));
2192 	for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2193 	     throttler_idx++) {
2194 		if (throttler_status & logging_label[throttler_idx].feature_mask) {
2195 			throtting_events++;
2196 			buf_idx += snprintf(log_buf + buf_idx,
2197 					    sizeof(log_buf) - buf_idx,
2198 					    "%s%s",
2199 					    throtting_events > 1 ? " and " : "",
2200 					    logging_label[throttler_idx].label);
2201 			if (buf_idx >= sizeof(log_buf)) {
2202 				dev_err(adev->dev, "buffer overflow!\n");
2203 				log_buf[sizeof(log_buf) - 1] = '\0';
2204 				break;
2205 			}
2206 		}
2207 	}
2208 
2209 	dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2210 			log_buf);
2211 	kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2212 }
2213 
2214 static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2215 {
2216 	struct amdgpu_device *adev = smu->adev;
2217 	uint32_t esm_ctrl;
2218 
2219 	/* TODO: confirm this on real target */
2220 	esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2221 	if ((esm_ctrl >> 15) & 0x1FFFF)
2222 		return (((esm_ctrl >> 8) & 0x3F) + 128);
2223 
2224 	return smu_v11_0_get_current_pcie_link_speed(smu);
2225 }
2226 
2227 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2228 					void **table)
2229 {
2230 	struct smu_table_context *smu_table = &smu->smu_table;
2231 	struct gpu_metrics_v1_0 *gpu_metrics =
2232 		(struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2233 	SmuMetrics_t metrics;
2234 	int ret = 0;
2235 
2236 	ret = smu_cmn_get_metrics_table(smu,
2237 					&metrics,
2238 					true);
2239 	if (ret)
2240 		return ret;
2241 
2242 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 0);
2243 
2244 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2245 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2246 	gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2247 	gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2248 	gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2249 	gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2250 
2251 	gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2252 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2253 	gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2254 
2255 	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2256 	gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2257 
2258 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2259 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2260 	gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2261 	gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2262 	gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2263 
2264 	gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2265 	gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2266 	gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2267 	gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2268 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2269 
2270 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2271 
2272 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2273 
2274 	gpu_metrics->pcie_link_width =
2275 			smu_v11_0_get_current_pcie_link_width(smu);
2276 	gpu_metrics->pcie_link_speed =
2277 			arcturus_get_current_pcie_link_speed(smu);
2278 
2279 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2280 
2281 	*table = (void *)gpu_metrics;
2282 
2283 	return sizeof(struct gpu_metrics_v1_0);
2284 }
2285 
2286 static const struct pptable_funcs arcturus_ppt_funcs = {
2287 	/* init dpm */
2288 	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2289 	/* btc */
2290 	.run_btc = arcturus_run_btc,
2291 	/* dpm/clk tables */
2292 	.set_default_dpm_table = arcturus_set_default_dpm_table,
2293 	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
2294 	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2295 	.print_clk_levels = arcturus_print_clk_levels,
2296 	.force_clk_levels = arcturus_force_clk_levels,
2297 	.read_sensor = arcturus_read_sensor,
2298 	.get_fan_speed_percent = arcturus_get_fan_speed_percent,
2299 	.get_power_profile_mode = arcturus_get_power_profile_mode,
2300 	.set_power_profile_mode = arcturus_set_power_profile_mode,
2301 	.set_performance_level = arcturus_set_performance_level,
2302 	/* debug (internal used) */
2303 	.dump_pptable = arcturus_dump_pptable,
2304 	.get_power_limit = arcturus_get_power_limit,
2305 	.is_dpm_running = arcturus_is_dpm_running,
2306 	.dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2307 	.i2c_init = arcturus_i2c_control_init,
2308 	.i2c_fini = arcturus_i2c_control_fini,
2309 	.get_unique_id = arcturus_get_unique_id,
2310 	.init_microcode = smu_v11_0_init_microcode,
2311 	.load_microcode = smu_v11_0_load_microcode,
2312 	.fini_microcode = smu_v11_0_fini_microcode,
2313 	.init_smc_tables = arcturus_init_smc_tables,
2314 	.fini_smc_tables = smu_v11_0_fini_smc_tables,
2315 	.init_power = smu_v11_0_init_power,
2316 	.fini_power = smu_v11_0_fini_power,
2317 	.check_fw_status = smu_v11_0_check_fw_status,
2318 	/* pptable related */
2319 	.setup_pptable = arcturus_setup_pptable,
2320 	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2321 	.check_fw_version = smu_v11_0_check_fw_version,
2322 	.write_pptable = smu_cmn_write_pptable,
2323 	.set_driver_table_location = smu_v11_0_set_driver_table_location,
2324 	.set_tool_table_location = smu_v11_0_set_tool_table_location,
2325 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2326 	.system_features_control = smu_v11_0_system_features_control,
2327 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2328 	.send_smc_msg = smu_cmn_send_smc_msg,
2329 	.init_display_count = NULL,
2330 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
2331 	.get_enabled_mask = smu_cmn_get_enabled_mask,
2332 	.feature_is_enabled = smu_cmn_feature_is_enabled,
2333 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2334 	.notify_display_change = NULL,
2335 	.set_power_limit = smu_v11_0_set_power_limit,
2336 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2337 	.enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2338 	.disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2339 	.set_min_dcef_deep_sleep = NULL,
2340 	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2341 	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2342 	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2343 	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2344 	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2345 	.gfx_off_control = smu_v11_0_gfx_off_control,
2346 	.register_irq_handler = smu_v11_0_register_irq_handler,
2347 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2348 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2349 	.baco_is_support= arcturus_is_baco_supported,
2350 	.baco_get_state = smu_v11_0_baco_get_state,
2351 	.baco_set_state = smu_v11_0_baco_set_state,
2352 	.baco_enter = smu_v11_0_baco_enter,
2353 	.baco_exit = smu_v11_0_baco_exit,
2354 	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2355 	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2356 	.set_df_cstate = arcturus_set_df_cstate,
2357 	.allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2358 	.log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2359 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2360 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2361 	.get_gpu_metrics = arcturus_get_gpu_metrics,
2362 	.gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2363 	.deep_sleep_control = smu_v11_0_deep_sleep_control,
2364 	.get_fan_parameters = arcturus_get_fan_parameters,
2365 	.interrupt_work = smu_v11_0_interrupt_work,
2366 };
2367 
2368 void arcturus_set_ppt_funcs(struct smu_context *smu)
2369 {
2370 	smu->ppt_funcs = &arcturus_ppt_funcs;
2371 	smu->message_map = arcturus_message_map;
2372 	smu->clock_map = arcturus_clk_map;
2373 	smu->feature_map = arcturus_feature_mask_map;
2374 	smu->table_map = arcturus_table_map;
2375 	smu->pwr_src_map = arcturus_pwr_src_map;
2376 	smu->workload_map = arcturus_workload_map;
2377 }
2378