1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_dpm.h" 29 #include "amdgpu_smu.h" 30 #include "atomfirmware.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_atombios.h" 33 #include "smu_v11_0.h" 34 #include "smu11_driver_if_arcturus.h" 35 #include "soc15_common.h" 36 #include "atom.h" 37 #include "arcturus_ppt.h" 38 #include "smu_v11_0_pptable.h" 39 #include "arcturus_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/i2c.h> 46 #include <linux/pci.h> 47 #include "amdgpu_ras.h" 48 #include "smu_cmn.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \ 61 [smu_feature] = {1, (arcturus_feature)} 62 63 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 64 #define SMU_FEATURES_LOW_SHIFT 0 65 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 66 #define SMU_FEATURES_HIGH_SHIFT 32 67 68 #define SMC_DPM_FEATURE ( \ 69 FEATURE_DPM_PREFETCHER_MASK | \ 70 FEATURE_DPM_GFXCLK_MASK | \ 71 FEATURE_DPM_UCLK_MASK | \ 72 FEATURE_DPM_SOCCLK_MASK | \ 73 FEATURE_DPM_MP0CLK_MASK | \ 74 FEATURE_DPM_FCLK_MASK | \ 75 FEATURE_DPM_XGMI_MASK) 76 77 /* possible frequency drift (1Mhz) */ 78 #define EPSILON 1 79 80 #define smnPCIE_ESM_CTRL 0x111003D0 81 82 #define mmCG_FDO_CTRL0_ARCT 0x8B 83 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0 84 85 #define mmCG_FDO_CTRL1_ARCT 0x8C 86 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0 87 88 #define mmCG_FDO_CTRL2_ARCT 0x8D 89 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0 90 91 #define mmCG_TACH_CTRL_ARCT 0x8E 92 #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0 93 94 #define mmCG_TACH_STATUS_ARCT 0x8F 95 #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0 96 97 #define mmCG_THERMAL_STATUS_ARCT 0x90 98 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0 99 100 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = { 101 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 102 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 103 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 104 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 105 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 106 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 107 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 108 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 109 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 110 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 111 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 112 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), 113 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), 114 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 115 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 116 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 117 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 118 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 119 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 120 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 121 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 122 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 123 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 124 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 125 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 126 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 127 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 128 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 129 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 130 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 131 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 132 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 133 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 134 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 135 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0), 136 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 137 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 138 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 139 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 140 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0), 141 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0), 142 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0), 143 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0), 144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 145 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 146 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 147 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0), 148 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0), 149 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 153 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 154 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 155 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0), 156 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 157 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 158 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 159 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1), 160 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1), 161 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0), 162 }; 163 164 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = { 165 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 166 CLK_MAP(SCLK, PPCLK_GFXCLK), 167 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 168 CLK_MAP(FCLK, PPCLK_FCLK), 169 CLK_MAP(UCLK, PPCLK_UCLK), 170 CLK_MAP(MCLK, PPCLK_UCLK), 171 CLK_MAP(DCLK, PPCLK_DCLK), 172 CLK_MAP(VCLK, PPCLK_VCLK), 173 }; 174 175 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = { 176 FEA_MAP(DPM_PREFETCHER), 177 FEA_MAP(DPM_GFXCLK), 178 FEA_MAP(DPM_UCLK), 179 FEA_MAP(DPM_SOCCLK), 180 FEA_MAP(DPM_FCLK), 181 FEA_MAP(DPM_MP0CLK), 182 FEA_MAP(DPM_XGMI), 183 FEA_MAP(DS_GFXCLK), 184 FEA_MAP(DS_SOCCLK), 185 FEA_MAP(DS_LCLK), 186 FEA_MAP(DS_FCLK), 187 FEA_MAP(DS_UCLK), 188 FEA_MAP(GFX_ULV), 189 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 190 FEA_MAP(RSMU_SMN_CG), 191 FEA_MAP(WAFL_CG), 192 FEA_MAP(PPT), 193 FEA_MAP(TDC), 194 FEA_MAP(APCC_PLUS), 195 FEA_MAP(VR0HOT), 196 FEA_MAP(VR1HOT), 197 FEA_MAP(FW_CTF), 198 FEA_MAP(FAN_CONTROL), 199 FEA_MAP(THERMAL), 200 FEA_MAP(OUT_OF_BAND_MONITOR), 201 FEA_MAP(TEMP_DEPENDENT_VMIN), 202 }; 203 204 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = { 205 TAB_MAP(PPTABLE), 206 TAB_MAP(AVFS), 207 TAB_MAP(AVFS_PSM_DEBUG), 208 TAB_MAP(AVFS_FUSE_OVERRIDE), 209 TAB_MAP(PMSTATUSLOG), 210 TAB_MAP(SMU_METRICS), 211 TAB_MAP(DRIVER_SMU_CONFIG), 212 TAB_MAP(OVERDRIVE), 213 TAB_MAP(I2C_COMMANDS), 214 TAB_MAP(ACTIVITY_MONITOR_COEFF), 215 }; 216 217 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 218 PWR_MAP(AC), 219 PWR_MAP(DC), 220 }; 221 222 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 223 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 224 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 228 }; 229 230 static const uint8_t arcturus_throttler_map[] = { 231 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 232 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 233 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 234 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 235 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 236 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 237 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 238 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 239 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 240 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 241 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 242 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 243 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 244 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 245 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 246 [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT), 247 [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT), 248 }; 249 250 static int arcturus_tables_init(struct smu_context *smu) 251 { 252 struct smu_table_context *smu_table = &smu->smu_table; 253 struct smu_table *tables = smu_table->tables; 254 255 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 256 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 257 258 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 259 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 260 261 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 262 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 263 264 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 265 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 266 267 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 268 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 269 AMDGPU_GEM_DOMAIN_VRAM); 270 271 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 272 if (!smu_table->metrics_table) 273 return -ENOMEM; 274 smu_table->metrics_time = 0; 275 276 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 277 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 278 if (!smu_table->gpu_metrics_table) { 279 kfree(smu_table->metrics_table); 280 return -ENOMEM; 281 } 282 283 return 0; 284 } 285 286 static int arcturus_allocate_dpm_context(struct smu_context *smu) 287 { 288 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 289 290 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 291 GFP_KERNEL); 292 if (!smu_dpm->dpm_context) 293 return -ENOMEM; 294 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 295 296 return 0; 297 } 298 299 static int arcturus_init_smc_tables(struct smu_context *smu) 300 { 301 int ret = 0; 302 303 ret = arcturus_tables_init(smu); 304 if (ret) 305 return ret; 306 307 ret = arcturus_allocate_dpm_context(smu); 308 if (ret) 309 return ret; 310 311 return smu_v11_0_init_smc_tables(smu); 312 } 313 314 static int 315 arcturus_get_allowed_feature_mask(struct smu_context *smu, 316 uint32_t *feature_mask, uint32_t num) 317 { 318 if (num > 2) 319 return -EINVAL; 320 321 /* pptable will handle the features to enable */ 322 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 323 324 return 0; 325 } 326 327 static int arcturus_set_default_dpm_table(struct smu_context *smu) 328 { 329 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 330 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 331 struct smu_11_0_dpm_table *dpm_table = NULL; 332 int ret = 0; 333 334 /* socclk dpm table setup */ 335 dpm_table = &dpm_context->dpm_tables.soc_table; 336 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 337 ret = smu_v11_0_set_single_dpm_table(smu, 338 SMU_SOCCLK, 339 dpm_table); 340 if (ret) 341 return ret; 342 dpm_table->is_fine_grained = 343 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 344 } else { 345 dpm_table->count = 1; 346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 347 dpm_table->dpm_levels[0].enabled = true; 348 dpm_table->min = dpm_table->dpm_levels[0].value; 349 dpm_table->max = dpm_table->dpm_levels[0].value; 350 } 351 352 /* gfxclk dpm table setup */ 353 dpm_table = &dpm_context->dpm_tables.gfx_table; 354 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 355 ret = smu_v11_0_set_single_dpm_table(smu, 356 SMU_GFXCLK, 357 dpm_table); 358 if (ret) 359 return ret; 360 dpm_table->is_fine_grained = 361 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 362 } else { 363 dpm_table->count = 1; 364 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 365 dpm_table->dpm_levels[0].enabled = true; 366 dpm_table->min = dpm_table->dpm_levels[0].value; 367 dpm_table->max = dpm_table->dpm_levels[0].value; 368 } 369 370 /* memclk dpm table setup */ 371 dpm_table = &dpm_context->dpm_tables.uclk_table; 372 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 373 ret = smu_v11_0_set_single_dpm_table(smu, 374 SMU_UCLK, 375 dpm_table); 376 if (ret) 377 return ret; 378 dpm_table->is_fine_grained = 379 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 380 } else { 381 dpm_table->count = 1; 382 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 383 dpm_table->dpm_levels[0].enabled = true; 384 dpm_table->min = dpm_table->dpm_levels[0].value; 385 dpm_table->max = dpm_table->dpm_levels[0].value; 386 } 387 388 /* fclk dpm table setup */ 389 dpm_table = &dpm_context->dpm_tables.fclk_table; 390 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 391 ret = smu_v11_0_set_single_dpm_table(smu, 392 SMU_FCLK, 393 dpm_table); 394 if (ret) 395 return ret; 396 dpm_table->is_fine_grained = 397 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; 398 } else { 399 dpm_table->count = 1; 400 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 401 dpm_table->dpm_levels[0].enabled = true; 402 dpm_table->min = dpm_table->dpm_levels[0].value; 403 dpm_table->max = dpm_table->dpm_levels[0].value; 404 } 405 406 return 0; 407 } 408 409 static void arcturus_check_bxco_support(struct smu_context *smu) 410 { 411 struct smu_table_context *table_context = &smu->smu_table; 412 struct smu_11_0_powerplay_table *powerplay_table = 413 table_context->power_play_table; 414 struct smu_baco_context *smu_baco = &smu->smu_baco; 415 struct amdgpu_device *adev = smu->adev; 416 uint32_t val; 417 418 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 419 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 420 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 421 smu_baco->platform_support = 422 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 423 false; 424 } 425 } 426 427 static void arcturus_check_fan_support(struct smu_context *smu) 428 { 429 struct smu_table_context *table_context = &smu->smu_table; 430 PPTable_t *pptable = table_context->driver_pptable; 431 432 /* No sort of fan control possible if PPTable has it disabled */ 433 smu->adev->pm.no_fan = 434 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK); 435 if (smu->adev->pm.no_fan) 436 dev_info_once(smu->adev->dev, 437 "PMFW based fan control disabled"); 438 } 439 440 static int arcturus_check_powerplay_table(struct smu_context *smu) 441 { 442 struct smu_table_context *table_context = &smu->smu_table; 443 struct smu_11_0_powerplay_table *powerplay_table = 444 table_context->power_play_table; 445 446 arcturus_check_bxco_support(smu); 447 arcturus_check_fan_support(smu); 448 449 table_context->thermal_controller_type = 450 powerplay_table->thermal_controller_type; 451 452 return 0; 453 } 454 455 static int arcturus_store_powerplay_table(struct smu_context *smu) 456 { 457 struct smu_table_context *table_context = &smu->smu_table; 458 struct smu_11_0_powerplay_table *powerplay_table = 459 table_context->power_play_table; 460 461 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 462 sizeof(PPTable_t)); 463 464 return 0; 465 } 466 467 static int arcturus_append_powerplay_table(struct smu_context *smu) 468 { 469 struct smu_table_context *table_context = &smu->smu_table; 470 PPTable_t *smc_pptable = table_context->driver_pptable; 471 struct atom_smc_dpm_info_v4_6 *smc_dpm_table; 472 int index, ret; 473 474 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 475 smc_dpm_info); 476 477 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 478 (uint8_t **)&smc_dpm_table); 479 if (ret) 480 return ret; 481 482 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 483 smc_dpm_table->table_header.format_revision, 484 smc_dpm_table->table_header.content_revision); 485 486 if ((smc_dpm_table->table_header.format_revision == 4) && 487 (smc_dpm_table->table_header.content_revision == 6)) 488 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved, 489 smc_dpm_table, maxvoltagestepgfx); 490 return 0; 491 } 492 493 static int arcturus_setup_pptable(struct smu_context *smu) 494 { 495 int ret = 0; 496 497 ret = smu_v11_0_setup_pptable(smu); 498 if (ret) 499 return ret; 500 501 ret = arcturus_store_powerplay_table(smu); 502 if (ret) 503 return ret; 504 505 ret = arcturus_append_powerplay_table(smu); 506 if (ret) 507 return ret; 508 509 ret = arcturus_check_powerplay_table(smu); 510 if (ret) 511 return ret; 512 513 return ret; 514 } 515 516 static int arcturus_run_btc(struct smu_context *smu) 517 { 518 int ret = 0; 519 520 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL); 521 if (ret) { 522 dev_err(smu->adev->dev, "RunAfllBtc failed!\n"); 523 return ret; 524 } 525 526 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 527 } 528 529 static int arcturus_populate_umd_state_clk(struct smu_context *smu) 530 { 531 struct smu_11_0_dpm_context *dpm_context = 532 smu->smu_dpm.dpm_context; 533 struct smu_11_0_dpm_table *gfx_table = 534 &dpm_context->dpm_tables.gfx_table; 535 struct smu_11_0_dpm_table *mem_table = 536 &dpm_context->dpm_tables.uclk_table; 537 struct smu_11_0_dpm_table *soc_table = 538 &dpm_context->dpm_tables.soc_table; 539 struct smu_umd_pstate_table *pstate_table = 540 &smu->pstate_table; 541 542 pstate_table->gfxclk_pstate.min = gfx_table->min; 543 pstate_table->gfxclk_pstate.peak = gfx_table->max; 544 545 pstate_table->uclk_pstate.min = mem_table->min; 546 pstate_table->uclk_pstate.peak = mem_table->max; 547 548 pstate_table->socclk_pstate.min = soc_table->min; 549 pstate_table->socclk_pstate.peak = soc_table->max; 550 551 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL && 552 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && 553 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) { 554 pstate_table->gfxclk_pstate.standard = 555 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value; 556 pstate_table->uclk_pstate.standard = 557 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value; 558 pstate_table->socclk_pstate.standard = 559 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value; 560 } else { 561 pstate_table->gfxclk_pstate.standard = 562 pstate_table->gfxclk_pstate.min; 563 pstate_table->uclk_pstate.standard = 564 pstate_table->uclk_pstate.min; 565 pstate_table->socclk_pstate.standard = 566 pstate_table->socclk_pstate.min; 567 } 568 569 return 0; 570 } 571 572 static int arcturus_get_clk_table(struct smu_context *smu, 573 struct pp_clock_levels_with_latency *clocks, 574 struct smu_11_0_dpm_table *dpm_table) 575 { 576 uint32_t i; 577 578 clocks->num_levels = min_t(uint32_t, 579 dpm_table->count, 580 (uint32_t)PP_MAX_CLOCK_LEVELS); 581 582 for (i = 0; i < clocks->num_levels; i++) { 583 clocks->data[i].clocks_in_khz = 584 dpm_table->dpm_levels[i].value * 1000; 585 clocks->data[i].latency_in_us = 0; 586 } 587 588 return 0; 589 } 590 591 static int arcturus_freqs_in_same_level(int32_t frequency1, 592 int32_t frequency2) 593 { 594 return (abs(frequency1 - frequency2) <= EPSILON); 595 } 596 597 static int arcturus_get_smu_metrics_data(struct smu_context *smu, 598 MetricsMember_t member, 599 uint32_t *value) 600 { 601 struct smu_table_context *smu_table = &smu->smu_table; 602 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 603 int ret = 0; 604 605 ret = smu_cmn_get_metrics_table(smu, 606 NULL, 607 false); 608 if (ret) 609 return ret; 610 611 switch (member) { 612 case METRICS_CURR_GFXCLK: 613 *value = metrics->CurrClock[PPCLK_GFXCLK]; 614 break; 615 case METRICS_CURR_SOCCLK: 616 *value = metrics->CurrClock[PPCLK_SOCCLK]; 617 break; 618 case METRICS_CURR_UCLK: 619 *value = metrics->CurrClock[PPCLK_UCLK]; 620 break; 621 case METRICS_CURR_VCLK: 622 *value = metrics->CurrClock[PPCLK_VCLK]; 623 break; 624 case METRICS_CURR_DCLK: 625 *value = metrics->CurrClock[PPCLK_DCLK]; 626 break; 627 case METRICS_CURR_FCLK: 628 *value = metrics->CurrClock[PPCLK_FCLK]; 629 break; 630 case METRICS_AVERAGE_GFXCLK: 631 *value = metrics->AverageGfxclkFrequency; 632 break; 633 case METRICS_AVERAGE_SOCCLK: 634 *value = metrics->AverageSocclkFrequency; 635 break; 636 case METRICS_AVERAGE_UCLK: 637 *value = metrics->AverageUclkFrequency; 638 break; 639 case METRICS_AVERAGE_VCLK: 640 *value = metrics->AverageVclkFrequency; 641 break; 642 case METRICS_AVERAGE_DCLK: 643 *value = metrics->AverageDclkFrequency; 644 break; 645 case METRICS_AVERAGE_GFXACTIVITY: 646 *value = metrics->AverageGfxActivity; 647 break; 648 case METRICS_AVERAGE_MEMACTIVITY: 649 *value = metrics->AverageUclkActivity; 650 break; 651 case METRICS_AVERAGE_VCNACTIVITY: 652 *value = metrics->VcnActivityPercentage; 653 break; 654 case METRICS_AVERAGE_SOCKETPOWER: 655 *value = metrics->AverageSocketPower << 8; 656 break; 657 case METRICS_TEMPERATURE_EDGE: 658 *value = metrics->TemperatureEdge * 659 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 660 break; 661 case METRICS_TEMPERATURE_HOTSPOT: 662 *value = metrics->TemperatureHotspot * 663 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 664 break; 665 case METRICS_TEMPERATURE_MEM: 666 *value = metrics->TemperatureHBM * 667 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 668 break; 669 case METRICS_TEMPERATURE_VRGFX: 670 *value = metrics->TemperatureVrGfx * 671 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 672 break; 673 case METRICS_TEMPERATURE_VRSOC: 674 *value = metrics->TemperatureVrSoc * 675 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 676 break; 677 case METRICS_TEMPERATURE_VRMEM: 678 *value = metrics->TemperatureVrMem * 679 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 680 break; 681 case METRICS_THROTTLER_STATUS: 682 *value = metrics->ThrottlerStatus; 683 break; 684 case METRICS_CURR_FANSPEED: 685 *value = metrics->CurrFanSpeed; 686 break; 687 default: 688 *value = UINT_MAX; 689 break; 690 } 691 692 return ret; 693 } 694 695 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu, 696 enum smu_clk_type clk_type, 697 uint32_t *value) 698 { 699 MetricsMember_t member_type; 700 int clk_id = 0; 701 702 if (!value) 703 return -EINVAL; 704 705 clk_id = smu_cmn_to_asic_specific_index(smu, 706 CMN2ASIC_MAPPING_CLK, 707 clk_type); 708 if (clk_id < 0) 709 return -EINVAL; 710 711 switch (clk_id) { 712 case PPCLK_GFXCLK: 713 /* 714 * CurrClock[clk_id] can provide accurate 715 * output only when the dpm feature is enabled. 716 * We can use Average_* for dpm disabled case. 717 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 718 */ 719 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 720 member_type = METRICS_CURR_GFXCLK; 721 else 722 member_type = METRICS_AVERAGE_GFXCLK; 723 break; 724 case PPCLK_UCLK: 725 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 726 member_type = METRICS_CURR_UCLK; 727 else 728 member_type = METRICS_AVERAGE_UCLK; 729 break; 730 case PPCLK_SOCCLK: 731 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 732 member_type = METRICS_CURR_SOCCLK; 733 else 734 member_type = METRICS_AVERAGE_SOCCLK; 735 break; 736 case PPCLK_VCLK: 737 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) 738 member_type = METRICS_CURR_VCLK; 739 else 740 member_type = METRICS_AVERAGE_VCLK; 741 break; 742 case PPCLK_DCLK: 743 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) 744 member_type = METRICS_CURR_DCLK; 745 else 746 member_type = METRICS_AVERAGE_DCLK; 747 break; 748 case PPCLK_FCLK: 749 member_type = METRICS_CURR_FCLK; 750 break; 751 default: 752 return -EINVAL; 753 } 754 755 return arcturus_get_smu_metrics_data(smu, 756 member_type, 757 value); 758 } 759 760 static int arcturus_print_clk_levels(struct smu_context *smu, 761 enum smu_clk_type type, char *buf) 762 { 763 int i, now, size = 0; 764 int ret = 0; 765 struct pp_clock_levels_with_latency clocks; 766 struct smu_11_0_dpm_table *single_dpm_table; 767 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 768 struct smu_11_0_dpm_context *dpm_context = NULL; 769 uint32_t gen_speed, lane_width; 770 771 smu_cmn_get_sysfs_buf(&buf, &size); 772 773 if (amdgpu_ras_intr_triggered()) { 774 size += sysfs_emit_at(buf, size, "unavailable\n"); 775 return size; 776 } 777 778 dpm_context = smu_dpm->dpm_context; 779 780 switch (type) { 781 case SMU_SCLK: 782 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 783 if (ret) { 784 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 785 return ret; 786 } 787 788 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 789 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 790 if (ret) { 791 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 792 return ret; 793 } 794 795 /* 796 * For DPM disabled case, there will be only one clock level. 797 * And it's safe to assume that is always the current clock. 798 */ 799 for (i = 0; i < clocks.num_levels; i++) 800 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 801 clocks.data[i].clocks_in_khz / 1000, 802 (clocks.num_levels == 1) ? "*" : 803 (arcturus_freqs_in_same_level( 804 clocks.data[i].clocks_in_khz / 1000, 805 now) ? "*" : "")); 806 break; 807 808 case SMU_MCLK: 809 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 810 if (ret) { 811 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 812 return ret; 813 } 814 815 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 816 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 817 if (ret) { 818 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 819 return ret; 820 } 821 822 for (i = 0; i < clocks.num_levels; i++) 823 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 824 i, clocks.data[i].clocks_in_khz / 1000, 825 (clocks.num_levels == 1) ? "*" : 826 (arcturus_freqs_in_same_level( 827 clocks.data[i].clocks_in_khz / 1000, 828 now) ? "*" : "")); 829 break; 830 831 case SMU_SOCCLK: 832 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 833 if (ret) { 834 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 835 return ret; 836 } 837 838 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 839 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 840 if (ret) { 841 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 842 return ret; 843 } 844 845 for (i = 0; i < clocks.num_levels; i++) 846 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 847 i, clocks.data[i].clocks_in_khz / 1000, 848 (clocks.num_levels == 1) ? "*" : 849 (arcturus_freqs_in_same_level( 850 clocks.data[i].clocks_in_khz / 1000, 851 now) ? "*" : "")); 852 break; 853 854 case SMU_FCLK: 855 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 856 if (ret) { 857 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 858 return ret; 859 } 860 861 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 862 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 863 if (ret) { 864 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 865 return ret; 866 } 867 868 for (i = 0; i < single_dpm_table->count; i++) 869 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 870 i, single_dpm_table->dpm_levels[i].value, 871 (clocks.num_levels == 1) ? "*" : 872 (arcturus_freqs_in_same_level( 873 clocks.data[i].clocks_in_khz / 1000, 874 now) ? "*" : "")); 875 break; 876 877 case SMU_VCLK: 878 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 879 if (ret) { 880 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 881 return ret; 882 } 883 884 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 885 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 886 if (ret) { 887 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 888 return ret; 889 } 890 891 for (i = 0; i < single_dpm_table->count; i++) 892 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 893 i, single_dpm_table->dpm_levels[i].value, 894 (clocks.num_levels == 1) ? "*" : 895 (arcturus_freqs_in_same_level( 896 clocks.data[i].clocks_in_khz / 1000, 897 now) ? "*" : "")); 898 break; 899 900 case SMU_DCLK: 901 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 902 if (ret) { 903 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 904 return ret; 905 } 906 907 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 908 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 909 if (ret) { 910 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 911 return ret; 912 } 913 914 for (i = 0; i < single_dpm_table->count; i++) 915 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 916 i, single_dpm_table->dpm_levels[i].value, 917 (clocks.num_levels == 1) ? "*" : 918 (arcturus_freqs_in_same_level( 919 clocks.data[i].clocks_in_khz / 1000, 920 now) ? "*" : "")); 921 break; 922 923 case SMU_PCIE: 924 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 925 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 926 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n", 927 (gen_speed == 0) ? "2.5GT/s," : 928 (gen_speed == 1) ? "5.0GT/s," : 929 (gen_speed == 2) ? "8.0GT/s," : 930 (gen_speed == 3) ? "16.0GT/s," : "", 931 (lane_width == 1) ? "x1" : 932 (lane_width == 2) ? "x2" : 933 (lane_width == 3) ? "x4" : 934 (lane_width == 4) ? "x8" : 935 (lane_width == 5) ? "x12" : 936 (lane_width == 6) ? "x16" : "", 937 smu->smu_table.boot_values.lclk / 100); 938 break; 939 940 default: 941 break; 942 } 943 944 return size; 945 } 946 947 static int arcturus_upload_dpm_level(struct smu_context *smu, 948 bool max, 949 uint32_t feature_mask, 950 uint32_t level) 951 { 952 struct smu_11_0_dpm_context *dpm_context = 953 smu->smu_dpm.dpm_context; 954 uint32_t freq; 955 int ret = 0; 956 957 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 958 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 959 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 960 ret = smu_cmn_send_smc_msg_with_param(smu, 961 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 962 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 963 NULL); 964 if (ret) { 965 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 966 max ? "max" : "min"); 967 return ret; 968 } 969 } 970 971 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 972 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 973 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 974 ret = smu_cmn_send_smc_msg_with_param(smu, 975 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 976 (PPCLK_UCLK << 16) | (freq & 0xffff), 977 NULL); 978 if (ret) { 979 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 980 max ? "max" : "min"); 981 return ret; 982 } 983 } 984 985 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 986 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 987 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 988 ret = smu_cmn_send_smc_msg_with_param(smu, 989 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 990 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 991 NULL); 992 if (ret) { 993 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 994 max ? "max" : "min"); 995 return ret; 996 } 997 } 998 999 return ret; 1000 } 1001 1002 static int arcturus_force_clk_levels(struct smu_context *smu, 1003 enum smu_clk_type type, uint32_t mask) 1004 { 1005 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1006 struct smu_11_0_dpm_table *single_dpm_table = NULL; 1007 uint32_t soft_min_level, soft_max_level; 1008 uint32_t smu_version; 1009 int ret = 0; 1010 1011 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1012 if (ret) { 1013 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 1014 return ret; 1015 } 1016 1017 if ((smu_version >= 0x361200) && 1018 (smu_version <= 0x361a00)) { 1019 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 1020 "54.18 - 54.26(included) SMU firmwares\n"); 1021 return -EOPNOTSUPP; 1022 } 1023 1024 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1025 soft_max_level = mask ? (fls(mask) - 1) : 0; 1026 1027 switch (type) { 1028 case SMU_SCLK: 1029 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1030 if (soft_max_level >= single_dpm_table->count) { 1031 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1032 soft_max_level, single_dpm_table->count - 1); 1033 ret = -EINVAL; 1034 break; 1035 } 1036 1037 ret = arcturus_upload_dpm_level(smu, 1038 false, 1039 FEATURE_DPM_GFXCLK_MASK, 1040 soft_min_level); 1041 if (ret) { 1042 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1043 break; 1044 } 1045 1046 ret = arcturus_upload_dpm_level(smu, 1047 true, 1048 FEATURE_DPM_GFXCLK_MASK, 1049 soft_max_level); 1050 if (ret) 1051 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1052 1053 break; 1054 1055 case SMU_MCLK: 1056 case SMU_SOCCLK: 1057 case SMU_FCLK: 1058 /* 1059 * Should not arrive here since Arcturus does not 1060 * support mclk/socclk/fclk softmin/softmax settings 1061 */ 1062 ret = -EINVAL; 1063 break; 1064 1065 default: 1066 break; 1067 } 1068 1069 return ret; 1070 } 1071 1072 static int arcturus_get_thermal_temperature_range(struct smu_context *smu, 1073 struct smu_temperature_range *range) 1074 { 1075 struct smu_table_context *table_context = &smu->smu_table; 1076 struct smu_11_0_powerplay_table *powerplay_table = 1077 table_context->power_play_table; 1078 PPTable_t *pptable = smu->smu_table.driver_pptable; 1079 1080 if (!range) 1081 return -EINVAL; 1082 1083 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1084 1085 range->max = pptable->TedgeLimit * 1086 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1087 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 1088 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1089 range->hotspot_crit_max = pptable->ThotspotLimit * 1090 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1091 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1092 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1093 range->mem_crit_max = pptable->TmemLimit * 1094 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1095 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1096 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1097 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1098 1099 return 0; 1100 } 1101 1102 static int arcturus_read_sensor(struct smu_context *smu, 1103 enum amd_pp_sensors sensor, 1104 void *data, uint32_t *size) 1105 { 1106 struct smu_table_context *table_context = &smu->smu_table; 1107 PPTable_t *pptable = table_context->driver_pptable; 1108 int ret = 0; 1109 1110 if (amdgpu_ras_intr_triggered()) 1111 return 0; 1112 1113 if (!data || !size) 1114 return -EINVAL; 1115 1116 switch (sensor) { 1117 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1118 *(uint32_t *)data = pptable->FanMaximumRpm; 1119 *size = 4; 1120 break; 1121 case AMDGPU_PP_SENSOR_MEM_LOAD: 1122 ret = arcturus_get_smu_metrics_data(smu, 1123 METRICS_AVERAGE_MEMACTIVITY, 1124 (uint32_t *)data); 1125 *size = 4; 1126 break; 1127 case AMDGPU_PP_SENSOR_GPU_LOAD: 1128 ret = arcturus_get_smu_metrics_data(smu, 1129 METRICS_AVERAGE_GFXACTIVITY, 1130 (uint32_t *)data); 1131 *size = 4; 1132 break; 1133 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 1134 ret = arcturus_get_smu_metrics_data(smu, 1135 METRICS_AVERAGE_SOCKETPOWER, 1136 (uint32_t *)data); 1137 *size = 4; 1138 break; 1139 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1140 ret = arcturus_get_smu_metrics_data(smu, 1141 METRICS_TEMPERATURE_HOTSPOT, 1142 (uint32_t *)data); 1143 *size = 4; 1144 break; 1145 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1146 ret = arcturus_get_smu_metrics_data(smu, 1147 METRICS_TEMPERATURE_EDGE, 1148 (uint32_t *)data); 1149 *size = 4; 1150 break; 1151 case AMDGPU_PP_SENSOR_MEM_TEMP: 1152 ret = arcturus_get_smu_metrics_data(smu, 1153 METRICS_TEMPERATURE_MEM, 1154 (uint32_t *)data); 1155 *size = 4; 1156 break; 1157 case AMDGPU_PP_SENSOR_GFX_MCLK: 1158 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1159 /* the output clock frequency in 10K unit */ 1160 *(uint32_t *)data *= 100; 1161 *size = 4; 1162 break; 1163 case AMDGPU_PP_SENSOR_GFX_SCLK: 1164 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1165 *(uint32_t *)data *= 100; 1166 *size = 4; 1167 break; 1168 case AMDGPU_PP_SENSOR_VDDGFX: 1169 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1170 *size = 4; 1171 break; 1172 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 1173 default: 1174 ret = -EOPNOTSUPP; 1175 break; 1176 } 1177 1178 return ret; 1179 } 1180 1181 static int arcturus_set_fan_static_mode(struct smu_context *smu, 1182 uint32_t mode) 1183 { 1184 struct amdgpu_device *adev = smu->adev; 1185 1186 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1187 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1188 CG_FDO_CTRL2, TMIN, 0)); 1189 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1190 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1191 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1192 1193 return 0; 1194 } 1195 1196 static int arcturus_get_fan_speed_rpm(struct smu_context *smu, 1197 uint32_t *speed) 1198 { 1199 struct amdgpu_device *adev = smu->adev; 1200 uint32_t crystal_clock_freq = 2500; 1201 uint32_t tach_status; 1202 uint64_t tmp64; 1203 int ret = 0; 1204 1205 if (!speed) 1206 return -EINVAL; 1207 1208 switch (smu_v11_0_get_fan_control_mode(smu)) { 1209 case AMD_FAN_CTRL_AUTO: 1210 ret = arcturus_get_smu_metrics_data(smu, 1211 METRICS_CURR_FANSPEED, 1212 speed); 1213 break; 1214 default: 1215 /* 1216 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1217 * detected via register retrieving. To workaround this, we will 1218 * report the fan speed as 0 RPM if user just requested such. 1219 */ 1220 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1221 && !smu->user_dpm_profile.fan_speed_rpm) { 1222 *speed = 0; 1223 return 0; 1224 } 1225 1226 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1227 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT); 1228 if (tach_status) { 1229 do_div(tmp64, tach_status); 1230 *speed = (uint32_t)tmp64; 1231 } else { 1232 *speed = 0; 1233 } 1234 1235 break; 1236 } 1237 1238 return ret; 1239 } 1240 1241 static int arcturus_set_fan_speed_pwm(struct smu_context *smu, 1242 uint32_t speed) 1243 { 1244 struct amdgpu_device *adev = smu->adev; 1245 uint32_t duty100, duty; 1246 uint64_t tmp64; 1247 1248 speed = MIN(speed, 255); 1249 1250 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1251 CG_FDO_CTRL1, FMAX_DUTY100); 1252 if (!duty100) 1253 return -EINVAL; 1254 1255 tmp64 = (uint64_t)speed * duty100; 1256 do_div(tmp64, 255); 1257 duty = (uint32_t)tmp64; 1258 1259 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT, 1260 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT), 1261 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1262 1263 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1264 } 1265 1266 static int arcturus_set_fan_speed_rpm(struct smu_context *smu, 1267 uint32_t speed) 1268 { 1269 struct amdgpu_device *adev = smu->adev; 1270 /* 1271 * crystal_clock_freq used for fan speed rpm calculation is 1272 * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1273 */ 1274 uint32_t crystal_clock_freq = 2500; 1275 uint32_t tach_period; 1276 1277 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1278 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT, 1279 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT), 1280 CG_TACH_CTRL, TARGET_PERIOD, 1281 tach_period)); 1282 1283 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1284 } 1285 1286 static int arcturus_get_fan_speed_pwm(struct smu_context *smu, 1287 uint32_t *speed) 1288 { 1289 struct amdgpu_device *adev = smu->adev; 1290 uint32_t duty100, duty; 1291 uint64_t tmp64; 1292 1293 /* 1294 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1295 * detected via register retrieving. To workaround this, we will 1296 * report the fan speed as 0 PWM if user just requested such. 1297 */ 1298 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 1299 && !smu->user_dpm_profile.fan_speed_pwm) { 1300 *speed = 0; 1301 return 0; 1302 } 1303 1304 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1305 CG_FDO_CTRL1, FMAX_DUTY100); 1306 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT), 1307 CG_THERMAL_STATUS, FDO_PWM_DUTY); 1308 1309 if (duty100) { 1310 tmp64 = (uint64_t)duty * 255; 1311 do_div(tmp64, duty100); 1312 *speed = MIN((uint32_t)tmp64, 255); 1313 } else { 1314 *speed = 0; 1315 } 1316 1317 return 0; 1318 } 1319 1320 static int arcturus_get_fan_parameters(struct smu_context *smu) 1321 { 1322 PPTable_t *pptable = smu->smu_table.driver_pptable; 1323 1324 smu->fan_max_rpm = pptable->FanMaximumRpm; 1325 1326 return 0; 1327 } 1328 1329 static int arcturus_get_power_limit(struct smu_context *smu, 1330 uint32_t *current_power_limit, 1331 uint32_t *default_power_limit, 1332 uint32_t *max_power_limit) 1333 { 1334 struct smu_11_0_powerplay_table *powerplay_table = 1335 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 1336 PPTable_t *pptable = smu->smu_table.driver_pptable; 1337 uint32_t power_limit, od_percent; 1338 1339 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1340 /* the last hope to figure out the ppt limit */ 1341 if (!pptable) { 1342 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1343 return -EINVAL; 1344 } 1345 power_limit = 1346 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1347 } 1348 1349 if (current_power_limit) 1350 *current_power_limit = power_limit; 1351 if (default_power_limit) 1352 *default_power_limit = power_limit; 1353 1354 if (max_power_limit) { 1355 if (smu->od_enabled) { 1356 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 1357 1358 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1359 1360 power_limit *= (100 + od_percent); 1361 power_limit /= 100; 1362 } 1363 1364 *max_power_limit = power_limit; 1365 } 1366 1367 return 0; 1368 } 1369 1370 static int arcturus_get_power_profile_mode(struct smu_context *smu, 1371 char *buf) 1372 { 1373 DpmActivityMonitorCoeffInt_t activity_monitor; 1374 static const char *title[] = { 1375 "PROFILE_INDEX(NAME)", 1376 "CLOCK_TYPE(NAME)", 1377 "FPS", 1378 "UseRlcBusy", 1379 "MinActiveFreqType", 1380 "MinActiveFreq", 1381 "BoosterFreqType", 1382 "BoosterFreq", 1383 "PD_Data_limit_c", 1384 "PD_Data_error_coeff", 1385 "PD_Data_error_rate_coeff"}; 1386 uint32_t i, size = 0; 1387 int16_t workload_type = 0; 1388 int result = 0; 1389 uint32_t smu_version; 1390 1391 if (!buf) 1392 return -EINVAL; 1393 1394 result = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1395 if (result) 1396 return result; 1397 1398 if (smu_version >= 0x360d00) 1399 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1400 title[0], title[1], title[2], title[3], title[4], title[5], 1401 title[6], title[7], title[8], title[9], title[10]); 1402 else 1403 size += sysfs_emit_at(buf, size, "%16s\n", 1404 title[0]); 1405 1406 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1407 /* 1408 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1409 * Not all profile modes are supported on arcturus. 1410 */ 1411 workload_type = smu_cmn_to_asic_specific_index(smu, 1412 CMN2ASIC_MAPPING_WORKLOAD, 1413 i); 1414 if (workload_type < 0) 1415 continue; 1416 1417 if (smu_version >= 0x360d00) { 1418 result = smu_cmn_update_table(smu, 1419 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1420 workload_type, 1421 (void *)(&activity_monitor), 1422 false); 1423 if (result) { 1424 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1425 return result; 1426 } 1427 } 1428 1429 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1430 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1431 1432 if (smu_version >= 0x360d00) { 1433 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1434 " ", 1435 0, 1436 "GFXCLK", 1437 activity_monitor.Gfx_FPS, 1438 activity_monitor.Gfx_UseRlcBusy, 1439 activity_monitor.Gfx_MinActiveFreqType, 1440 activity_monitor.Gfx_MinActiveFreq, 1441 activity_monitor.Gfx_BoosterFreqType, 1442 activity_monitor.Gfx_BoosterFreq, 1443 activity_monitor.Gfx_PD_Data_limit_c, 1444 activity_monitor.Gfx_PD_Data_error_coeff, 1445 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1446 1447 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1448 " ", 1449 1, 1450 "UCLK", 1451 activity_monitor.Mem_FPS, 1452 activity_monitor.Mem_UseRlcBusy, 1453 activity_monitor.Mem_MinActiveFreqType, 1454 activity_monitor.Mem_MinActiveFreq, 1455 activity_monitor.Mem_BoosterFreqType, 1456 activity_monitor.Mem_BoosterFreq, 1457 activity_monitor.Mem_PD_Data_limit_c, 1458 activity_monitor.Mem_PD_Data_error_coeff, 1459 activity_monitor.Mem_PD_Data_error_rate_coeff); 1460 } 1461 } 1462 1463 return size; 1464 } 1465 1466 static int arcturus_set_power_profile_mode(struct smu_context *smu, 1467 long *input, 1468 uint32_t size) 1469 { 1470 DpmActivityMonitorCoeffInt_t activity_monitor; 1471 int workload_type = 0; 1472 uint32_t profile_mode = input[size]; 1473 int ret = 0; 1474 uint32_t smu_version; 1475 1476 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1477 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1478 return -EINVAL; 1479 } 1480 1481 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1482 if (ret) 1483 return ret; 1484 1485 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && 1486 (smu_version >= 0x360d00)) { 1487 ret = smu_cmn_update_table(smu, 1488 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1489 WORKLOAD_PPLIB_CUSTOM_BIT, 1490 (void *)(&activity_monitor), 1491 false); 1492 if (ret) { 1493 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1494 return ret; 1495 } 1496 1497 switch (input[0]) { 1498 case 0: /* Gfxclk */ 1499 activity_monitor.Gfx_FPS = input[1]; 1500 activity_monitor.Gfx_UseRlcBusy = input[2]; 1501 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1502 activity_monitor.Gfx_MinActiveFreq = input[4]; 1503 activity_monitor.Gfx_BoosterFreqType = input[5]; 1504 activity_monitor.Gfx_BoosterFreq = input[6]; 1505 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1506 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1507 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1508 break; 1509 case 1: /* Uclk */ 1510 activity_monitor.Mem_FPS = input[1]; 1511 activity_monitor.Mem_UseRlcBusy = input[2]; 1512 activity_monitor.Mem_MinActiveFreqType = input[3]; 1513 activity_monitor.Mem_MinActiveFreq = input[4]; 1514 activity_monitor.Mem_BoosterFreqType = input[5]; 1515 activity_monitor.Mem_BoosterFreq = input[6]; 1516 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1517 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1518 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1519 break; 1520 } 1521 1522 ret = smu_cmn_update_table(smu, 1523 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1524 WORKLOAD_PPLIB_CUSTOM_BIT, 1525 (void *)(&activity_monitor), 1526 true); 1527 if (ret) { 1528 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1529 return ret; 1530 } 1531 } 1532 1533 /* 1534 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1535 * Not all profile modes are supported on arcturus. 1536 */ 1537 workload_type = smu_cmn_to_asic_specific_index(smu, 1538 CMN2ASIC_MAPPING_WORKLOAD, 1539 profile_mode); 1540 if (workload_type < 0) { 1541 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode); 1542 return -EINVAL; 1543 } 1544 1545 ret = smu_cmn_send_smc_msg_with_param(smu, 1546 SMU_MSG_SetWorkloadMask, 1547 1 << workload_type, 1548 NULL); 1549 if (ret) { 1550 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 1551 return ret; 1552 } 1553 1554 smu->power_profile_mode = profile_mode; 1555 1556 return 0; 1557 } 1558 1559 static int arcturus_set_performance_level(struct smu_context *smu, 1560 enum amd_dpm_forced_level level) 1561 { 1562 uint32_t smu_version; 1563 int ret; 1564 1565 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1566 if (ret) { 1567 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 1568 return ret; 1569 } 1570 1571 switch (level) { 1572 case AMD_DPM_FORCED_LEVEL_HIGH: 1573 case AMD_DPM_FORCED_LEVEL_LOW: 1574 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1575 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1576 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1577 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1578 if ((smu_version >= 0x361200) && 1579 (smu_version <= 0x361a00)) { 1580 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 1581 "54.18 - 54.26(included) SMU firmwares\n"); 1582 return -EOPNOTSUPP; 1583 } 1584 break; 1585 default: 1586 break; 1587 } 1588 1589 return smu_v11_0_set_performance_level(smu, level); 1590 } 1591 1592 static void arcturus_dump_pptable(struct smu_context *smu) 1593 { 1594 struct smu_table_context *table_context = &smu->smu_table; 1595 PPTable_t *pptable = table_context->driver_pptable; 1596 int i; 1597 1598 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 1599 1600 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 1601 1602 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 1603 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 1604 1605 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 1606 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]); 1607 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]); 1608 } 1609 1610 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc); 1611 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau); 1612 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx); 1613 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau); 1614 1615 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit); 1616 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit); 1617 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit); 1618 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit); 1619 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit); 1620 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit); 1621 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit); 1622 1623 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit); 1624 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); 1625 1626 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask); 1627 1628 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); 1629 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding); 1630 1631 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass); 1632 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]); 1633 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]); 1634 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]); 1635 1636 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx); 1637 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc); 1638 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx); 1639 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc); 1640 1641 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx); 1642 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc); 1643 1644 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 1645 " .VoltageMode = 0x%02x\n" 1646 " .SnapToDiscrete = 0x%02x\n" 1647 " .NumDiscreteLevels = 0x%02x\n" 1648 " .padding = 0x%02x\n" 1649 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1650 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1651 " .SsFmin = 0x%04x\n" 1652 " .Padding_16 = 0x%04x\n", 1653 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 1654 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 1655 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 1656 pptable->DpmDescriptor[PPCLK_GFXCLK].padding, 1657 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 1658 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 1659 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 1660 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 1661 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 1662 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 1663 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 1664 1665 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n" 1666 " .VoltageMode = 0x%02x\n" 1667 " .SnapToDiscrete = 0x%02x\n" 1668 " .NumDiscreteLevels = 0x%02x\n" 1669 " .padding = 0x%02x\n" 1670 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1671 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1672 " .SsFmin = 0x%04x\n" 1673 " .Padding_16 = 0x%04x\n", 1674 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode, 1675 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete, 1676 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels, 1677 pptable->DpmDescriptor[PPCLK_VCLK].padding, 1678 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m, 1679 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b, 1680 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a, 1681 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b, 1682 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c, 1683 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin, 1684 pptable->DpmDescriptor[PPCLK_VCLK].Padding16); 1685 1686 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n" 1687 " .VoltageMode = 0x%02x\n" 1688 " .SnapToDiscrete = 0x%02x\n" 1689 " .NumDiscreteLevels = 0x%02x\n" 1690 " .padding = 0x%02x\n" 1691 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1692 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1693 " .SsFmin = 0x%04x\n" 1694 " .Padding_16 = 0x%04x\n", 1695 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode, 1696 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete, 1697 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels, 1698 pptable->DpmDescriptor[PPCLK_DCLK].padding, 1699 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m, 1700 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b, 1701 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a, 1702 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b, 1703 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c, 1704 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin, 1705 pptable->DpmDescriptor[PPCLK_DCLK].Padding16); 1706 1707 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 1708 " .VoltageMode = 0x%02x\n" 1709 " .SnapToDiscrete = 0x%02x\n" 1710 " .NumDiscreteLevels = 0x%02x\n" 1711 " .padding = 0x%02x\n" 1712 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1713 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1714 " .SsFmin = 0x%04x\n" 1715 " .Padding_16 = 0x%04x\n", 1716 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 1717 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 1718 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 1719 pptable->DpmDescriptor[PPCLK_SOCCLK].padding, 1720 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 1721 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 1722 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 1723 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 1724 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 1725 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 1726 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 1727 1728 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 1729 " .VoltageMode = 0x%02x\n" 1730 " .SnapToDiscrete = 0x%02x\n" 1731 " .NumDiscreteLevels = 0x%02x\n" 1732 " .padding = 0x%02x\n" 1733 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1734 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1735 " .SsFmin = 0x%04x\n" 1736 " .Padding_16 = 0x%04x\n", 1737 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 1738 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 1739 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 1740 pptable->DpmDescriptor[PPCLK_UCLK].padding, 1741 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 1742 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 1743 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 1744 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 1745 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 1746 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 1747 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 1748 1749 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 1750 " .VoltageMode = 0x%02x\n" 1751 " .SnapToDiscrete = 0x%02x\n" 1752 " .NumDiscreteLevels = 0x%02x\n" 1753 " .padding = 0x%02x\n" 1754 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1755 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1756 " .SsFmin = 0x%04x\n" 1757 " .Padding_16 = 0x%04x\n", 1758 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 1759 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 1760 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 1761 pptable->DpmDescriptor[PPCLK_FCLK].padding, 1762 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 1763 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 1764 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 1765 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 1766 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 1767 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 1768 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 1769 1770 1771 dev_info(smu->adev->dev, "FreqTableGfx\n"); 1772 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 1773 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]); 1774 1775 dev_info(smu->adev->dev, "FreqTableVclk\n"); 1776 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 1777 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]); 1778 1779 dev_info(smu->adev->dev, "FreqTableDclk\n"); 1780 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 1781 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]); 1782 1783 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 1784 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 1785 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]); 1786 1787 dev_info(smu->adev->dev, "FreqTableUclk\n"); 1788 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 1789 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]); 1790 1791 dev_info(smu->adev->dev, "FreqTableFclk\n"); 1792 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 1793 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]); 1794 1795 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 1796 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1797 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]); 1798 1799 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 1800 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1801 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]); 1802 1803 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 1804 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate); 1805 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]); 1806 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]); 1807 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]); 1808 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]); 1809 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq); 1810 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 1811 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456); 1812 1813 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm); 1814 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature); 1815 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature); 1816 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit); 1817 1818 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp); 1819 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp); 1820 1821 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge); 1822 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot); 1823 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx); 1824 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc); 1825 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem); 1826 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm); 1827 1828 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin); 1829 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm); 1830 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm); 1831 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm); 1832 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature); 1833 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk); 1834 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable); 1835 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev); 1836 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect); 1837 1838 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta); 1839 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta); 1840 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta); 1841 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved); 1842 1843 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 1844 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 1845 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]); 1846 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]); 1847 1848 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 1849 pptable->dBtcGbGfxPll.a, 1850 pptable->dBtcGbGfxPll.b, 1851 pptable->dBtcGbGfxPll.c); 1852 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 1853 pptable->dBtcGbGfxAfll.a, 1854 pptable->dBtcGbGfxAfll.b, 1855 pptable->dBtcGbGfxAfll.c); 1856 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 1857 pptable->dBtcGbSoc.a, 1858 pptable->dBtcGbSoc.b, 1859 pptable->dBtcGbSoc.c); 1860 1861 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 1862 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 1863 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 1864 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 1865 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 1866 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 1867 1868 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 1869 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 1870 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 1871 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 1872 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 1873 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 1874 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 1875 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 1876 1877 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 1878 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 1879 1880 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 1881 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 1882 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 1883 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 1884 1885 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 1886 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 1887 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 1888 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 1889 1890 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 1891 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 1892 1893 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 1894 for (i = 0; i < NUM_XGMI_LEVELS; i++) 1895 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]); 1896 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 1897 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 1898 1899 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin); 1900 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin); 1901 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp); 1902 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp); 1903 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp); 1904 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp); 1905 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis); 1906 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis); 1907 1908 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 1909 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 1910 pptable->ReservedEquation0.a, 1911 pptable->ReservedEquation0.b, 1912 pptable->ReservedEquation0.c); 1913 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 1914 pptable->ReservedEquation1.a, 1915 pptable->ReservedEquation1.b, 1916 pptable->ReservedEquation1.c); 1917 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 1918 pptable->ReservedEquation2.a, 1919 pptable->ReservedEquation2.b, 1920 pptable->ReservedEquation2.c); 1921 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 1922 pptable->ReservedEquation3.a, 1923 pptable->ReservedEquation3.b, 1924 pptable->ReservedEquation3.c); 1925 1926 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); 1927 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv); 1928 1929 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig); 1930 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1); 1931 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2); 1932 1933 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow); 1934 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh); 1935 1936 dev_info(smu->adev->dev, "Board Parameters:\n"); 1937 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); 1938 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); 1939 1940 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 1941 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 1942 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping); 1943 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping); 1944 1945 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 1946 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent); 1947 1948 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 1949 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 1950 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 1951 1952 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 1953 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 1954 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 1955 1956 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent); 1957 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset); 1958 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem); 1959 1960 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent); 1961 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset); 1962 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput); 1963 1964 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio); 1965 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity); 1966 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio); 1967 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity); 1968 1969 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled); 1970 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent); 1971 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq); 1972 1973 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled); 1974 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent); 1975 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq); 1976 1977 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled); 1978 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent); 1979 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq); 1980 1981 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled); 1982 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); 1983 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); 1984 1985 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 1986 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 1987 dev_info(smu->adev->dev, " .Enabled = %d\n", 1988 pptable->I2cControllers[i].Enabled); 1989 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 1990 pptable->I2cControllers[i].SlaveAddress); 1991 dev_info(smu->adev->dev, " .ControllerPort = %d\n", 1992 pptable->I2cControllers[i].ControllerPort); 1993 dev_info(smu->adev->dev, " .ControllerName = %d\n", 1994 pptable->I2cControllers[i].ControllerName); 1995 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n", 1996 pptable->I2cControllers[i].ThermalThrotter); 1997 dev_info(smu->adev->dev, " .I2cProtocol = %d\n", 1998 pptable->I2cControllers[i].I2cProtocol); 1999 dev_info(smu->adev->dev, " .Speed = %d\n", 2000 pptable->I2cControllers[i].Speed); 2001 } 2002 2003 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled); 2004 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth); 2005 2006 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower); 2007 2008 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2009 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2010 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]); 2011 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2012 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2013 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]); 2014 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2015 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2016 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]); 2017 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2018 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2019 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]); 2020 2021 } 2022 2023 static bool arcturus_is_dpm_running(struct smu_context *smu) 2024 { 2025 int ret = 0; 2026 uint64_t feature_enabled; 2027 2028 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 2029 if (ret) 2030 return false; 2031 2032 return !!(feature_enabled & SMC_DPM_FEATURE); 2033 } 2034 2035 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 2036 { 2037 int ret = 0; 2038 2039 if (enable) { 2040 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) { 2041 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1); 2042 if (ret) { 2043 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n"); 2044 return ret; 2045 } 2046 } 2047 } else { 2048 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) { 2049 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0); 2050 if (ret) { 2051 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n"); 2052 return ret; 2053 } 2054 } 2055 } 2056 2057 return ret; 2058 } 2059 2060 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap, 2061 struct i2c_msg *msg, int num_msgs) 2062 { 2063 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap); 2064 struct amdgpu_device *adev = smu_i2c->adev; 2065 struct smu_context *smu = adev->powerplay.pp_handle; 2066 struct smu_table_context *smu_table = &smu->smu_table; 2067 struct smu_table *table = &smu_table->driver_table; 2068 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2069 int i, j, r, c; 2070 u16 dir; 2071 2072 if (!adev->pm.dpm_enabled) 2073 return -EBUSY; 2074 2075 req = kzalloc(sizeof(*req), GFP_KERNEL); 2076 if (!req) 2077 return -ENOMEM; 2078 2079 req->I2CcontrollerPort = smu_i2c->port; 2080 req->I2CSpeed = I2C_SPEED_FAST_400K; 2081 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2082 dir = msg[0].flags & I2C_M_RD; 2083 2084 for (c = i = 0; i < num_msgs; i++) { 2085 for (j = 0; j < msg[i].len; j++, c++) { 2086 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2087 2088 if (!(msg[i].flags & I2C_M_RD)) { 2089 /* write */ 2090 cmd->Cmd = I2C_CMD_WRITE; 2091 cmd->RegisterAddr = msg[i].buf[j]; 2092 } 2093 2094 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2095 /* The direction changes. 2096 */ 2097 dir = msg[i].flags & I2C_M_RD; 2098 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2099 } 2100 2101 req->NumCmds++; 2102 2103 /* 2104 * Insert STOP if we are at the last byte of either last 2105 * message for the transaction or the client explicitly 2106 * requires a STOP at this particular message. 2107 */ 2108 if ((j == msg[i].len - 1) && 2109 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2110 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2111 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2112 } 2113 } 2114 } 2115 mutex_lock(&adev->pm.mutex); 2116 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2117 if (r) 2118 goto fail; 2119 2120 for (c = i = 0; i < num_msgs; i++) { 2121 if (!(msg[i].flags & I2C_M_RD)) { 2122 c += msg[i].len; 2123 continue; 2124 } 2125 for (j = 0; j < msg[i].len; j++, c++) { 2126 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2127 2128 msg[i].buf[j] = cmd->Data; 2129 } 2130 } 2131 r = num_msgs; 2132 fail: 2133 mutex_unlock(&adev->pm.mutex); 2134 kfree(req); 2135 return r; 2136 } 2137 2138 static u32 arcturus_i2c_func(struct i2c_adapter *adap) 2139 { 2140 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2141 } 2142 2143 2144 static const struct i2c_algorithm arcturus_i2c_algo = { 2145 .master_xfer = arcturus_i2c_xfer, 2146 .functionality = arcturus_i2c_func, 2147 }; 2148 2149 2150 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = { 2151 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2152 .max_read_len = MAX_SW_I2C_COMMANDS, 2153 .max_write_len = MAX_SW_I2C_COMMANDS, 2154 .max_comb_1st_msg_len = 2, 2155 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2156 }; 2157 2158 static int arcturus_i2c_control_init(struct smu_context *smu) 2159 { 2160 struct amdgpu_device *adev = smu->adev; 2161 int res, i; 2162 2163 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2164 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2165 struct i2c_adapter *control = &smu_i2c->adapter; 2166 2167 smu_i2c->adev = adev; 2168 smu_i2c->port = i; 2169 mutex_init(&smu_i2c->mutex); 2170 control->owner = THIS_MODULE; 2171 control->class = I2C_CLASS_HWMON; 2172 control->dev.parent = &adev->pdev->dev; 2173 control->algo = &arcturus_i2c_algo; 2174 control->quirks = &arcturus_i2c_control_quirks; 2175 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i); 2176 i2c_set_adapdata(control, smu_i2c); 2177 2178 res = i2c_add_adapter(control); 2179 if (res) { 2180 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2181 goto Out_err; 2182 } 2183 } 2184 2185 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 2186 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter; 2187 2188 return 0; 2189 Out_err: 2190 for ( ; i >= 0; i--) { 2191 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2192 struct i2c_adapter *control = &smu_i2c->adapter; 2193 2194 i2c_del_adapter(control); 2195 } 2196 return res; 2197 } 2198 2199 static void arcturus_i2c_control_fini(struct smu_context *smu) 2200 { 2201 struct amdgpu_device *adev = smu->adev; 2202 int i; 2203 2204 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) { 2205 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i]; 2206 struct i2c_adapter *control = &smu_i2c->adapter; 2207 2208 i2c_del_adapter(control); 2209 } 2210 adev->pm.ras_eeprom_i2c_bus = NULL; 2211 adev->pm.fru_eeprom_i2c_bus = NULL; 2212 } 2213 2214 static void arcturus_get_unique_id(struct smu_context *smu) 2215 { 2216 struct amdgpu_device *adev = smu->adev; 2217 uint32_t top32 = 0, bottom32 = 0, smu_version; 2218 uint64_t id; 2219 2220 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) { 2221 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n"); 2222 return; 2223 } 2224 2225 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */ 2226 if (smu_version < 0x361700) { 2227 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n"); 2228 return; 2229 } 2230 2231 /* Get the SN to turn into a Unique ID */ 2232 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32); 2233 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32); 2234 2235 id = ((uint64_t)bottom32 << 32) | top32; 2236 adev->unique_id = id; 2237 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a 2238 * 16-digit HEX string for convenience and backwards-compatibility 2239 */ 2240 sprintf(adev->serial, "%llx", id); 2241 } 2242 2243 static int arcturus_set_df_cstate(struct smu_context *smu, 2244 enum pp_df_cstate state) 2245 { 2246 struct amdgpu_device *adev = smu->adev; 2247 uint32_t smu_version; 2248 int ret; 2249 2250 /* 2251 * Arcturus does not need the cstate disablement 2252 * prerequisite for gpu reset. 2253 */ 2254 if (amdgpu_in_reset(adev) || adev->in_suspend) 2255 return 0; 2256 2257 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2258 if (ret) { 2259 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2260 return ret; 2261 } 2262 2263 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */ 2264 if (smu_version < 0x360F00) { 2265 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n"); 2266 return -EINVAL; 2267 } 2268 2269 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 2270 } 2271 2272 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en) 2273 { 2274 uint32_t smu_version; 2275 int ret; 2276 2277 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2278 if (ret) { 2279 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2280 return ret; 2281 } 2282 2283 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */ 2284 if (smu_version < 0x00361700) { 2285 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n"); 2286 return -EINVAL; 2287 } 2288 2289 if (en) 2290 return smu_cmn_send_smc_msg_with_param(smu, 2291 SMU_MSG_GmiPwrDnControl, 2292 1, 2293 NULL); 2294 2295 return smu_cmn_send_smc_msg_with_param(smu, 2296 SMU_MSG_GmiPwrDnControl, 2297 0, 2298 NULL); 2299 } 2300 2301 static const struct throttling_logging_label { 2302 uint32_t feature_mask; 2303 const char *label; 2304 } logging_label[] = { 2305 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"}, 2306 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 2307 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 2308 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 2309 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 2310 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"}, 2311 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"}, 2312 }; 2313 static void arcturus_log_thermal_throttling_event(struct smu_context *smu) 2314 { 2315 int ret; 2316 int throttler_idx, throtting_events = 0, buf_idx = 0; 2317 struct amdgpu_device *adev = smu->adev; 2318 uint32_t throttler_status; 2319 char log_buf[256]; 2320 2321 ret = arcturus_get_smu_metrics_data(smu, 2322 METRICS_THROTTLER_STATUS, 2323 &throttler_status); 2324 if (ret) 2325 return; 2326 2327 memset(log_buf, 0, sizeof(log_buf)); 2328 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 2329 throttler_idx++) { 2330 if (throttler_status & logging_label[throttler_idx].feature_mask) { 2331 throtting_events++; 2332 buf_idx += snprintf(log_buf + buf_idx, 2333 sizeof(log_buf) - buf_idx, 2334 "%s%s", 2335 throtting_events > 1 ? " and " : "", 2336 logging_label[throttler_idx].label); 2337 if (buf_idx >= sizeof(log_buf)) { 2338 dev_err(adev->dev, "buffer overflow!\n"); 2339 log_buf[sizeof(log_buf) - 1] = '\0'; 2340 break; 2341 } 2342 } 2343 } 2344 2345 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 2346 log_buf); 2347 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 2348 smu_cmn_get_indep_throttler_status(throttler_status, 2349 arcturus_throttler_map)); 2350 } 2351 2352 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu) 2353 { 2354 struct amdgpu_device *adev = smu->adev; 2355 uint32_t esm_ctrl; 2356 2357 /* TODO: confirm this on real target */ 2358 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 2359 if ((esm_ctrl >> 15) & 0x1) 2360 return (uint16_t)(((esm_ctrl >> 8) & 0x7F) + 128); 2361 2362 return smu_v11_0_get_current_pcie_link_speed(smu); 2363 } 2364 2365 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, 2366 void **table) 2367 { 2368 struct smu_table_context *smu_table = &smu->smu_table; 2369 struct gpu_metrics_v1_3 *gpu_metrics = 2370 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2371 SmuMetrics_t metrics; 2372 int ret = 0; 2373 2374 ret = smu_cmn_get_metrics_table(smu, 2375 &metrics, 2376 true); 2377 if (ret) 2378 return ret; 2379 2380 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2381 2382 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2383 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2384 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2385 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2386 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2387 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2388 2389 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2390 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2391 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 2392 2393 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2394 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 2395 2396 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2397 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2398 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2399 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 2400 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 2401 2402 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2403 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2404 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2405 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2406 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2407 2408 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2409 gpu_metrics->indep_throttle_status = 2410 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2411 arcturus_throttler_map); 2412 2413 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2414 2415 gpu_metrics->pcie_link_width = 2416 smu_v11_0_get_current_pcie_link_width(smu); 2417 gpu_metrics->pcie_link_speed = 2418 arcturus_get_current_pcie_link_speed(smu); 2419 2420 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2421 2422 *table = (void *)gpu_metrics; 2423 2424 return sizeof(struct gpu_metrics_v1_3); 2425 } 2426 2427 static const struct pptable_funcs arcturus_ppt_funcs = { 2428 /* init dpm */ 2429 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, 2430 /* btc */ 2431 .run_btc = arcturus_run_btc, 2432 /* dpm/clk tables */ 2433 .set_default_dpm_table = arcturus_set_default_dpm_table, 2434 .populate_umd_state_clk = arcturus_populate_umd_state_clk, 2435 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range, 2436 .print_clk_levels = arcturus_print_clk_levels, 2437 .force_clk_levels = arcturus_force_clk_levels, 2438 .read_sensor = arcturus_read_sensor, 2439 .get_fan_speed_pwm = arcturus_get_fan_speed_pwm, 2440 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm, 2441 .get_power_profile_mode = arcturus_get_power_profile_mode, 2442 .set_power_profile_mode = arcturus_set_power_profile_mode, 2443 .set_performance_level = arcturus_set_performance_level, 2444 /* debug (internal used) */ 2445 .dump_pptable = arcturus_dump_pptable, 2446 .get_power_limit = arcturus_get_power_limit, 2447 .is_dpm_running = arcturus_is_dpm_running, 2448 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable, 2449 .i2c_init = arcturus_i2c_control_init, 2450 .i2c_fini = arcturus_i2c_control_fini, 2451 .get_unique_id = arcturus_get_unique_id, 2452 .init_microcode = smu_v11_0_init_microcode, 2453 .load_microcode = smu_v11_0_load_microcode, 2454 .fini_microcode = smu_v11_0_fini_microcode, 2455 .init_smc_tables = arcturus_init_smc_tables, 2456 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2457 .init_power = smu_v11_0_init_power, 2458 .fini_power = smu_v11_0_fini_power, 2459 .check_fw_status = smu_v11_0_check_fw_status, 2460 /* pptable related */ 2461 .setup_pptable = arcturus_setup_pptable, 2462 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2463 .check_fw_version = smu_v11_0_check_fw_version, 2464 .write_pptable = smu_cmn_write_pptable, 2465 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2466 .set_tool_table_location = smu_v11_0_set_tool_table_location, 2467 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2468 .system_features_control = smu_v11_0_system_features_control, 2469 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2470 .send_smc_msg = smu_cmn_send_smc_msg, 2471 .init_display_count = NULL, 2472 .set_allowed_mask = smu_v11_0_set_allowed_mask, 2473 .get_enabled_mask = smu_cmn_get_enabled_mask, 2474 .feature_is_enabled = smu_cmn_feature_is_enabled, 2475 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2476 .notify_display_change = NULL, 2477 .set_power_limit = smu_v11_0_set_power_limit, 2478 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 2479 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 2480 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 2481 .set_min_dcef_deep_sleep = NULL, 2482 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 2483 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 2484 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 2485 .set_fan_speed_pwm = arcturus_set_fan_speed_pwm, 2486 .set_fan_speed_rpm = arcturus_set_fan_speed_rpm, 2487 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 2488 .gfx_off_control = smu_v11_0_gfx_off_control, 2489 .register_irq_handler = smu_v11_0_register_irq_handler, 2490 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 2491 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 2492 .baco_is_support = smu_v11_0_baco_is_support, 2493 .baco_get_state = smu_v11_0_baco_get_state, 2494 .baco_set_state = smu_v11_0_baco_set_state, 2495 .baco_enter = smu_v11_0_baco_enter, 2496 .baco_exit = smu_v11_0_baco_exit, 2497 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 2498 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 2499 .set_df_cstate = arcturus_set_df_cstate, 2500 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, 2501 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, 2502 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2503 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2504 .get_gpu_metrics = arcturus_get_gpu_metrics, 2505 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 2506 .deep_sleep_control = smu_v11_0_deep_sleep_control, 2507 .get_fan_parameters = arcturus_get_fan_parameters, 2508 .interrupt_work = smu_v11_0_interrupt_work, 2509 .smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr, 2510 .set_mp1_state = smu_cmn_set_mp1_state, 2511 }; 2512 2513 void arcturus_set_ppt_funcs(struct smu_context *smu) 2514 { 2515 smu->ppt_funcs = &arcturus_ppt_funcs; 2516 smu->message_map = arcturus_message_map; 2517 smu->clock_map = arcturus_clk_map; 2518 smu->feature_map = arcturus_feature_mask_map; 2519 smu->table_map = arcturus_table_map; 2520 smu->pwr_src_map = arcturus_pwr_src_map; 2521 smu->workload_map = arcturus_workload_map; 2522 smu_v11_0_set_smu_mailbox_registers(smu); 2523 } 2524