1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #define SWSMU_CODE_LAYER_L2 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_smu.h" 29 #include "atomfirmware.h" 30 #include "amdgpu_atomfirmware.h" 31 #include "amdgpu_atombios.h" 32 #include "smu_v11_0.h" 33 #include "smu11_driver_if_arcturus.h" 34 #include "soc15_common.h" 35 #include "atom.h" 36 #include "power_state.h" 37 #include "arcturus_ppt.h" 38 #include "smu_v11_0_pptable.h" 39 #include "arcturus_ppsmc.h" 40 #include "nbio/nbio_7_4_offset.h" 41 #include "nbio/nbio_7_4_sh_mask.h" 42 #include "thm/thm_11_0_2_offset.h" 43 #include "thm/thm_11_0_2_sh_mask.h" 44 #include "amdgpu_xgmi.h" 45 #include <linux/i2c.h> 46 #include <linux/pci.h> 47 #include "amdgpu_ras.h" 48 #include "smu_cmn.h" 49 50 /* 51 * DO NOT use these for err/warn/info/debug messages. 52 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 53 * They are more MGPU friendly. 54 */ 55 #undef pr_err 56 #undef pr_warn 57 #undef pr_info 58 #undef pr_debug 59 60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 61 62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \ 63 [smu_feature] = {1, (arcturus_feature)} 64 65 #define SMU_FEATURES_LOW_MASK 0x00000000FFFFFFFF 66 #define SMU_FEATURES_LOW_SHIFT 0 67 #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 68 #define SMU_FEATURES_HIGH_SHIFT 32 69 70 #define SMC_DPM_FEATURE ( \ 71 FEATURE_DPM_PREFETCHER_MASK | \ 72 FEATURE_DPM_GFXCLK_MASK | \ 73 FEATURE_DPM_UCLK_MASK | \ 74 FEATURE_DPM_SOCCLK_MASK | \ 75 FEATURE_DPM_MP0CLK_MASK | \ 76 FEATURE_DPM_FCLK_MASK | \ 77 FEATURE_DPM_XGMI_MASK) 78 79 /* possible frequency drift (1Mhz) */ 80 #define EPSILON 1 81 82 #define smnPCIE_ESM_CTRL 0x111003D0 83 84 #define mmCG_FDO_CTRL0_ARCT 0x8B 85 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX 0 86 87 #define mmCG_FDO_CTRL1_ARCT 0x8C 88 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX 0 89 90 #define mmCG_FDO_CTRL2_ARCT 0x8D 91 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX 0 92 93 #define mmCG_TACH_CTRL_ARCT 0x8E 94 #define mmCG_TACH_CTRL_ARCT_BASE_IDX 0 95 96 #define mmCG_TACH_STATUS_ARCT 0x8F 97 #define mmCG_TACH_STATUS_ARCT_BASE_IDX 0 98 99 #define mmCG_THERMAL_STATUS_ARCT 0x90 100 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX 0 101 102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = { 103 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), 104 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), 105 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 106 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0), 107 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0), 108 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), 109 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0), 110 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1), 111 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1), 112 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0), 113 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0), 114 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0), 115 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0), 116 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 117 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 118 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0), 119 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0), 120 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 121 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0), 122 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0), 123 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0), 124 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0), 125 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0), 126 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0), 127 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0), 128 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), 129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0), 130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0), 131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0), 132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0), 133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0), 134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0), 135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1), 136 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1), 137 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0), 138 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0), 139 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0), 140 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), 141 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), 142 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0), 143 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0), 144 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0), 145 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0), 146 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), 147 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0), 148 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0), 149 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0), 150 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0), 151 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0), 152 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0), 153 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0), 154 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0), 155 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0), 156 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0), 157 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0), 158 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0), 159 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), 160 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0), 161 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1), 162 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1), 163 MSG_MAP(LightSBR, PPSMC_MSG_LightSBR, 0), 164 }; 165 166 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = { 167 CLK_MAP(GFXCLK, PPCLK_GFXCLK), 168 CLK_MAP(SCLK, PPCLK_GFXCLK), 169 CLK_MAP(SOCCLK, PPCLK_SOCCLK), 170 CLK_MAP(FCLK, PPCLK_FCLK), 171 CLK_MAP(UCLK, PPCLK_UCLK), 172 CLK_MAP(MCLK, PPCLK_UCLK), 173 CLK_MAP(DCLK, PPCLK_DCLK), 174 CLK_MAP(VCLK, PPCLK_VCLK), 175 }; 176 177 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = { 178 FEA_MAP(DPM_PREFETCHER), 179 FEA_MAP(DPM_GFXCLK), 180 FEA_MAP(DPM_UCLK), 181 FEA_MAP(DPM_SOCCLK), 182 FEA_MAP(DPM_FCLK), 183 FEA_MAP(DPM_MP0CLK), 184 FEA_MAP(DPM_XGMI), 185 FEA_MAP(DS_GFXCLK), 186 FEA_MAP(DS_SOCCLK), 187 FEA_MAP(DS_LCLK), 188 FEA_MAP(DS_FCLK), 189 FEA_MAP(DS_UCLK), 190 FEA_MAP(GFX_ULV), 191 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT), 192 FEA_MAP(RSMU_SMN_CG), 193 FEA_MAP(WAFL_CG), 194 FEA_MAP(PPT), 195 FEA_MAP(TDC), 196 FEA_MAP(APCC_PLUS), 197 FEA_MAP(VR0HOT), 198 FEA_MAP(VR1HOT), 199 FEA_MAP(FW_CTF), 200 FEA_MAP(FAN_CONTROL), 201 FEA_MAP(THERMAL), 202 FEA_MAP(OUT_OF_BAND_MONITOR), 203 FEA_MAP(TEMP_DEPENDENT_VMIN), 204 }; 205 206 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = { 207 TAB_MAP(PPTABLE), 208 TAB_MAP(AVFS), 209 TAB_MAP(AVFS_PSM_DEBUG), 210 TAB_MAP(AVFS_FUSE_OVERRIDE), 211 TAB_MAP(PMSTATUSLOG), 212 TAB_MAP(SMU_METRICS), 213 TAB_MAP(DRIVER_SMU_CONFIG), 214 TAB_MAP(OVERDRIVE), 215 TAB_MAP(I2C_COMMANDS), 216 TAB_MAP(ACTIVITY_MONITOR_COEFF), 217 }; 218 219 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = { 220 PWR_MAP(AC), 221 PWR_MAP(DC), 222 }; 223 224 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = { 225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT), 226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), 227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), 228 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), 229 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), 230 }; 231 232 static const uint8_t arcturus_throttler_map[] = { 233 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT), 234 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT), 235 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT), 236 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT), 237 [THROTTLER_TEMP_VR_MEM_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT), 238 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT), 239 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT), 240 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT), 241 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT), 242 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT), 243 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT), 244 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT), 245 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT), 246 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), 247 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT), 248 [THROTTLER_VRHOT0_BIT] = (SMU_THROTTLER_VRHOT0_BIT), 249 [THROTTLER_VRHOT1_BIT] = (SMU_THROTTLER_VRHOT1_BIT), 250 }; 251 252 static int arcturus_tables_init(struct smu_context *smu) 253 { 254 struct smu_table_context *smu_table = &smu->smu_table; 255 struct smu_table *tables = smu_table->tables; 256 257 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), 258 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 259 260 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, 261 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 262 263 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 264 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 265 266 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), 267 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 268 269 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, 270 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, 271 AMDGPU_GEM_DOMAIN_VRAM); 272 273 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 274 if (!smu_table->metrics_table) 275 return -ENOMEM; 276 smu_table->metrics_time = 0; 277 278 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); 279 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 280 if (!smu_table->gpu_metrics_table) { 281 kfree(smu_table->metrics_table); 282 return -ENOMEM; 283 } 284 285 return 0; 286 } 287 288 static int arcturus_allocate_dpm_context(struct smu_context *smu) 289 { 290 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 291 292 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context), 293 GFP_KERNEL); 294 if (!smu_dpm->dpm_context) 295 return -ENOMEM; 296 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context); 297 298 return 0; 299 } 300 301 static int arcturus_init_smc_tables(struct smu_context *smu) 302 { 303 int ret = 0; 304 305 ret = arcturus_tables_init(smu); 306 if (ret) 307 return ret; 308 309 ret = arcturus_allocate_dpm_context(smu); 310 if (ret) 311 return ret; 312 313 return smu_v11_0_init_smc_tables(smu); 314 } 315 316 static int 317 arcturus_get_allowed_feature_mask(struct smu_context *smu, 318 uint32_t *feature_mask, uint32_t num) 319 { 320 if (num > 2) 321 return -EINVAL; 322 323 /* pptable will handle the features to enable */ 324 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 325 326 return 0; 327 } 328 329 static int arcturus_set_default_dpm_table(struct smu_context *smu) 330 { 331 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 332 PPTable_t *driver_ppt = smu->smu_table.driver_pptable; 333 struct smu_11_0_dpm_table *dpm_table = NULL; 334 int ret = 0; 335 336 /* socclk dpm table setup */ 337 dpm_table = &dpm_context->dpm_tables.soc_table; 338 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { 339 ret = smu_v11_0_set_single_dpm_table(smu, 340 SMU_SOCCLK, 341 dpm_table); 342 if (ret) 343 return ret; 344 dpm_table->is_fine_grained = 345 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; 346 } else { 347 dpm_table->count = 1; 348 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; 349 dpm_table->dpm_levels[0].enabled = true; 350 dpm_table->min = dpm_table->dpm_levels[0].value; 351 dpm_table->max = dpm_table->dpm_levels[0].value; 352 } 353 354 /* gfxclk dpm table setup */ 355 dpm_table = &dpm_context->dpm_tables.gfx_table; 356 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { 357 ret = smu_v11_0_set_single_dpm_table(smu, 358 SMU_GFXCLK, 359 dpm_table); 360 if (ret) 361 return ret; 362 dpm_table->is_fine_grained = 363 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; 364 } else { 365 dpm_table->count = 1; 366 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; 367 dpm_table->dpm_levels[0].enabled = true; 368 dpm_table->min = dpm_table->dpm_levels[0].value; 369 dpm_table->max = dpm_table->dpm_levels[0].value; 370 } 371 372 /* memclk dpm table setup */ 373 dpm_table = &dpm_context->dpm_tables.uclk_table; 374 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { 375 ret = smu_v11_0_set_single_dpm_table(smu, 376 SMU_UCLK, 377 dpm_table); 378 if (ret) 379 return ret; 380 dpm_table->is_fine_grained = 381 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; 382 } else { 383 dpm_table->count = 1; 384 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; 385 dpm_table->dpm_levels[0].enabled = true; 386 dpm_table->min = dpm_table->dpm_levels[0].value; 387 dpm_table->max = dpm_table->dpm_levels[0].value; 388 } 389 390 /* fclk dpm table setup */ 391 dpm_table = &dpm_context->dpm_tables.fclk_table; 392 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { 393 ret = smu_v11_0_set_single_dpm_table(smu, 394 SMU_FCLK, 395 dpm_table); 396 if (ret) 397 return ret; 398 dpm_table->is_fine_grained = 399 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; 400 } else { 401 dpm_table->count = 1; 402 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; 403 dpm_table->dpm_levels[0].enabled = true; 404 dpm_table->min = dpm_table->dpm_levels[0].value; 405 dpm_table->max = dpm_table->dpm_levels[0].value; 406 } 407 408 return 0; 409 } 410 411 static void arcturus_check_bxco_support(struct smu_context *smu) 412 { 413 struct smu_table_context *table_context = &smu->smu_table; 414 struct smu_11_0_powerplay_table *powerplay_table = 415 table_context->power_play_table; 416 struct smu_baco_context *smu_baco = &smu->smu_baco; 417 struct amdgpu_device *adev = smu->adev; 418 uint32_t val; 419 420 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO || 421 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) { 422 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0); 423 smu_baco->platform_support = 424 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : 425 false; 426 } 427 } 428 429 static void arcturus_check_fan_support(struct smu_context *smu) 430 { 431 struct smu_table_context *table_context = &smu->smu_table; 432 PPTable_t *pptable = table_context->driver_pptable; 433 434 /* No sort of fan control possible if PPTable has it disabled */ 435 smu->adev->pm.no_fan = 436 !(pptable->FeaturesToRun[0] & FEATURE_FAN_CONTROL_MASK); 437 if (smu->adev->pm.no_fan) 438 dev_info_once(smu->adev->dev, 439 "PMFW based fan control disabled"); 440 } 441 442 static int arcturus_check_powerplay_table(struct smu_context *smu) 443 { 444 struct smu_table_context *table_context = &smu->smu_table; 445 struct smu_11_0_powerplay_table *powerplay_table = 446 table_context->power_play_table; 447 448 arcturus_check_bxco_support(smu); 449 arcturus_check_fan_support(smu); 450 451 table_context->thermal_controller_type = 452 powerplay_table->thermal_controller_type; 453 454 return 0; 455 } 456 457 static int arcturus_store_powerplay_table(struct smu_context *smu) 458 { 459 struct smu_table_context *table_context = &smu->smu_table; 460 struct smu_11_0_powerplay_table *powerplay_table = 461 table_context->power_play_table; 462 463 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable, 464 sizeof(PPTable_t)); 465 466 return 0; 467 } 468 469 static int arcturus_append_powerplay_table(struct smu_context *smu) 470 { 471 struct smu_table_context *table_context = &smu->smu_table; 472 PPTable_t *smc_pptable = table_context->driver_pptable; 473 struct atom_smc_dpm_info_v4_6 *smc_dpm_table; 474 int index, ret; 475 476 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, 477 smc_dpm_info); 478 479 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL, 480 (uint8_t **)&smc_dpm_table); 481 if (ret) 482 return ret; 483 484 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n", 485 smc_dpm_table->table_header.format_revision, 486 smc_dpm_table->table_header.content_revision); 487 488 if ((smc_dpm_table->table_header.format_revision == 4) && 489 (smc_dpm_table->table_header.content_revision == 6)) 490 smu_memcpy_trailing(smc_pptable, MaxVoltageStepGfx, BoardReserved, 491 smc_dpm_table, maxvoltagestepgfx); 492 return 0; 493 } 494 495 static int arcturus_setup_pptable(struct smu_context *smu) 496 { 497 int ret = 0; 498 499 ret = smu_v11_0_setup_pptable(smu); 500 if (ret) 501 return ret; 502 503 ret = arcturus_store_powerplay_table(smu); 504 if (ret) 505 return ret; 506 507 ret = arcturus_append_powerplay_table(smu); 508 if (ret) 509 return ret; 510 511 ret = arcturus_check_powerplay_table(smu); 512 if (ret) 513 return ret; 514 515 return ret; 516 } 517 518 static int arcturus_run_btc(struct smu_context *smu) 519 { 520 int ret = 0; 521 522 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL); 523 if (ret) { 524 dev_err(smu->adev->dev, "RunAfllBtc failed!\n"); 525 return ret; 526 } 527 528 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); 529 } 530 531 static int arcturus_populate_umd_state_clk(struct smu_context *smu) 532 { 533 struct smu_11_0_dpm_context *dpm_context = 534 smu->smu_dpm.dpm_context; 535 struct smu_11_0_dpm_table *gfx_table = 536 &dpm_context->dpm_tables.gfx_table; 537 struct smu_11_0_dpm_table *mem_table = 538 &dpm_context->dpm_tables.uclk_table; 539 struct smu_11_0_dpm_table *soc_table = 540 &dpm_context->dpm_tables.soc_table; 541 struct smu_umd_pstate_table *pstate_table = 542 &smu->pstate_table; 543 544 pstate_table->gfxclk_pstate.min = gfx_table->min; 545 pstate_table->gfxclk_pstate.peak = gfx_table->max; 546 547 pstate_table->uclk_pstate.min = mem_table->min; 548 pstate_table->uclk_pstate.peak = mem_table->max; 549 550 pstate_table->socclk_pstate.min = soc_table->min; 551 pstate_table->socclk_pstate.peak = soc_table->max; 552 553 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL && 554 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && 555 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) { 556 pstate_table->gfxclk_pstate.standard = 557 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value; 558 pstate_table->uclk_pstate.standard = 559 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value; 560 pstate_table->socclk_pstate.standard = 561 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value; 562 } else { 563 pstate_table->gfxclk_pstate.standard = 564 pstate_table->gfxclk_pstate.min; 565 pstate_table->uclk_pstate.standard = 566 pstate_table->uclk_pstate.min; 567 pstate_table->socclk_pstate.standard = 568 pstate_table->socclk_pstate.min; 569 } 570 571 return 0; 572 } 573 574 static int arcturus_get_clk_table(struct smu_context *smu, 575 struct pp_clock_levels_with_latency *clocks, 576 struct smu_11_0_dpm_table *dpm_table) 577 { 578 int i, count; 579 580 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 581 clocks->num_levels = count; 582 583 for (i = 0; i < count; i++) { 584 clocks->data[i].clocks_in_khz = 585 dpm_table->dpm_levels[i].value * 1000; 586 clocks->data[i].latency_in_us = 0; 587 } 588 589 return 0; 590 } 591 592 static int arcturus_freqs_in_same_level(int32_t frequency1, 593 int32_t frequency2) 594 { 595 return (abs(frequency1 - frequency2) <= EPSILON); 596 } 597 598 static int arcturus_get_smu_metrics_data(struct smu_context *smu, 599 MetricsMember_t member, 600 uint32_t *value) 601 { 602 struct smu_table_context *smu_table= &smu->smu_table; 603 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 604 int ret = 0; 605 606 mutex_lock(&smu->metrics_lock); 607 608 ret = smu_cmn_get_metrics_table_locked(smu, 609 NULL, 610 false); 611 if (ret) { 612 mutex_unlock(&smu->metrics_lock); 613 return ret; 614 } 615 616 switch (member) { 617 case METRICS_CURR_GFXCLK: 618 *value = metrics->CurrClock[PPCLK_GFXCLK]; 619 break; 620 case METRICS_CURR_SOCCLK: 621 *value = metrics->CurrClock[PPCLK_SOCCLK]; 622 break; 623 case METRICS_CURR_UCLK: 624 *value = metrics->CurrClock[PPCLK_UCLK]; 625 break; 626 case METRICS_CURR_VCLK: 627 *value = metrics->CurrClock[PPCLK_VCLK]; 628 break; 629 case METRICS_CURR_DCLK: 630 *value = metrics->CurrClock[PPCLK_DCLK]; 631 break; 632 case METRICS_CURR_FCLK: 633 *value = metrics->CurrClock[PPCLK_FCLK]; 634 break; 635 case METRICS_AVERAGE_GFXCLK: 636 *value = metrics->AverageGfxclkFrequency; 637 break; 638 case METRICS_AVERAGE_SOCCLK: 639 *value = metrics->AverageSocclkFrequency; 640 break; 641 case METRICS_AVERAGE_UCLK: 642 *value = metrics->AverageUclkFrequency; 643 break; 644 case METRICS_AVERAGE_VCLK: 645 *value = metrics->AverageVclkFrequency; 646 break; 647 case METRICS_AVERAGE_DCLK: 648 *value = metrics->AverageDclkFrequency; 649 break; 650 case METRICS_AVERAGE_GFXACTIVITY: 651 *value = metrics->AverageGfxActivity; 652 break; 653 case METRICS_AVERAGE_MEMACTIVITY: 654 *value = metrics->AverageUclkActivity; 655 break; 656 case METRICS_AVERAGE_VCNACTIVITY: 657 *value = metrics->VcnActivityPercentage; 658 break; 659 case METRICS_AVERAGE_SOCKETPOWER: 660 *value = metrics->AverageSocketPower << 8; 661 break; 662 case METRICS_TEMPERATURE_EDGE: 663 *value = metrics->TemperatureEdge * 664 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 665 break; 666 case METRICS_TEMPERATURE_HOTSPOT: 667 *value = metrics->TemperatureHotspot * 668 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 669 break; 670 case METRICS_TEMPERATURE_MEM: 671 *value = metrics->TemperatureHBM * 672 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 673 break; 674 case METRICS_TEMPERATURE_VRGFX: 675 *value = metrics->TemperatureVrGfx * 676 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 677 break; 678 case METRICS_TEMPERATURE_VRSOC: 679 *value = metrics->TemperatureVrSoc * 680 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 681 break; 682 case METRICS_TEMPERATURE_VRMEM: 683 *value = metrics->TemperatureVrMem * 684 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 685 break; 686 case METRICS_THROTTLER_STATUS: 687 *value = metrics->ThrottlerStatus; 688 break; 689 case METRICS_CURR_FANSPEED: 690 *value = metrics->CurrFanSpeed; 691 break; 692 default: 693 *value = UINT_MAX; 694 break; 695 } 696 697 mutex_unlock(&smu->metrics_lock); 698 699 return ret; 700 } 701 702 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu, 703 enum smu_clk_type clk_type, 704 uint32_t *value) 705 { 706 MetricsMember_t member_type; 707 int clk_id = 0; 708 709 if (!value) 710 return -EINVAL; 711 712 clk_id = smu_cmn_to_asic_specific_index(smu, 713 CMN2ASIC_MAPPING_CLK, 714 clk_type); 715 if (clk_id < 0) 716 return -EINVAL; 717 718 switch (clk_id) { 719 case PPCLK_GFXCLK: 720 /* 721 * CurrClock[clk_id] can provide accurate 722 * output only when the dpm feature is enabled. 723 * We can use Average_* for dpm disabled case. 724 * But this is available for gfxclk/uclk/socclk/vclk/dclk. 725 */ 726 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) 727 member_type = METRICS_CURR_GFXCLK; 728 else 729 member_type = METRICS_AVERAGE_GFXCLK; 730 break; 731 case PPCLK_UCLK: 732 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) 733 member_type = METRICS_CURR_UCLK; 734 else 735 member_type = METRICS_AVERAGE_UCLK; 736 break; 737 case PPCLK_SOCCLK: 738 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) 739 member_type = METRICS_CURR_SOCCLK; 740 else 741 member_type = METRICS_AVERAGE_SOCCLK; 742 break; 743 case PPCLK_VCLK: 744 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) 745 member_type = METRICS_CURR_VCLK; 746 else 747 member_type = METRICS_AVERAGE_VCLK; 748 break; 749 case PPCLK_DCLK: 750 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) 751 member_type = METRICS_CURR_DCLK; 752 else 753 member_type = METRICS_AVERAGE_DCLK; 754 break; 755 case PPCLK_FCLK: 756 member_type = METRICS_CURR_FCLK; 757 break; 758 default: 759 return -EINVAL; 760 } 761 762 return arcturus_get_smu_metrics_data(smu, 763 member_type, 764 value); 765 } 766 767 static int arcturus_print_clk_levels(struct smu_context *smu, 768 enum smu_clk_type type, char *buf) 769 { 770 int i, now, size = 0; 771 int ret = 0; 772 struct pp_clock_levels_with_latency clocks; 773 struct smu_11_0_dpm_table *single_dpm_table; 774 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 775 struct smu_11_0_dpm_context *dpm_context = NULL; 776 uint32_t gen_speed, lane_width; 777 778 smu_cmn_get_sysfs_buf(&buf, &size); 779 780 if (amdgpu_ras_intr_triggered()) { 781 size += sysfs_emit_at(buf, size, "unavailable\n"); 782 return size; 783 } 784 785 dpm_context = smu_dpm->dpm_context; 786 787 switch (type) { 788 case SMU_SCLK: 789 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now); 790 if (ret) { 791 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!"); 792 return ret; 793 } 794 795 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 796 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 797 if (ret) { 798 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!"); 799 return ret; 800 } 801 802 /* 803 * For DPM disabled case, there will be only one clock level. 804 * And it's safe to assume that is always the current clock. 805 */ 806 for (i = 0; i < clocks.num_levels; i++) 807 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 808 clocks.data[i].clocks_in_khz / 1000, 809 (clocks.num_levels == 1) ? "*" : 810 (arcturus_freqs_in_same_level( 811 clocks.data[i].clocks_in_khz / 1000, 812 now) ? "*" : "")); 813 break; 814 815 case SMU_MCLK: 816 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now); 817 if (ret) { 818 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!"); 819 return ret; 820 } 821 822 single_dpm_table = &(dpm_context->dpm_tables.uclk_table); 823 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 824 if (ret) { 825 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!"); 826 return ret; 827 } 828 829 for (i = 0; i < clocks.num_levels; i++) 830 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 831 i, clocks.data[i].clocks_in_khz / 1000, 832 (clocks.num_levels == 1) ? "*" : 833 (arcturus_freqs_in_same_level( 834 clocks.data[i].clocks_in_khz / 1000, 835 now) ? "*" : "")); 836 break; 837 838 case SMU_SOCCLK: 839 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now); 840 if (ret) { 841 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!"); 842 return ret; 843 } 844 845 single_dpm_table = &(dpm_context->dpm_tables.soc_table); 846 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 847 if (ret) { 848 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!"); 849 return ret; 850 } 851 852 for (i = 0; i < clocks.num_levels; i++) 853 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 854 i, clocks.data[i].clocks_in_khz / 1000, 855 (clocks.num_levels == 1) ? "*" : 856 (arcturus_freqs_in_same_level( 857 clocks.data[i].clocks_in_khz / 1000, 858 now) ? "*" : "")); 859 break; 860 861 case SMU_FCLK: 862 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now); 863 if (ret) { 864 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!"); 865 return ret; 866 } 867 868 single_dpm_table = &(dpm_context->dpm_tables.fclk_table); 869 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 870 if (ret) { 871 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!"); 872 return ret; 873 } 874 875 for (i = 0; i < single_dpm_table->count; i++) 876 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 877 i, single_dpm_table->dpm_levels[i].value, 878 (clocks.num_levels == 1) ? "*" : 879 (arcturus_freqs_in_same_level( 880 clocks.data[i].clocks_in_khz / 1000, 881 now) ? "*" : "")); 882 break; 883 884 case SMU_VCLK: 885 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now); 886 if (ret) { 887 dev_err(smu->adev->dev, "Attempt to get current vclk Failed!"); 888 return ret; 889 } 890 891 single_dpm_table = &(dpm_context->dpm_tables.vclk_table); 892 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 893 if (ret) { 894 dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!"); 895 return ret; 896 } 897 898 for (i = 0; i < single_dpm_table->count; i++) 899 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 900 i, single_dpm_table->dpm_levels[i].value, 901 (clocks.num_levels == 1) ? "*" : 902 (arcturus_freqs_in_same_level( 903 clocks.data[i].clocks_in_khz / 1000, 904 now) ? "*" : "")); 905 break; 906 907 case SMU_DCLK: 908 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now); 909 if (ret) { 910 dev_err(smu->adev->dev, "Attempt to get current dclk Failed!"); 911 return ret; 912 } 913 914 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); 915 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table); 916 if (ret) { 917 dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!"); 918 return ret; 919 } 920 921 for (i = 0; i < single_dpm_table->count; i++) 922 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", 923 i, single_dpm_table->dpm_levels[i].value, 924 (clocks.num_levels == 1) ? "*" : 925 (arcturus_freqs_in_same_level( 926 clocks.data[i].clocks_in_khz / 1000, 927 now) ? "*" : "")); 928 break; 929 930 case SMU_PCIE: 931 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); 932 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); 933 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n", 934 (gen_speed == 0) ? "2.5GT/s," : 935 (gen_speed == 1) ? "5.0GT/s," : 936 (gen_speed == 2) ? "8.0GT/s," : 937 (gen_speed == 3) ? "16.0GT/s," : "", 938 (lane_width == 1) ? "x1" : 939 (lane_width == 2) ? "x2" : 940 (lane_width == 3) ? "x4" : 941 (lane_width == 4) ? "x8" : 942 (lane_width == 5) ? "x12" : 943 (lane_width == 6) ? "x16" : "", 944 smu->smu_table.boot_values.lclk / 100); 945 break; 946 947 default: 948 break; 949 } 950 951 return size; 952 } 953 954 static int arcturus_upload_dpm_level(struct smu_context *smu, 955 bool max, 956 uint32_t feature_mask, 957 uint32_t level) 958 { 959 struct smu_11_0_dpm_context *dpm_context = 960 smu->smu_dpm.dpm_context; 961 uint32_t freq; 962 int ret = 0; 963 964 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) && 965 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 966 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value; 967 ret = smu_cmn_send_smc_msg_with_param(smu, 968 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 969 (PPCLK_GFXCLK << 16) | (freq & 0xffff), 970 NULL); 971 if (ret) { 972 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n", 973 max ? "max" : "min"); 974 return ret; 975 } 976 } 977 978 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && 979 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 980 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value; 981 ret = smu_cmn_send_smc_msg_with_param(smu, 982 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 983 (PPCLK_UCLK << 16) | (freq & 0xffff), 984 NULL); 985 if (ret) { 986 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n", 987 max ? "max" : "min"); 988 return ret; 989 } 990 } 991 992 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) && 993 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 994 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value; 995 ret = smu_cmn_send_smc_msg_with_param(smu, 996 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq), 997 (PPCLK_SOCCLK << 16) | (freq & 0xffff), 998 NULL); 999 if (ret) { 1000 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n", 1001 max ? "max" : "min"); 1002 return ret; 1003 } 1004 } 1005 1006 return ret; 1007 } 1008 1009 static int arcturus_force_clk_levels(struct smu_context *smu, 1010 enum smu_clk_type type, uint32_t mask) 1011 { 1012 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; 1013 struct smu_11_0_dpm_table *single_dpm_table = NULL; 1014 uint32_t soft_min_level, soft_max_level; 1015 uint32_t smu_version; 1016 int ret = 0; 1017 1018 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1019 if (ret) { 1020 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 1021 return ret; 1022 } 1023 1024 if ((smu_version >= 0x361200) && 1025 (smu_version <= 0x361a00)) { 1026 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 1027 "54.18 - 54.26(included) SMU firmwares\n"); 1028 return -EOPNOTSUPP; 1029 } 1030 1031 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1032 soft_max_level = mask ? (fls(mask) - 1) : 0; 1033 1034 switch (type) { 1035 case SMU_SCLK: 1036 single_dpm_table = &(dpm_context->dpm_tables.gfx_table); 1037 if (soft_max_level >= single_dpm_table->count) { 1038 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n", 1039 soft_max_level, single_dpm_table->count - 1); 1040 ret = -EINVAL; 1041 break; 1042 } 1043 1044 ret = arcturus_upload_dpm_level(smu, 1045 false, 1046 FEATURE_DPM_GFXCLK_MASK, 1047 soft_min_level); 1048 if (ret) { 1049 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n"); 1050 break; 1051 } 1052 1053 ret = arcturus_upload_dpm_level(smu, 1054 true, 1055 FEATURE_DPM_GFXCLK_MASK, 1056 soft_max_level); 1057 if (ret) 1058 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n"); 1059 1060 break; 1061 1062 case SMU_MCLK: 1063 case SMU_SOCCLK: 1064 case SMU_FCLK: 1065 /* 1066 * Should not arrive here since Arcturus does not 1067 * support mclk/socclk/fclk softmin/softmax settings 1068 */ 1069 ret = -EINVAL; 1070 break; 1071 1072 default: 1073 break; 1074 } 1075 1076 return ret; 1077 } 1078 1079 static int arcturus_get_thermal_temperature_range(struct smu_context *smu, 1080 struct smu_temperature_range *range) 1081 { 1082 struct smu_table_context *table_context = &smu->smu_table; 1083 struct smu_11_0_powerplay_table *powerplay_table = 1084 table_context->power_play_table; 1085 PPTable_t *pptable = smu->smu_table.driver_pptable; 1086 1087 if (!range) 1088 return -EINVAL; 1089 1090 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range)); 1091 1092 range->max = pptable->TedgeLimit * 1093 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1094 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * 1095 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1096 range->hotspot_crit_max = pptable->ThotspotLimit * 1097 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1098 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 1099 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1100 range->mem_crit_max = pptable->TmemLimit * 1101 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1102 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)* 1103 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 1104 range->software_shutdown_temp = powerplay_table->software_shutdown_temp; 1105 1106 return 0; 1107 } 1108 1109 static int arcturus_read_sensor(struct smu_context *smu, 1110 enum amd_pp_sensors sensor, 1111 void *data, uint32_t *size) 1112 { 1113 struct smu_table_context *table_context = &smu->smu_table; 1114 PPTable_t *pptable = table_context->driver_pptable; 1115 int ret = 0; 1116 1117 if (amdgpu_ras_intr_triggered()) 1118 return 0; 1119 1120 if (!data || !size) 1121 return -EINVAL; 1122 1123 mutex_lock(&smu->sensor_lock); 1124 switch (sensor) { 1125 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 1126 *(uint32_t *)data = pptable->FanMaximumRpm; 1127 *size = 4; 1128 break; 1129 case AMDGPU_PP_SENSOR_MEM_LOAD: 1130 ret = arcturus_get_smu_metrics_data(smu, 1131 METRICS_AVERAGE_MEMACTIVITY, 1132 (uint32_t *)data); 1133 *size = 4; 1134 break; 1135 case AMDGPU_PP_SENSOR_GPU_LOAD: 1136 ret = arcturus_get_smu_metrics_data(smu, 1137 METRICS_AVERAGE_GFXACTIVITY, 1138 (uint32_t *)data); 1139 *size = 4; 1140 break; 1141 case AMDGPU_PP_SENSOR_GPU_POWER: 1142 ret = arcturus_get_smu_metrics_data(smu, 1143 METRICS_AVERAGE_SOCKETPOWER, 1144 (uint32_t *)data); 1145 *size = 4; 1146 break; 1147 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1148 ret = arcturus_get_smu_metrics_data(smu, 1149 METRICS_TEMPERATURE_HOTSPOT, 1150 (uint32_t *)data); 1151 *size = 4; 1152 break; 1153 case AMDGPU_PP_SENSOR_EDGE_TEMP: 1154 ret = arcturus_get_smu_metrics_data(smu, 1155 METRICS_TEMPERATURE_EDGE, 1156 (uint32_t *)data); 1157 *size = 4; 1158 break; 1159 case AMDGPU_PP_SENSOR_MEM_TEMP: 1160 ret = arcturus_get_smu_metrics_data(smu, 1161 METRICS_TEMPERATURE_MEM, 1162 (uint32_t *)data); 1163 *size = 4; 1164 break; 1165 case AMDGPU_PP_SENSOR_GFX_MCLK: 1166 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data); 1167 /* the output clock frequency in 10K unit */ 1168 *(uint32_t *)data *= 100; 1169 *size = 4; 1170 break; 1171 case AMDGPU_PP_SENSOR_GFX_SCLK: 1172 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data); 1173 *(uint32_t *)data *= 100; 1174 *size = 4; 1175 break; 1176 case AMDGPU_PP_SENSOR_VDDGFX: 1177 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data); 1178 *size = 4; 1179 break; 1180 default: 1181 ret = -EOPNOTSUPP; 1182 break; 1183 } 1184 mutex_unlock(&smu->sensor_lock); 1185 1186 return ret; 1187 } 1188 1189 static int arcturus_set_fan_static_mode(struct smu_context *smu, 1190 uint32_t mode) 1191 { 1192 struct amdgpu_device *adev = smu->adev; 1193 1194 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1195 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1196 CG_FDO_CTRL2, TMIN, 0)); 1197 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT, 1198 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT), 1199 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 1200 1201 return 0; 1202 } 1203 1204 static int arcturus_get_fan_speed_rpm(struct smu_context *smu, 1205 uint32_t *speed) 1206 { 1207 struct amdgpu_device *adev = smu->adev; 1208 uint32_t crystal_clock_freq = 2500; 1209 uint32_t tach_status; 1210 uint64_t tmp64; 1211 int ret = 0; 1212 1213 if (!speed) 1214 return -EINVAL; 1215 1216 switch (smu_v11_0_get_fan_control_mode(smu)) { 1217 case AMD_FAN_CTRL_AUTO: 1218 ret = arcturus_get_smu_metrics_data(smu, 1219 METRICS_CURR_FANSPEED, 1220 speed); 1221 break; 1222 default: 1223 /* 1224 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1225 * detected via register retrieving. To workaround this, we will 1226 * report the fan speed as 0 RPM if user just requested such. 1227 */ 1228 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM) 1229 && !smu->user_dpm_profile.fan_speed_rpm) { 1230 *speed = 0; 1231 return 0; 1232 } 1233 1234 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; 1235 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT); 1236 if (tach_status) { 1237 do_div(tmp64, tach_status); 1238 *speed = (uint32_t)tmp64; 1239 } else { 1240 *speed = 0; 1241 } 1242 1243 break; 1244 } 1245 1246 return ret; 1247 } 1248 1249 static int arcturus_set_fan_speed_pwm(struct smu_context *smu, 1250 uint32_t speed) 1251 { 1252 struct amdgpu_device *adev = smu->adev; 1253 uint32_t duty100, duty; 1254 uint64_t tmp64; 1255 1256 speed = MIN(speed, 255); 1257 1258 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1259 CG_FDO_CTRL1, FMAX_DUTY100); 1260 if (!duty100) 1261 return -EINVAL; 1262 1263 tmp64 = (uint64_t)speed * duty100; 1264 do_div(tmp64, 255); 1265 duty = (uint32_t)tmp64; 1266 1267 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT, 1268 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT), 1269 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 1270 1271 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC); 1272 } 1273 1274 static int arcturus_set_fan_speed_rpm(struct smu_context *smu, 1275 uint32_t speed) 1276 { 1277 struct amdgpu_device *adev = smu->adev; 1278 /* 1279 * crystal_clock_freq used for fan speed rpm calculation is 1280 * always 25Mhz. So, hardcode it as 2500(in 10K unit). 1281 */ 1282 uint32_t crystal_clock_freq = 2500; 1283 uint32_t tach_period; 1284 1285 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 1286 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT, 1287 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT), 1288 CG_TACH_CTRL, TARGET_PERIOD, 1289 tach_period)); 1290 1291 return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM); 1292 } 1293 1294 static int arcturus_get_fan_speed_pwm(struct smu_context *smu, 1295 uint32_t *speed) 1296 { 1297 struct amdgpu_device *adev = smu->adev; 1298 uint32_t duty100, duty; 1299 uint64_t tmp64; 1300 1301 /* 1302 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly 1303 * detected via register retrieving. To workaround this, we will 1304 * report the fan speed as 0 PWM if user just requested such. 1305 */ 1306 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM) 1307 && !smu->user_dpm_profile.fan_speed_pwm) { 1308 *speed = 0; 1309 return 0; 1310 } 1311 1312 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT), 1313 CG_FDO_CTRL1, FMAX_DUTY100); 1314 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT), 1315 CG_THERMAL_STATUS, FDO_PWM_DUTY); 1316 1317 if (duty100) { 1318 tmp64 = (uint64_t)duty * 255; 1319 do_div(tmp64, duty100); 1320 *speed = MIN((uint32_t)tmp64, 255); 1321 } else { 1322 *speed = 0; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static int arcturus_get_fan_parameters(struct smu_context *smu) 1329 { 1330 PPTable_t *pptable = smu->smu_table.driver_pptable; 1331 1332 smu->fan_max_rpm = pptable->FanMaximumRpm; 1333 1334 return 0; 1335 } 1336 1337 static int arcturus_get_power_limit(struct smu_context *smu, 1338 uint32_t *current_power_limit, 1339 uint32_t *default_power_limit, 1340 uint32_t *max_power_limit) 1341 { 1342 struct smu_11_0_powerplay_table *powerplay_table = 1343 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table; 1344 PPTable_t *pptable = smu->smu_table.driver_pptable; 1345 uint32_t power_limit, od_percent; 1346 1347 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) { 1348 /* the last hope to figure out the ppt limit */ 1349 if (!pptable) { 1350 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!"); 1351 return -EINVAL; 1352 } 1353 power_limit = 1354 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; 1355 } 1356 1357 if (current_power_limit) 1358 *current_power_limit = power_limit; 1359 if (default_power_limit) 1360 *default_power_limit = power_limit; 1361 1362 if (max_power_limit) { 1363 if (smu->od_enabled) { 1364 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]); 1365 1366 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit); 1367 1368 power_limit *= (100 + od_percent); 1369 power_limit /= 100; 1370 } 1371 1372 *max_power_limit = power_limit; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int arcturus_get_power_profile_mode(struct smu_context *smu, 1379 char *buf) 1380 { 1381 DpmActivityMonitorCoeffInt_t activity_monitor; 1382 static const char *title[] = { 1383 "PROFILE_INDEX(NAME)", 1384 "CLOCK_TYPE(NAME)", 1385 "FPS", 1386 "UseRlcBusy", 1387 "MinActiveFreqType", 1388 "MinActiveFreq", 1389 "BoosterFreqType", 1390 "BoosterFreq", 1391 "PD_Data_limit_c", 1392 "PD_Data_error_coeff", 1393 "PD_Data_error_rate_coeff"}; 1394 uint32_t i, size = 0; 1395 int16_t workload_type = 0; 1396 int result = 0; 1397 uint32_t smu_version; 1398 1399 if (!buf) 1400 return -EINVAL; 1401 1402 result = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1403 if (result) 1404 return result; 1405 1406 if (smu_version >= 0x360d00) 1407 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 1408 title[0], title[1], title[2], title[3], title[4], title[5], 1409 title[6], title[7], title[8], title[9], title[10]); 1410 else 1411 size += sysfs_emit_at(buf, size, "%16s\n", 1412 title[0]); 1413 1414 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 1415 /* 1416 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1417 * Not all profile modes are supported on arcturus. 1418 */ 1419 workload_type = smu_cmn_to_asic_specific_index(smu, 1420 CMN2ASIC_MAPPING_WORKLOAD, 1421 i); 1422 if (workload_type < 0) 1423 continue; 1424 1425 if (smu_version >= 0x360d00) { 1426 result = smu_cmn_update_table(smu, 1427 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1428 workload_type, 1429 (void *)(&activity_monitor), 1430 false); 1431 if (result) { 1432 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1433 return result; 1434 } 1435 } 1436 1437 size += sysfs_emit_at(buf, size, "%2d %14s%s\n", 1438 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " "); 1439 1440 if (smu_version >= 0x360d00) { 1441 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1442 " ", 1443 0, 1444 "GFXCLK", 1445 activity_monitor.Gfx_FPS, 1446 activity_monitor.Gfx_UseRlcBusy, 1447 activity_monitor.Gfx_MinActiveFreqType, 1448 activity_monitor.Gfx_MinActiveFreq, 1449 activity_monitor.Gfx_BoosterFreqType, 1450 activity_monitor.Gfx_BoosterFreq, 1451 activity_monitor.Gfx_PD_Data_limit_c, 1452 activity_monitor.Gfx_PD_Data_error_coeff, 1453 activity_monitor.Gfx_PD_Data_error_rate_coeff); 1454 1455 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 1456 " ", 1457 1, 1458 "UCLK", 1459 activity_monitor.Mem_FPS, 1460 activity_monitor.Mem_UseRlcBusy, 1461 activity_monitor.Mem_MinActiveFreqType, 1462 activity_monitor.Mem_MinActiveFreq, 1463 activity_monitor.Mem_BoosterFreqType, 1464 activity_monitor.Mem_BoosterFreq, 1465 activity_monitor.Mem_PD_Data_limit_c, 1466 activity_monitor.Mem_PD_Data_error_coeff, 1467 activity_monitor.Mem_PD_Data_error_rate_coeff); 1468 } 1469 } 1470 1471 return size; 1472 } 1473 1474 static int arcturus_set_power_profile_mode(struct smu_context *smu, 1475 long *input, 1476 uint32_t size) 1477 { 1478 DpmActivityMonitorCoeffInt_t activity_monitor; 1479 int workload_type = 0; 1480 uint32_t profile_mode = input[size]; 1481 int ret = 0; 1482 uint32_t smu_version; 1483 1484 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 1485 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode); 1486 return -EINVAL; 1487 } 1488 1489 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1490 if (ret) 1491 return ret; 1492 1493 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) && 1494 (smu_version >=0x360d00)) { 1495 ret = smu_cmn_update_table(smu, 1496 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1497 WORKLOAD_PPLIB_CUSTOM_BIT, 1498 (void *)(&activity_monitor), 1499 false); 1500 if (ret) { 1501 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); 1502 return ret; 1503 } 1504 1505 switch (input[0]) { 1506 case 0: /* Gfxclk */ 1507 activity_monitor.Gfx_FPS = input[1]; 1508 activity_monitor.Gfx_UseRlcBusy = input[2]; 1509 activity_monitor.Gfx_MinActiveFreqType = input[3]; 1510 activity_monitor.Gfx_MinActiveFreq = input[4]; 1511 activity_monitor.Gfx_BoosterFreqType = input[5]; 1512 activity_monitor.Gfx_BoosterFreq = input[6]; 1513 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 1514 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 1515 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 1516 break; 1517 case 1: /* Uclk */ 1518 activity_monitor.Mem_FPS = input[1]; 1519 activity_monitor.Mem_UseRlcBusy = input[2]; 1520 activity_monitor.Mem_MinActiveFreqType = input[3]; 1521 activity_monitor.Mem_MinActiveFreq = input[4]; 1522 activity_monitor.Mem_BoosterFreqType = input[5]; 1523 activity_monitor.Mem_BoosterFreq = input[6]; 1524 activity_monitor.Mem_PD_Data_limit_c = input[7]; 1525 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 1526 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 1527 break; 1528 } 1529 1530 ret = smu_cmn_update_table(smu, 1531 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 1532 WORKLOAD_PPLIB_CUSTOM_BIT, 1533 (void *)(&activity_monitor), 1534 true); 1535 if (ret) { 1536 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); 1537 return ret; 1538 } 1539 } 1540 1541 /* 1542 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT 1543 * Not all profile modes are supported on arcturus. 1544 */ 1545 workload_type = smu_cmn_to_asic_specific_index(smu, 1546 CMN2ASIC_MAPPING_WORKLOAD, 1547 profile_mode); 1548 if (workload_type < 0) { 1549 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode); 1550 return -EINVAL; 1551 } 1552 1553 ret = smu_cmn_send_smc_msg_with_param(smu, 1554 SMU_MSG_SetWorkloadMask, 1555 1 << workload_type, 1556 NULL); 1557 if (ret) { 1558 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type); 1559 return ret; 1560 } 1561 1562 smu->power_profile_mode = profile_mode; 1563 1564 return 0; 1565 } 1566 1567 static int arcturus_set_performance_level(struct smu_context *smu, 1568 enum amd_dpm_forced_level level) 1569 { 1570 uint32_t smu_version; 1571 int ret; 1572 1573 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 1574 if (ret) { 1575 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 1576 return ret; 1577 } 1578 1579 switch (level) { 1580 case AMD_DPM_FORCED_LEVEL_HIGH: 1581 case AMD_DPM_FORCED_LEVEL_LOW: 1582 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1583 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1584 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1585 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1586 if ((smu_version >= 0x361200) && 1587 (smu_version <= 0x361a00)) { 1588 dev_err(smu->adev->dev, "Forcing clock level is not supported with " 1589 "54.18 - 54.26(included) SMU firmwares\n"); 1590 return -EOPNOTSUPP; 1591 } 1592 break; 1593 default: 1594 break; 1595 } 1596 1597 return smu_v11_0_set_performance_level(smu, level); 1598 } 1599 1600 static void arcturus_dump_pptable(struct smu_context *smu) 1601 { 1602 struct smu_table_context *table_context = &smu->smu_table; 1603 PPTable_t *pptable = table_context->driver_pptable; 1604 int i; 1605 1606 dev_info(smu->adev->dev, "Dumped PPTable:\n"); 1607 1608 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version); 1609 1610 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]); 1611 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]); 1612 1613 for (i = 0; i < PPT_THROTTLER_COUNT; i++) { 1614 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]); 1615 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]); 1616 } 1617 1618 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc); 1619 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau); 1620 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx); 1621 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau); 1622 1623 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit); 1624 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit); 1625 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit); 1626 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit); 1627 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit); 1628 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit); 1629 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit); 1630 1631 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit); 1632 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); 1633 1634 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask); 1635 1636 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); 1637 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding); 1638 1639 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass); 1640 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]); 1641 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]); 1642 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]); 1643 1644 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx); 1645 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc); 1646 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx); 1647 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc); 1648 1649 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx); 1650 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc); 1651 1652 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n" 1653 " .VoltageMode = 0x%02x\n" 1654 " .SnapToDiscrete = 0x%02x\n" 1655 " .NumDiscreteLevels = 0x%02x\n" 1656 " .padding = 0x%02x\n" 1657 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1658 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1659 " .SsFmin = 0x%04x\n" 1660 " .Padding_16 = 0x%04x\n", 1661 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode, 1662 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete, 1663 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels, 1664 pptable->DpmDescriptor[PPCLK_GFXCLK].padding, 1665 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m, 1666 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b, 1667 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a, 1668 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b, 1669 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c, 1670 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin, 1671 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16); 1672 1673 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n" 1674 " .VoltageMode = 0x%02x\n" 1675 " .SnapToDiscrete = 0x%02x\n" 1676 " .NumDiscreteLevels = 0x%02x\n" 1677 " .padding = 0x%02x\n" 1678 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1679 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1680 " .SsFmin = 0x%04x\n" 1681 " .Padding_16 = 0x%04x\n", 1682 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode, 1683 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete, 1684 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels, 1685 pptable->DpmDescriptor[PPCLK_VCLK].padding, 1686 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m, 1687 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b, 1688 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a, 1689 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b, 1690 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c, 1691 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin, 1692 pptable->DpmDescriptor[PPCLK_VCLK].Padding16); 1693 1694 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n" 1695 " .VoltageMode = 0x%02x\n" 1696 " .SnapToDiscrete = 0x%02x\n" 1697 " .NumDiscreteLevels = 0x%02x\n" 1698 " .padding = 0x%02x\n" 1699 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1700 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1701 " .SsFmin = 0x%04x\n" 1702 " .Padding_16 = 0x%04x\n", 1703 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode, 1704 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete, 1705 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels, 1706 pptable->DpmDescriptor[PPCLK_DCLK].padding, 1707 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m, 1708 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b, 1709 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a, 1710 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b, 1711 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c, 1712 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin, 1713 pptable->DpmDescriptor[PPCLK_DCLK].Padding16); 1714 1715 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n" 1716 " .VoltageMode = 0x%02x\n" 1717 " .SnapToDiscrete = 0x%02x\n" 1718 " .NumDiscreteLevels = 0x%02x\n" 1719 " .padding = 0x%02x\n" 1720 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1721 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1722 " .SsFmin = 0x%04x\n" 1723 " .Padding_16 = 0x%04x\n", 1724 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode, 1725 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete, 1726 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels, 1727 pptable->DpmDescriptor[PPCLK_SOCCLK].padding, 1728 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m, 1729 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b, 1730 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a, 1731 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b, 1732 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c, 1733 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin, 1734 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16); 1735 1736 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n" 1737 " .VoltageMode = 0x%02x\n" 1738 " .SnapToDiscrete = 0x%02x\n" 1739 " .NumDiscreteLevels = 0x%02x\n" 1740 " .padding = 0x%02x\n" 1741 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1742 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1743 " .SsFmin = 0x%04x\n" 1744 " .Padding_16 = 0x%04x\n", 1745 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode, 1746 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete, 1747 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels, 1748 pptable->DpmDescriptor[PPCLK_UCLK].padding, 1749 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m, 1750 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b, 1751 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a, 1752 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b, 1753 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c, 1754 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin, 1755 pptable->DpmDescriptor[PPCLK_UCLK].Padding16); 1756 1757 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n" 1758 " .VoltageMode = 0x%02x\n" 1759 " .SnapToDiscrete = 0x%02x\n" 1760 " .NumDiscreteLevels = 0x%02x\n" 1761 " .padding = 0x%02x\n" 1762 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n" 1763 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n" 1764 " .SsFmin = 0x%04x\n" 1765 " .Padding_16 = 0x%04x\n", 1766 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode, 1767 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete, 1768 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels, 1769 pptable->DpmDescriptor[PPCLK_FCLK].padding, 1770 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m, 1771 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b, 1772 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a, 1773 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b, 1774 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c, 1775 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin, 1776 pptable->DpmDescriptor[PPCLK_FCLK].Padding16); 1777 1778 1779 dev_info(smu->adev->dev, "FreqTableGfx\n"); 1780 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) 1781 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i]); 1782 1783 dev_info(smu->adev->dev, "FreqTableVclk\n"); 1784 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++) 1785 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i]); 1786 1787 dev_info(smu->adev->dev, "FreqTableDclk\n"); 1788 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++) 1789 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i]); 1790 1791 dev_info(smu->adev->dev, "FreqTableSocclk\n"); 1792 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) 1793 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]); 1794 1795 dev_info(smu->adev->dev, "FreqTableUclk\n"); 1796 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) 1797 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i]); 1798 1799 dev_info(smu->adev->dev, "FreqTableFclk\n"); 1800 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) 1801 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i]); 1802 1803 dev_info(smu->adev->dev, "Mp0clkFreq\n"); 1804 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1805 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i]); 1806 1807 dev_info(smu->adev->dev, "Mp0DpmVoltage\n"); 1808 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++) 1809 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]); 1810 1811 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle); 1812 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate); 1813 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]); 1814 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]); 1815 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]); 1816 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]); 1817 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq); 1818 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource); 1819 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456); 1820 1821 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm); 1822 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature); 1823 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature); 1824 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit); 1825 1826 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp); 1827 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp); 1828 1829 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge); 1830 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot); 1831 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx); 1832 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc); 1833 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem); 1834 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm); 1835 1836 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin); 1837 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm); 1838 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm); 1839 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm); 1840 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature); 1841 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk); 1842 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable); 1843 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev); 1844 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect); 1845 1846 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta); 1847 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta); 1848 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta); 1849 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved); 1850 1851 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]); 1852 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]); 1853 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]); 1854 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]); 1855 1856 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n", 1857 pptable->dBtcGbGfxPll.a, 1858 pptable->dBtcGbGfxPll.b, 1859 pptable->dBtcGbGfxPll.c); 1860 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n", 1861 pptable->dBtcGbGfxAfll.a, 1862 pptable->dBtcGbGfxAfll.b, 1863 pptable->dBtcGbGfxAfll.c); 1864 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n", 1865 pptable->dBtcGbSoc.a, 1866 pptable->dBtcGbSoc.b, 1867 pptable->dBtcGbSoc.c); 1868 1869 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n", 1870 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m, 1871 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b); 1872 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n", 1873 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m, 1874 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b); 1875 1876 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n", 1877 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a, 1878 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b, 1879 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c); 1880 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n", 1881 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a, 1882 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b, 1883 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c); 1884 1885 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]); 1886 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]); 1887 1888 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]); 1889 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]); 1890 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]); 1891 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]); 1892 1893 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]); 1894 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]); 1895 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]); 1896 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]); 1897 1898 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]); 1899 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]); 1900 1901 dev_info(smu->adev->dev, "XgmiDpmPstates\n"); 1902 for (i = 0; i < NUM_XGMI_LEVELS; i++) 1903 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]); 1904 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]); 1905 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]); 1906 1907 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin); 1908 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin); 1909 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp); 1910 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp); 1911 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp); 1912 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp); 1913 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis); 1914 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis); 1915 1916 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides); 1917 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n", 1918 pptable->ReservedEquation0.a, 1919 pptable->ReservedEquation0.b, 1920 pptable->ReservedEquation0.c); 1921 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n", 1922 pptable->ReservedEquation1.a, 1923 pptable->ReservedEquation1.b, 1924 pptable->ReservedEquation1.c); 1925 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n", 1926 pptable->ReservedEquation2.a, 1927 pptable->ReservedEquation2.b, 1928 pptable->ReservedEquation2.c); 1929 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n", 1930 pptable->ReservedEquation3.a, 1931 pptable->ReservedEquation3.b, 1932 pptable->ReservedEquation3.c); 1933 1934 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); 1935 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv); 1936 1937 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig); 1938 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1); 1939 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2); 1940 1941 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow); 1942 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh); 1943 1944 dev_info(smu->adev->dev, "Board Parameters:\n"); 1945 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); 1946 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); 1947 1948 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping); 1949 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping); 1950 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping); 1951 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping); 1952 1953 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask); 1954 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent); 1955 1956 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent); 1957 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset); 1958 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx); 1959 1960 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent); 1961 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset); 1962 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc); 1963 1964 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent); 1965 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset); 1966 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem); 1967 1968 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent); 1969 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset); 1970 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput); 1971 1972 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio); 1973 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity); 1974 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio); 1975 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity); 1976 1977 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled); 1978 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent); 1979 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq); 1980 1981 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled); 1982 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent); 1983 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq); 1984 1985 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled); 1986 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent); 1987 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq); 1988 1989 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled); 1990 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); 1991 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); 1992 1993 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) { 1994 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i); 1995 dev_info(smu->adev->dev, " .Enabled = %d\n", 1996 pptable->I2cControllers[i].Enabled); 1997 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n", 1998 pptable->I2cControllers[i].SlaveAddress); 1999 dev_info(smu->adev->dev, " .ControllerPort = %d\n", 2000 pptable->I2cControllers[i].ControllerPort); 2001 dev_info(smu->adev->dev, " .ControllerName = %d\n", 2002 pptable->I2cControllers[i].ControllerName); 2003 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n", 2004 pptable->I2cControllers[i].ThermalThrotter); 2005 dev_info(smu->adev->dev, " .I2cProtocol = %d\n", 2006 pptable->I2cControllers[i].I2cProtocol); 2007 dev_info(smu->adev->dev, " .Speed = %d\n", 2008 pptable->I2cControllers[i].Speed); 2009 } 2010 2011 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled); 2012 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth); 2013 2014 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower); 2015 2016 dev_info(smu->adev->dev, "XgmiLinkSpeed\n"); 2017 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2018 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]); 2019 dev_info(smu->adev->dev, "XgmiLinkWidth\n"); 2020 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2021 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]); 2022 dev_info(smu->adev->dev, "XgmiFclkFreq\n"); 2023 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2024 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]); 2025 dev_info(smu->adev->dev, "XgmiSocVoltage\n"); 2026 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) 2027 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]); 2028 2029 } 2030 2031 static bool arcturus_is_dpm_running(struct smu_context *smu) 2032 { 2033 int ret = 0; 2034 uint32_t feature_mask[2]; 2035 uint64_t feature_enabled; 2036 2037 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); 2038 if (ret) 2039 return false; 2040 2041 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0]; 2042 2043 return !!(feature_enabled & SMC_DPM_FEATURE); 2044 } 2045 2046 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable) 2047 { 2048 int ret = 0; 2049 2050 if (enable) { 2051 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) { 2052 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1); 2053 if (ret) { 2054 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n"); 2055 return ret; 2056 } 2057 } 2058 } else { 2059 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) { 2060 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0); 2061 if (ret) { 2062 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n"); 2063 return ret; 2064 } 2065 } 2066 } 2067 2068 return ret; 2069 } 2070 2071 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap, 2072 struct i2c_msg *msg, int num_msgs) 2073 { 2074 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 2075 struct smu_table_context *smu_table = &adev->smu.smu_table; 2076 struct smu_table *table = &smu_table->driver_table; 2077 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr; 2078 int i, j, r, c; 2079 u16 dir; 2080 2081 req = kzalloc(sizeof(*req), GFP_KERNEL); 2082 if (!req) 2083 return -ENOMEM; 2084 2085 req->I2CcontrollerPort = 0; 2086 req->I2CSpeed = I2C_SPEED_FAST_400K; 2087 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */ 2088 dir = msg[0].flags & I2C_M_RD; 2089 2090 for (c = i = 0; i < num_msgs; i++) { 2091 for (j = 0; j < msg[i].len; j++, c++) { 2092 SwI2cCmd_t *cmd = &req->SwI2cCmds[c]; 2093 2094 if (!(msg[i].flags & I2C_M_RD)) { 2095 /* write */ 2096 cmd->Cmd = I2C_CMD_WRITE; 2097 cmd->RegisterAddr = msg[i].buf[j]; 2098 } 2099 2100 if ((dir ^ msg[i].flags) & I2C_M_RD) { 2101 /* The direction changes. 2102 */ 2103 dir = msg[i].flags & I2C_M_RD; 2104 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK; 2105 } 2106 2107 req->NumCmds++; 2108 2109 /* 2110 * Insert STOP if we are at the last byte of either last 2111 * message for the transaction or the client explicitly 2112 * requires a STOP at this particular message. 2113 */ 2114 if ((j == msg[i].len - 1) && 2115 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) { 2116 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK; 2117 cmd->CmdConfig |= CMDCONFIG_STOP_MASK; 2118 } 2119 } 2120 } 2121 mutex_lock(&adev->smu.mutex); 2122 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true); 2123 mutex_unlock(&adev->smu.mutex); 2124 if (r) 2125 goto fail; 2126 2127 for (c = i = 0; i < num_msgs; i++) { 2128 if (!(msg[i].flags & I2C_M_RD)) { 2129 c += msg[i].len; 2130 continue; 2131 } 2132 for (j = 0; j < msg[i].len; j++, c++) { 2133 SwI2cCmd_t *cmd = &res->SwI2cCmds[c]; 2134 2135 msg[i].buf[j] = cmd->Data; 2136 } 2137 } 2138 r = num_msgs; 2139 fail: 2140 kfree(req); 2141 return r; 2142 } 2143 2144 static u32 arcturus_i2c_func(struct i2c_adapter *adap) 2145 { 2146 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 2147 } 2148 2149 2150 static const struct i2c_algorithm arcturus_i2c_algo = { 2151 .master_xfer = arcturus_i2c_xfer, 2152 .functionality = arcturus_i2c_func, 2153 }; 2154 2155 2156 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = { 2157 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN, 2158 .max_read_len = MAX_SW_I2C_COMMANDS, 2159 .max_write_len = MAX_SW_I2C_COMMANDS, 2160 .max_comb_1st_msg_len = 2, 2161 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2, 2162 }; 2163 2164 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control) 2165 { 2166 struct amdgpu_device *adev = to_amdgpu_device(control); 2167 int res; 2168 2169 control->owner = THIS_MODULE; 2170 control->class = I2C_CLASS_HWMON; 2171 control->dev.parent = &adev->pdev->dev; 2172 control->algo = &arcturus_i2c_algo; 2173 control->quirks = &arcturus_i2c_control_quirks; 2174 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 2175 2176 res = i2c_add_adapter(control); 2177 if (res) 2178 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 2179 2180 return res; 2181 } 2182 2183 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control) 2184 { 2185 i2c_del_adapter(control); 2186 } 2187 2188 static void arcturus_get_unique_id(struct smu_context *smu) 2189 { 2190 struct amdgpu_device *adev = smu->adev; 2191 uint32_t top32 = 0, bottom32 = 0, smu_version; 2192 uint64_t id; 2193 2194 if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) { 2195 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n"); 2196 return; 2197 } 2198 2199 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */ 2200 if (smu_version < 0x361700) { 2201 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n"); 2202 return; 2203 } 2204 2205 /* Get the SN to turn into a Unique ID */ 2206 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32); 2207 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32); 2208 2209 id = ((uint64_t)bottom32 << 32) | top32; 2210 adev->unique_id = id; 2211 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a 2212 * 16-digit HEX string for convenience and backwards-compatibility 2213 */ 2214 sprintf(adev->serial, "%llx", id); 2215 } 2216 2217 static int arcturus_set_df_cstate(struct smu_context *smu, 2218 enum pp_df_cstate state) 2219 { 2220 uint32_t smu_version; 2221 int ret; 2222 2223 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2224 if (ret) { 2225 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2226 return ret; 2227 } 2228 2229 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */ 2230 if (smu_version < 0x360F00) { 2231 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n"); 2232 return -EINVAL; 2233 } 2234 2235 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL); 2236 } 2237 2238 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en) 2239 { 2240 uint32_t smu_version; 2241 int ret; 2242 2243 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); 2244 if (ret) { 2245 dev_err(smu->adev->dev, "Failed to get smu version!\n"); 2246 return ret; 2247 } 2248 2249 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */ 2250 if (smu_version < 0x00361700) { 2251 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n"); 2252 return -EINVAL; 2253 } 2254 2255 if (en) 2256 return smu_cmn_send_smc_msg_with_param(smu, 2257 SMU_MSG_GmiPwrDnControl, 2258 1, 2259 NULL); 2260 2261 return smu_cmn_send_smc_msg_with_param(smu, 2262 SMU_MSG_GmiPwrDnControl, 2263 0, 2264 NULL); 2265 } 2266 2267 static const struct throttling_logging_label { 2268 uint32_t feature_mask; 2269 const char *label; 2270 } logging_label[] = { 2271 {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"}, 2272 {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"}, 2273 {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"}, 2274 {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"}, 2275 {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"}, 2276 {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"}, 2277 {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"}, 2278 }; 2279 static void arcturus_log_thermal_throttling_event(struct smu_context *smu) 2280 { 2281 int ret; 2282 int throttler_idx, throtting_events = 0, buf_idx = 0; 2283 struct amdgpu_device *adev = smu->adev; 2284 uint32_t throttler_status; 2285 char log_buf[256]; 2286 2287 ret = arcturus_get_smu_metrics_data(smu, 2288 METRICS_THROTTLER_STATUS, 2289 &throttler_status); 2290 if (ret) 2291 return; 2292 2293 memset(log_buf, 0, sizeof(log_buf)); 2294 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label); 2295 throttler_idx++) { 2296 if (throttler_status & logging_label[throttler_idx].feature_mask) { 2297 throtting_events++; 2298 buf_idx += snprintf(log_buf + buf_idx, 2299 sizeof(log_buf) - buf_idx, 2300 "%s%s", 2301 throtting_events > 1 ? " and " : "", 2302 logging_label[throttler_idx].label); 2303 if (buf_idx >= sizeof(log_buf)) { 2304 dev_err(adev->dev, "buffer overflow!\n"); 2305 log_buf[sizeof(log_buf) - 1] = '\0'; 2306 break; 2307 } 2308 } 2309 } 2310 2311 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n", 2312 log_buf); 2313 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, 2314 smu_cmn_get_indep_throttler_status(throttler_status, 2315 arcturus_throttler_map)); 2316 } 2317 2318 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu) 2319 { 2320 struct amdgpu_device *adev = smu->adev; 2321 uint32_t esm_ctrl; 2322 2323 /* TODO: confirm this on real target */ 2324 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); 2325 if ((esm_ctrl >> 15) & 0x1FFFF) 2326 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128); 2327 2328 return smu_v11_0_get_current_pcie_link_speed(smu); 2329 } 2330 2331 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, 2332 void **table) 2333 { 2334 struct smu_table_context *smu_table = &smu->smu_table; 2335 struct gpu_metrics_v1_3 *gpu_metrics = 2336 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; 2337 SmuMetrics_t metrics; 2338 int ret = 0; 2339 2340 ret = smu_cmn_get_metrics_table(smu, 2341 &metrics, 2342 true); 2343 if (ret) 2344 return ret; 2345 2346 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3); 2347 2348 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2349 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2350 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2351 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2352 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 2353 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2354 2355 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2356 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2357 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; 2358 2359 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 2360 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; 2361 2362 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2363 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2364 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2365 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency; 2366 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency; 2367 2368 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2369 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2370 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2371 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2372 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2373 2374 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2375 gpu_metrics->indep_throttle_status = 2376 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus, 2377 arcturus_throttler_map); 2378 2379 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; 2380 2381 gpu_metrics->pcie_link_width = 2382 smu_v11_0_get_current_pcie_link_width(smu); 2383 gpu_metrics->pcie_link_speed = 2384 arcturus_get_current_pcie_link_speed(smu); 2385 2386 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2387 2388 *table = (void *)gpu_metrics; 2389 2390 return sizeof(struct gpu_metrics_v1_3); 2391 } 2392 2393 static const struct pptable_funcs arcturus_ppt_funcs = { 2394 /* init dpm */ 2395 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, 2396 /* btc */ 2397 .run_btc = arcturus_run_btc, 2398 /* dpm/clk tables */ 2399 .set_default_dpm_table = arcturus_set_default_dpm_table, 2400 .populate_umd_state_clk = arcturus_populate_umd_state_clk, 2401 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range, 2402 .print_clk_levels = arcturus_print_clk_levels, 2403 .force_clk_levels = arcturus_force_clk_levels, 2404 .read_sensor = arcturus_read_sensor, 2405 .get_fan_speed_pwm = arcturus_get_fan_speed_pwm, 2406 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm, 2407 .get_power_profile_mode = arcturus_get_power_profile_mode, 2408 .set_power_profile_mode = arcturus_set_power_profile_mode, 2409 .set_performance_level = arcturus_set_performance_level, 2410 /* debug (internal used) */ 2411 .dump_pptable = arcturus_dump_pptable, 2412 .get_power_limit = arcturus_get_power_limit, 2413 .is_dpm_running = arcturus_is_dpm_running, 2414 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable, 2415 .i2c_init = arcturus_i2c_control_init, 2416 .i2c_fini = arcturus_i2c_control_fini, 2417 .get_unique_id = arcturus_get_unique_id, 2418 .init_microcode = smu_v11_0_init_microcode, 2419 .load_microcode = smu_v11_0_load_microcode, 2420 .fini_microcode = smu_v11_0_fini_microcode, 2421 .init_smc_tables = arcturus_init_smc_tables, 2422 .fini_smc_tables = smu_v11_0_fini_smc_tables, 2423 .init_power = smu_v11_0_init_power, 2424 .fini_power = smu_v11_0_fini_power, 2425 .check_fw_status = smu_v11_0_check_fw_status, 2426 /* pptable related */ 2427 .setup_pptable = arcturus_setup_pptable, 2428 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values, 2429 .check_fw_version = smu_v11_0_check_fw_version, 2430 .write_pptable = smu_cmn_write_pptable, 2431 .set_driver_table_location = smu_v11_0_set_driver_table_location, 2432 .set_tool_table_location = smu_v11_0_set_tool_table_location, 2433 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, 2434 .system_features_control = smu_v11_0_system_features_control, 2435 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 2436 .send_smc_msg = smu_cmn_send_smc_msg, 2437 .init_display_count = NULL, 2438 .set_allowed_mask = smu_v11_0_set_allowed_mask, 2439 .get_enabled_mask = smu_cmn_get_enabled_mask, 2440 .feature_is_enabled = smu_cmn_feature_is_enabled, 2441 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, 2442 .notify_display_change = NULL, 2443 .set_power_limit = smu_v11_0_set_power_limit, 2444 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks, 2445 .enable_thermal_alert = smu_v11_0_enable_thermal_alert, 2446 .disable_thermal_alert = smu_v11_0_disable_thermal_alert, 2447 .set_min_dcef_deep_sleep = NULL, 2448 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, 2449 .get_fan_control_mode = smu_v11_0_get_fan_control_mode, 2450 .set_fan_control_mode = smu_v11_0_set_fan_control_mode, 2451 .set_fan_speed_pwm = arcturus_set_fan_speed_pwm, 2452 .set_fan_speed_rpm = arcturus_set_fan_speed_rpm, 2453 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, 2454 .gfx_off_control = smu_v11_0_gfx_off_control, 2455 .register_irq_handler = smu_v11_0_register_irq_handler, 2456 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme, 2457 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc, 2458 .baco_is_support = smu_v11_0_baco_is_support, 2459 .baco_get_state = smu_v11_0_baco_get_state, 2460 .baco_set_state = smu_v11_0_baco_set_state, 2461 .baco_enter = smu_v11_0_baco_enter, 2462 .baco_exit = smu_v11_0_baco_exit, 2463 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq, 2464 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, 2465 .set_df_cstate = arcturus_set_df_cstate, 2466 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down, 2467 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event, 2468 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 2469 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, 2470 .get_gpu_metrics = arcturus_get_gpu_metrics, 2471 .gfx_ulv_control = smu_v11_0_gfx_ulv_control, 2472 .deep_sleep_control = smu_v11_0_deep_sleep_control, 2473 .get_fan_parameters = arcturus_get_fan_parameters, 2474 .interrupt_work = smu_v11_0_interrupt_work, 2475 .smu_handle_passthrough_sbr = smu_v11_0_handle_passthrough_sbr, 2476 .set_mp1_state = smu_cmn_set_mp1_state, 2477 }; 2478 2479 void arcturus_set_ppt_funcs(struct smu_context *smu) 2480 { 2481 smu->ppt_funcs = &arcturus_ppt_funcs; 2482 smu->message_map = arcturus_message_map; 2483 smu->clock_map = arcturus_clk_map; 2484 smu->feature_map = arcturus_feature_mask_map; 2485 smu->table_map = arcturus_table_map; 2486 smu->pwr_src_map = arcturus_pwr_src_map; 2487 smu->workload_map = arcturus_workload_map; 2488 } 2489