1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 /* Argument for PPSMC_MSG_GpuChangeState */ 27 enum gfx_change_state { 28 sGpuChangeState_D0Entry = 1, 29 sGpuChangeState_D3Entry, 30 }; 31 32 enum amdgpu_int_thermal_type { 33 THERMAL_TYPE_NONE, 34 THERMAL_TYPE_EXTERNAL, 35 THERMAL_TYPE_EXTERNAL_GPIO, 36 THERMAL_TYPE_RV6XX, 37 THERMAL_TYPE_RV770, 38 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 39 THERMAL_TYPE_EVERGREEN, 40 THERMAL_TYPE_SUMO, 41 THERMAL_TYPE_NI, 42 THERMAL_TYPE_SI, 43 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 44 THERMAL_TYPE_CI, 45 THERMAL_TYPE_KV, 46 }; 47 48 enum amdgpu_runpm_mode { 49 AMDGPU_RUNPM_NONE, 50 AMDGPU_RUNPM_PX, 51 AMDGPU_RUNPM_BOCO, 52 AMDGPU_RUNPM_BACO, 53 }; 54 55 struct amdgpu_ps { 56 u32 caps; /* vbios flags */ 57 u32 class; /* vbios flags */ 58 u32 class2; /* vbios flags */ 59 /* UVD clocks */ 60 u32 vclk; 61 u32 dclk; 62 /* VCE clocks */ 63 u32 evclk; 64 u32 ecclk; 65 bool vce_active; 66 enum amd_vce_level vce_level; 67 /* asic priv */ 68 void *ps_priv; 69 }; 70 71 struct amdgpu_dpm_thermal { 72 /* thermal interrupt work */ 73 struct work_struct work; 74 /* low temperature threshold */ 75 int min_temp; 76 /* high temperature threshold */ 77 int max_temp; 78 /* edge max emergency(shutdown) temp */ 79 int max_edge_emergency_temp; 80 /* hotspot low temperature threshold */ 81 int min_hotspot_temp; 82 /* hotspot high temperature critical threshold */ 83 int max_hotspot_crit_temp; 84 /* hotspot max emergency(shutdown) temp */ 85 int max_hotspot_emergency_temp; 86 /* memory low temperature threshold */ 87 int min_mem_temp; 88 /* memory high temperature critical threshold */ 89 int max_mem_crit_temp; 90 /* memory max emergency(shutdown) temp */ 91 int max_mem_emergency_temp; 92 /* was last interrupt low to high or high to low */ 93 bool high_to_low; 94 /* interrupt source */ 95 struct amdgpu_irq_src irq; 96 }; 97 98 struct amdgpu_clock_and_voltage_limits { 99 u32 sclk; 100 u32 mclk; 101 u16 vddc; 102 u16 vddci; 103 }; 104 105 struct amdgpu_clock_array { 106 u32 count; 107 u32 *values; 108 }; 109 110 struct amdgpu_clock_voltage_dependency_entry { 111 u32 clk; 112 u16 v; 113 }; 114 115 struct amdgpu_clock_voltage_dependency_table { 116 u32 count; 117 struct amdgpu_clock_voltage_dependency_entry *entries; 118 }; 119 120 union amdgpu_cac_leakage_entry { 121 struct { 122 u16 vddc; 123 u32 leakage; 124 }; 125 struct { 126 u16 vddc1; 127 u16 vddc2; 128 u16 vddc3; 129 }; 130 }; 131 132 struct amdgpu_cac_leakage_table { 133 u32 count; 134 union amdgpu_cac_leakage_entry *entries; 135 }; 136 137 struct amdgpu_phase_shedding_limits_entry { 138 u16 voltage; 139 u32 sclk; 140 u32 mclk; 141 }; 142 143 struct amdgpu_phase_shedding_limits_table { 144 u32 count; 145 struct amdgpu_phase_shedding_limits_entry *entries; 146 }; 147 148 struct amdgpu_uvd_clock_voltage_dependency_entry { 149 u32 vclk; 150 u32 dclk; 151 u16 v; 152 }; 153 154 struct amdgpu_uvd_clock_voltage_dependency_table { 155 u8 count; 156 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 157 }; 158 159 struct amdgpu_vce_clock_voltage_dependency_entry { 160 u32 ecclk; 161 u32 evclk; 162 u16 v; 163 }; 164 165 struct amdgpu_vce_clock_voltage_dependency_table { 166 u8 count; 167 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 168 }; 169 170 struct amdgpu_ppm_table { 171 u8 ppm_design; 172 u16 cpu_core_number; 173 u32 platform_tdp; 174 u32 small_ac_platform_tdp; 175 u32 platform_tdc; 176 u32 small_ac_platform_tdc; 177 u32 apu_tdp; 178 u32 dgpu_tdp; 179 u32 dgpu_ulv_power; 180 u32 tj_max; 181 }; 182 183 struct amdgpu_cac_tdp_table { 184 u16 tdp; 185 u16 configurable_tdp; 186 u16 tdc; 187 u16 battery_power_limit; 188 u16 small_power_limit; 189 u16 low_cac_leakage; 190 u16 high_cac_leakage; 191 u16 maximum_power_delivery_limit; 192 }; 193 194 struct amdgpu_dpm_dynamic_state { 195 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 196 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 197 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 198 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 199 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 200 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 201 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 202 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 203 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 204 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 205 struct amdgpu_clock_array valid_sclk_values; 206 struct amdgpu_clock_array valid_mclk_values; 207 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 208 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 209 u32 mclk_sclk_ratio; 210 u32 sclk_mclk_delta; 211 u16 vddc_vddci_delta; 212 u16 min_vddc_for_pcie_gen2; 213 struct amdgpu_cac_leakage_table cac_leakage_table; 214 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 215 struct amdgpu_ppm_table *ppm_table; 216 struct amdgpu_cac_tdp_table *cac_tdp_table; 217 }; 218 219 struct amdgpu_dpm_fan { 220 u16 t_min; 221 u16 t_med; 222 u16 t_high; 223 u16 pwm_min; 224 u16 pwm_med; 225 u16 pwm_high; 226 u8 t_hyst; 227 u32 cycle_delay; 228 u16 t_max; 229 u8 control_mode; 230 u16 default_max_fan_pwm; 231 u16 default_fan_output_sensitivity; 232 u16 fan_output_sensitivity; 233 bool ucode_fan_control; 234 }; 235 236 struct amdgpu_dpm { 237 struct amdgpu_ps *ps; 238 /* number of valid power states */ 239 int num_ps; 240 /* current power state that is active */ 241 struct amdgpu_ps *current_ps; 242 /* requested power state */ 243 struct amdgpu_ps *requested_ps; 244 /* boot up power state */ 245 struct amdgpu_ps *boot_ps; 246 /* default uvd power state */ 247 struct amdgpu_ps *uvd_ps; 248 /* vce requirements */ 249 u32 num_of_vce_states; 250 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 251 enum amd_vce_level vce_level; 252 enum amd_pm_state_type state; 253 enum amd_pm_state_type user_state; 254 enum amd_pm_state_type last_state; 255 enum amd_pm_state_type last_user_state; 256 u32 platform_caps; 257 u32 voltage_response_time; 258 u32 backbias_response_time; 259 void *priv; 260 u32 new_active_crtcs; 261 int new_active_crtc_count; 262 u32 current_active_crtcs; 263 int current_active_crtc_count; 264 struct amdgpu_dpm_dynamic_state dyn_state; 265 struct amdgpu_dpm_fan fan; 266 u32 tdp_limit; 267 u32 near_tdp_limit; 268 u32 near_tdp_limit_adjusted; 269 u32 sq_ramping_threshold; 270 u32 cac_leakage; 271 u16 tdp_od_limit; 272 u32 tdp_adjustment; 273 u16 load_line_slope; 274 bool power_control; 275 /* special states active */ 276 bool thermal_active; 277 bool uvd_active; 278 bool vce_active; 279 /* thermal handling */ 280 struct amdgpu_dpm_thermal thermal; 281 /* forced levels */ 282 enum amd_dpm_forced_level forced_level; 283 }; 284 285 enum ip_power_state { 286 POWER_STATE_UNKNOWN, 287 POWER_STATE_ON, 288 POWER_STATE_OFF, 289 }; 290 291 /* Used to mask smu debug modes */ 292 #define SMU_DEBUG_HALT_ON_ERROR 0x1 293 294 #define MAX_SMU_I2C_BUSES 2 295 296 struct amdgpu_smu_i2c_bus { 297 struct i2c_adapter adapter; 298 struct amdgpu_device *adev; 299 int port; 300 struct mutex mutex; 301 }; 302 303 struct config_table_setting 304 { 305 uint16_t gfxclk_average_tau; 306 uint16_t socclk_average_tau; 307 uint16_t uclk_average_tau; 308 uint16_t gfx_activity_average_tau; 309 uint16_t mem_activity_average_tau; 310 uint16_t socket_power_average_tau; 311 uint16_t apu_socket_power_average_tau; 312 uint16_t fclk_average_tau; 313 }; 314 315 struct amdgpu_pm { 316 struct mutex mutex; 317 u32 current_sclk; 318 u32 current_mclk; 319 u32 default_sclk; 320 u32 default_mclk; 321 struct amdgpu_i2c_chan *i2c_bus; 322 bool bus_locked; 323 /* internal thermal controller on rv6xx+ */ 324 enum amdgpu_int_thermal_type int_thermal_type; 325 struct device *int_hwmon_dev; 326 /* fan control parameters */ 327 bool no_fan; 328 u8 fan_pulses_per_revolution; 329 u8 fan_min_rpm; 330 u8 fan_max_rpm; 331 /* dpm */ 332 bool dpm_enabled; 333 bool sysfs_initialized; 334 struct amdgpu_dpm dpm; 335 const struct firmware *fw; /* SMC firmware */ 336 uint32_t fw_version; 337 uint32_t pcie_gen_mask; 338 uint32_t pcie_mlw_mask; 339 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 340 uint32_t smu_prv_buffer_size; 341 struct amdgpu_bo *smu_prv_buffer; 342 bool ac_power; 343 /* powerplay feature */ 344 uint32_t pp_feature; 345 346 /* Used for I2C access to various EEPROMs on relevant ASICs */ 347 struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES]; 348 struct i2c_adapter *ras_eeprom_i2c_bus; 349 struct i2c_adapter *fru_eeprom_i2c_bus; 350 struct list_head pm_attr_list; 351 352 atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; 353 354 /* 355 * 0 = disabled (default), otherwise enable corresponding debug mode 356 */ 357 uint32_t smu_debug_mask; 358 359 bool pp_force_state_enabled; 360 361 struct mutex stable_pstate_ctx_lock; 362 struct amdgpu_ctx *stable_pstate_ctx; 363 364 struct config_table_setting config_table; 365 /* runtime mode */ 366 enum amdgpu_runpm_mode rpm_mode; 367 }; 368 369 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 370 void *data, uint32_t *size); 371 372 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 373 uint32_t block_type, bool gate); 374 375 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 376 377 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 378 379 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, 380 uint32_t pstate); 381 382 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, 383 enum PP_SMC_POWER_PROFILE type, 384 bool en); 385 386 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); 387 388 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); 389 390 bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); 391 392 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); 393 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); 394 395 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, 396 enum pp_mp1_state mp1_state); 397 398 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); 399 400 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); 401 402 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); 403 404 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, 405 uint32_t cstate); 406 407 int amdgpu_dpm_allow_xgmi_power_down(struct amdgpu_device *adev, bool en); 408 409 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); 410 411 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, 412 uint32_t msg_id); 413 414 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, 415 bool acquire); 416 417 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); 418 419 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev); 420 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 421 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 422 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 423 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 424 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 425 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); 426 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size); 427 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, 428 enum pp_clock_type type, 429 uint32_t *min, 430 uint32_t *max); 431 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, 432 enum pp_clock_type type, 433 uint32_t min, 434 uint32_t max); 435 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); 436 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 437 uint64_t event_arg); 438 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value); 439 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value); 440 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value); 441 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 442 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); 443 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, 444 enum gfx_change_state state); 445 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, 446 void *umc_ecc); 447 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, 448 uint32_t idx); 449 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); 450 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, 451 enum amd_pm_state_type state); 452 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); 453 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, 454 enum amd_dpm_forced_level level); 455 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, 456 struct pp_states_info *states); 457 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, 458 enum amd_pp_task task_id, 459 enum amd_pm_state_type *user_state); 460 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); 461 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, 462 uint32_t type, 463 long *input, 464 uint32_t size); 465 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, 466 uint32_t type, 467 long *input, 468 uint32_t size); 469 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, 470 enum pp_clock_type type, 471 char *buf); 472 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, 473 enum pp_clock_type type, 474 char *buf, 475 int *offset); 476 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, 477 uint64_t ppfeature_masks); 478 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); 479 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, 480 enum pp_clock_type type, 481 uint32_t mask); 482 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); 483 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); 484 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); 485 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); 486 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, 487 char *buf); 488 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, 489 long *input, uint32_t size); 490 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); 491 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, 492 uint32_t *fan_mode); 493 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, 494 uint32_t speed); 495 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, 496 uint32_t *speed); 497 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, 498 uint32_t *speed); 499 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, 500 uint32_t speed); 501 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, 502 uint32_t mode); 503 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, 504 uint32_t *limit, 505 enum pp_power_limit_level pp_limit_level, 506 enum pp_power_type power_type); 507 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, 508 uint32_t limit); 509 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); 510 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, 511 struct seq_file *m); 512 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, 513 void **addr, 514 size_t *size); 515 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); 516 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, 517 const char *buf, 518 size_t size); 519 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); 520 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); 521 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, 522 const struct amd_pp_display_configuration *input); 523 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, 524 enum amd_pp_clock_type type, 525 struct amd_pp_clocks *clocks); 526 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, 527 struct amd_pp_simple_clock_info *clocks); 528 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, 529 enum amd_pp_clock_type type, 530 struct pp_clock_levels_with_latency *clocks); 531 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, 532 enum amd_pp_clock_type type, 533 struct pp_clock_levels_with_voltage *clocks); 534 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, 535 void *clock_ranges); 536 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, 537 struct pp_display_clock_request *clock); 538 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, 539 struct amd_pp_clock_info *clocks); 540 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); 541 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, 542 uint32_t count); 543 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, 544 uint32_t clock); 545 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, 546 uint32_t clock); 547 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, 548 uint32_t clock); 549 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, 550 bool disable_memory_clock_switch); 551 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, 552 struct pp_smu_nv_clock_table *max_clocks); 553 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, 554 unsigned int *clock_values_in_khz, 555 unsigned int *num_states); 556 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, 557 struct dpm_clocks *clock_table); 558 #endif 559